OV - exec - Function hypre_IJMatrixInitializeParCSR._omp

	Function: hypre_IJMatrixInitializeParCSR._omp_fn.0	Module: exec	Source: IJMatrix_parcsr.c:302-307	Coverage (incl. loops): 0.02% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 302 - 307

--------------------------------------------------------------------------------

302: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

303: #endif

304:          for (i=0; i < local_num_rows; i++)

305:          {

306: 	    indx_diag[i] = diag_i[i];

307: 	    indx_offd[i] = offd_i[i];

0x503840 STP	X29, X30, [SP, #976]!

0x503844 ADD	X29, SP, #0

0x503848 STP	X19, X20, [SP, #16]

0x50384c ORR	X20, XZR, X0

0x503850 STR	X21, [SP, #32]

0x503854 LDR	X21, [X0]

0x503858 BL	4101b0

0x50385c SBFM	X19, X0, #0, #31

0x503860 BL	4101c0

0x503864 SBFM	X3, X0, #0, #31

0x503868 SDIV	X2, X21, X19

0x50386c MSUB	X1, X2, X19, X21

0x503870 CMP	X3, X1

0x503874 B.LT	50393c

0x503878 MUL	X0, X2, X3

0x50387c ADD	X4, X1, X0

0x503880 ADD	X14, X2, X4

0x503884 CMP	X4, X14

0x503888 B.GE	50392c

0x50388c LDP	X12, X8, [X20, #24]

0x503890 ADD	X5, X1, #1

0x503894 CNTB	X10, ALL

0x503898 ADD	X13, X5, X0

0x50389c ADD	X18, X10, X4,LSL #3

0x5038a0 SUB	X30, X10, #16

0x5038a4 UBFM	X6, X4, #61, #60

0x5038a8 LDP	X9, X15, [X20, #8]

0x5038ac ADD	X11, X12, X13,LSL #3

0x5038b0 ADD	X17, X8, X18

0x5038b4 ADD	X21, X8, X13,LSL #3

0x5038b8 ADD	X7, X8, X4,LSL #3

0x5038bc ADD	X20, X15, X4,LSL #3

0x5038c0 ADD	X10, X9, X18

0x5038c4 ADD	X19, X9, X13,LSL #3

0x5038c8 ADD	X5, X9, X4,LSL #3

0x5038cc SUB	X16, X20, X11

0x5038d0 SUB	X3, X20, X21

0x5038d4 CMP	X3, X16

0x5038d8 SUB	X1, X20, X19

0x5038dc CSEL	X0, X3, X16, #9

0x5038e0 SUB	X13, X5, X11

0x5038e4 CMP	X1, X13

0x5038e8 CSEL	X18, X1, X13, #9

0x5038ec CMP	X10, X7

0x5038f0 CCMP	X17, X5, #0, #8

0x5038f4 CCMP	X0, X30, #0, #9

0x5038f8 CCMP	X18, X30, #0, #8

0x5038fc B.LS	503948

0x503900 MOVZ	X30, #0

0x503904 ADD	X14, X12, X6

0x503908 WHILELO	P7.D, XZR, X2

0x50390c CNTD	X4, ALL

(3012) 0x503910 LD1D	{Z30.D}, P7/Z, [X14, X30,LSL #3]

(3012) 0x503914 ST1D	{Z30.D}, P7, [X5, X30,LSL #3]

(3012) 0x503918 LD1D	{Z31.D}, P7/Z, [X7, X30,LSL #3]

(3012) 0x50391c ST1D	{Z31.D}, P7, [X20, X30,LSL #3]

(3012) 0x503920 ADD	X30, X30, X4

(3012) 0x503924 WHILELO	P7.D, X30, X2

(3012) 0x503928 B.NE	503910

0x50392c LDR	X21, [SP, #32]

0x503930 LDP	X19, X20, [SP, #16]

0x503934 LDP	X29, X30, [SP], #48

0x503938 RET

0x50393c ADD	X2, X2, #1

0x503940 MOVZ	X1, #0

0x503944 B	503878

0x503948 SUB	X2, X14, X4

0x50394c ANDS	X6, X2, #0x7

0x503950 B.EQ	503a18

0x503954 CMP	X6, #1

0x503958 B.EQ	5039fc

0x50395c CMP	X6, #2

0x503960 B.EQ	5039e8

0x503964 CMP	X6, #3

0x503968 B.EQ	5039d4

0x50396c CMP	X6, #4

0x503970 B.EQ	5039c0

0x503974 CMP	X6, #5

0x503978 B.EQ	5039ac

0x50397c CMP	X6, #6

0x503980 B.EQ	503998

0x503984 LDR	X20, [X12, X4,LSL #3]

0x503988 STR	X20, [X9, X4,LSL #3]

0x50398c LDR	X11, [X8, X4,LSL #3]

0x503990 STR	X11, [X15, X4,LSL #3]

0x503994 ADD	X4, X4, #1

0x503998 LDR	X21, [X12, X4,LSL #3]

0x50399c STR	X21, [X9, X4,LSL #3]

0x5039a0 LDR	X16, [X8, X4,LSL #3]

0x5039a4 STR	X16, [X15, X4,LSL #3]

0x5039a8 ADD	X4, X4, #1

0x5039ac LDR	X17, [X12, X4,LSL #3]

0x5039b0 STR	X17, [X9, X4,LSL #3]

0x5039b4 LDR	X7, [X8, X4,LSL #3]

0x5039b8 STR	X7, [X15, X4,LSL #3]

0x5039bc ADD	X4, X4, #1

0x5039c0 LDR	X19, [X12, X4,LSL #3]

0x5039c4 STR	X19, [X9, X4,LSL #3]

0x5039c8 LDR	X3, [X8, X4,LSL #3]

0x5039cc STR	X3, [X15, X4,LSL #3]

0x5039d0 ADD	X4, X4, #1

0x5039d4 LDR	X10, [X12, X4,LSL #3]

0x5039d8 STR	X10, [X9, X4,LSL #3]

0x5039dc LDR	X5, [X8, X4,LSL #3]

0x5039e0 STR	X5, [X15, X4,LSL #3]

0x5039e4 ADD	X4, X4, #1

0x5039e8 LDR	X0, [X12, X4,LSL #3]

0x5039ec STR	X0, [X9, X4,LSL #3]

0x5039f0 LDR	X1, [X8, X4,LSL #3]

0x5039f4 STR	X1, [X15, X4,LSL #3]

0x5039f8 ADD	X4, X4, #1

0x5039fc LDR	X13, [X12, X4,LSL #3]

0x503a00 STR	X13, [X9, X4,LSL #3]

0x503a04 LDR	X18, [X8, X4,LSL #3]

0x503a08 STR	X18, [X15, X4,LSL #3]

0x503a0c ADD	X4, X4, #1

0x503a10 CMP	X14, X4

0x503a14 B.EQ	50392c

(3011) 0x503a18 LDR	X30, [X12, X4,LSL #3]

(3011) 0x503a1c ADD	X20, X4, #1

(3011) 0x503a20 ADD	X11, X4, #2

(3011) 0x503a24 ADD	X6, X4, #3

(3011) 0x503a28 ADD	X21, X4, #4

(3011) 0x503a2c ADD	X16, X4, #5

(3011) 0x503a30 ADD	X2, X4, #6

(3011) 0x503a34 ADD	X17, X4, #7

(3011) 0x503a38 STR	X30, [X9, X4,LSL #3]

(3011) 0x503a3c LDR	X7, [X8, X4,LSL #3]

(3011) 0x503a40 STR	X7, [X15, X4,LSL #3]

(3011) 0x503a44 ADD	X4, X4, #8

(3011) 0x503a48 LDR	X19, [X12, X20,LSL #3]

(3011) 0x503a4c STR	X19, [X9, X20,LSL #3]

(3011) 0x503a50 LDR	X3, [X8, X20,LSL #3]

(3011) 0x503a54 STR	X3, [X15, X20,LSL #3]

(3011) 0x503a58 LDR	X10, [X12, X11,LSL #3]

(3011) 0x503a5c STR	X10, [X9, X11,LSL #3]

(3011) 0x503a60 LDR	X5, [X8, X11,LSL #3]

(3011) 0x503a64 STR	X5, [X15, X11,LSL #3]

(3011) 0x503a68 LDR	X0, [X12, X6,LSL #3]

(3011) 0x503a6c STR	X0, [X9, X6,LSL #3]

(3011) 0x503a70 LDR	X1, [X8, X6,LSL #3]

(3011) 0x503a74 STR	X1, [X15, X6,LSL #3]

(3011) 0x503a78 LDR	X13, [X12, X21,LSL #3]

(3011) 0x503a7c STR	X13, [X9, X21,LSL #3]

(3011) 0x503a80 LDR	X18, [X8, X21,LSL #3]

(3011) 0x503a84 STR	X18, [X15, X21,LSL #3]

(3011) 0x503a88 LDR	X30, [X12, X16,LSL #3]

(3011) 0x503a8c STR	X30, [X9, X16,LSL #3]

(3011) 0x503a90 LDR	X20, [X8, X16,LSL #3]

(3011) 0x503a94 STR	X20, [X15, X16,LSL #3]

(3011) 0x503a98 LDR	X6, [X12, X2,LSL #3]

(3011) 0x503a9c STR	X6, [X9, X2,LSL #3]

(3011) 0x503aa0 LDR	X11, [X8, X2,LSL #3]

(3011) 0x503aa4 STR	X11, [X15, X2,LSL #3]

(3011) 0x503aa8 LDR	X21, [X12, X17,LSL #3]

(3011) 0x503aac STR	X21, [X9, X17,LSL #3]

(3011) 0x503ab0 LDR	X16, [X8, X17,LSL #3]

(3011) 0x503ab4 STR	X16, [X15, X17,LSL #3]

(3011) 0x503ab8 CMP	X14, X4

(3011) 0x503abc B.NE	503a18

0x503ac0 B	50392c

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_IJMatrixInitializeParCSR	IJMatrix_parcsr.c:326	exec
○	HYPRE_IJMatrixInitialize	HYPRE_IJMatrix.c:292	exec
○	BuildIJLaplacian27pt	amg.c:2262	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Source Location	Module
►86.67+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►13.33+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_IJMatrixInitializeParCSR	IJMatrix_parcsr.c:326	exec
○	HYPRE_IJMatrixInitialize	HYPRE_IJMatrix.c:292	exec
○	BuildIJLaplacian27pt	amg.c:2262	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Source Location	Module
►70.00+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►30.00+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_IJMatrixInitializeParCSR	IJMatrix_parcsr.c:326	exec
○	HYPRE_IJMatrixInitialize	HYPRE_IJMatrix.c:292	exec
○	BuildIJLaplacian27pt	amg.c:2262	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Source Location	Module
►93.33+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►6.67+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_IJMatrixInitializeParCSR	IJMatrix_parcsr.c:326	exec
○	HYPRE_IJMatrixInitialize	HYPRE_IJMatrix.c:292	exec
○	BuildIJLaplacian27pt	amg.c:2262	exec
○	main	amg.c:274	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	IJMatrix_parcsr.c:302-307
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:302-307.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 15.25 cycles (1.31x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:302
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:302

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	112
nb uops	112
loop length	448
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.00	8.00	15.50	15.50	15.50	15.50	0.00	0.00	0.00	0.00	12.50	12.17	12.33	8.50	8.50
cycles	8.00	8.00	15.50	15.50	15.50	15.50	0.00	0.00	0.00	0.00	12.50	12.17	12.33	8.50	8.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	14.00
Dispatch	15.50
DIV/SQRT	5.00-20.00
Overall L1	15.50-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	28%
load	26%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	25%
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 503840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X3, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X2, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
MSUB X1, X2, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 50393c <hypre_IJMatrixInitializeParCSR._omp_fn.0+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X0, X2, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X4, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X14, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X4, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 50392c <hypre_IJMatrixInitializeParCSR._omp_fn.0+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X8, [X20, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X5, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CNTB X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X13, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X10, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X30, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X9, X15, [X20, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X11, X12, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X8, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X21, X8, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X8, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X15, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X10, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X9, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X9, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X16, X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X3, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X1, X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL X0, X3, X16, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X13, X5, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X18, X1, X13, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X10, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X17, X5, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X0, X30, #0, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X18, X30, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B.LS 503948 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
WHILELO P7.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B 503878 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X2, X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X6, X2, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 503a18 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5039fc <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5039e8 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5039d4 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5039c0 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5039ac <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 503998 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X11, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X21, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X16, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X17, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X7, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X19, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X19, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X3, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X10, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X18, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 50392c <hypre_IJMatrixInitializeParCSR._omp_fn.0+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 50392c <hypre_IJMatrixInitializeParCSR._omp_fn.0+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	IJMatrix_parcsr.c:302-307
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:302-307.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 15.25 cycles (1.31x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:302
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c:302

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	112
nb uops	112
loop length	448
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.00 cycles
front end	14.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.00	8.00	15.50	15.50	15.50	15.50	0.00	0.00	0.00	0.00	12.50	12.17	12.33	8.50	8.50
cycles	8.00	8.00	15.50	15.50	15.50	15.50	0.00	0.00	0.00	0.00	12.50	12.17	12.33	8.50	8.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	14.00
Dispatch	15.50
DIV/SQRT	5.00-20.00
Overall L1	15.50-20.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	28%
load	26%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	25%
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 503840

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #976]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X21, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
BL 4101b0 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X19, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
BL 4101c0 <@plt_start@+0x1a0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X3, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SDIV X2, X21, X19	1	0	0	0	0	1	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
MSUB X1, X2, X19, X21	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
CMP X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 50393c <hypre_IJMatrixInitializeParCSR._omp_fn.0+0xfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X0, X2, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
ADD X4, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X14, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X4, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 50392c <hypre_IJMatrixInitializeParCSR._omp_fn.0+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X8, [X20, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X5, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CNTB X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X13, X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X10, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X30, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X6, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X9, X15, [X20, #8]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X11, X12, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X8, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X21, X8, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X8, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X15, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X10, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X9, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X9, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X16, X20, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X3, X20, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X3, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X1, X20, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CSEL X0, X3, X16, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SUB X13, X5, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X1, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X18, X1, X13, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X10, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X17, X5, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X0, X30, #0, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CCMP X18, X30, #0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B.LS 503948 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x108>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X30, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X12, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
WHILELO P7.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
CNTD X4, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X21, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #48	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X2, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
B 503878 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x38>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X2, X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X6, X2, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 503a18 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5039fc <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5039e8 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5039d4 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5039c0 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5039ac <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X6, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 503998 <hypre_IJMatrixInitializeParCSR._omp_fn.0+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X20, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X11, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X21, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X16, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X17, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X7, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X7, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X19, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X19, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X3, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X10, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X10, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X5, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X1, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X13, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X8, X4,LSL #3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X18, [X15, X4,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.EQ 50392c <hypre_IJMatrixInitializeParCSR._omp_fn.0+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 50392c <hypre_IJMatrixInitializeParCSR._omp_fn.0+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0			5.66	0	4.76	0	11.23	0	19.41	0	16.8	0	21.01	0	36.81	0	31.02	0	81.35	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.055000003427267	0.015891391783953
1x2
1x4	3	5.66	5.66	4	0.015000000596046	0.009482198394835
1x8	6	4.76	4.76	8	0.025000000372529	0.018677575513721
1x16	10	11.23	11.23	16	0.010000000707805	0.0093160420656204
1x24	7	19.41	19.41	24	0.014999999664724	0.0056749293580651
1x32	12	16.8	16.8	32	0.0099999997764826	0.0070075336843729
1x40	14	21.01	21.01	40	0.0099999997764826	0.0059265070594847
1x48	10	36.81	36.81	48	0.0050000003539026	0.0033719057682902
1x56	13	31.02	31.02	56	0.010000000707805	0.0040665143169463
1x64	6	81.35	81.35	64	0.0049999998882413	0.0015220692148432

Name	Coverage (%)	Time (s)
▼hypre_IJMatrixInitializeParCSR._omp_fn.0–	0.02	0.06
○Loop 3012 - IJMatrix_parcsr.c:306-307 - exec	0.02	0.06
○Loop 3011 - IJMatrix_parcsr.c:306-307 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency