OV - exec - Function hypre_CSRMatrixMultiply._omp

	Function: hypre_CSRMatrixMultiply._omp_fn.0	Module: exec	Source: csr_matop.c:185-302 [...]	Coverage (incl. loops): 2.75% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 185 - 302

--------------------------------------------------------------------------------

185: #pragma omp parallel private(ia, ib, ic, ja, jb, num_nonzeros, row_start, counter, a_entry, b_entry)

[...]

192:     ii = hypre_GetThreadNum();

193:     num_threads = hypre_NumActiveThreads();

194:

195:    size = nrows_A/num_threads;

196:    rest = nrows_A - size*num_threads;

197:     if (ii < rest)

198:     {

199:        ns = ii*size+ii;

200:        ne = (ii+1)*size+ii+1;

201:     }

202:     else

203:     {

204:        ns = ii*size+rest;

205:        ne = (ii+1)*size+rest;

206:     }

207:

208:     B_marker = hypre_CTAlloc(HYPRE_Int, ncols_B);

209:

210:     for (ib = 0; ib < ncols_B; ib++)

211:       B_marker[ib] = -1;

212:

213:     num_nonzeros = 0;

214:     for (ic = ns; ic < ne; ic++)

215:     {

216:         C_i[ic] = num_nonzeros;

217: 	if (allsquare)

218:         {

219:            B_marker[ic] = ic;

220:            num_nonzeros++;

221:         }

222: 	for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

223: 	{

224: 	   ja = A_j[ia];

225: 	   for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

226: 	   {

227: 	      jb = B_j[ib];

228: 	      if (B_marker[jb] != ic)

229: 	      {

230: 	 	 B_marker[jb] = ic;

231: 		 num_nonzeros++;

232: 	      }

233: 	   }

234:    	}

235:    }

236:    jj_count[ii] = num_nonzeros;

237:

238: #ifdef HYPRE_USING_OPENMP

239: #pragma omp barrier

240: #endif

241:

242:     if (ii)

243:     {

244:        jj = jj_count[0];

245:        for (i1 = 1; i1 < ii; i1++)

246:           jj += jj_count[i1];

247:

248:        for (i1 = ns; i1 < ne; i1++)

249:           C_i[i1] += jj;

250:     }

251:     else

252:     {

253:        C_i[nrows_A] = 0;

254:        for (i1 = 0; i1 < num_threads; i1++)

255:           C_i[nrows_A] += jj_count[i1];

256:

257:        C = hypre_CSRMatrixCreate(nrows_A, ncols_B, C_i[nrows_A]);

258:        hypre_CSRMatrixI(C) = C_i;

259:        hypre_CSRMatrixInitialize(C);

260:        C_j = hypre_CSRMatrixJ(C);

261:        C_data = hypre_CSRMatrixData(C);

262:     }

263:

264: #ifdef HYPRE_USING_OPENMP

265: #pragma omp barrier

266: #endif

267:

268:    for (ib = 0; ib < ncols_B; ib++)

269:       B_marker[ib] = -1;

270:

271:    counter = C_i[ns];

272:    for (ic = ns; ic < ne; ic++)

273:    {

274:       row_start = C_i[ic];

275:       if (allsquare)

276:       {

277:          B_marker[ic] = counter;

278:          C_data[counter] = 0;

279:          C_j[counter] = ic;

280:          counter++;

281:       }

282:       for (ia = A_i[ic]; ia < A_i[ic+1]; ia++)

283:       {

284: 	 ja = A_j[ia];

285: 	 a_entry = A_data[ia];

286: 	 for (ib = B_i[ja]; ib < B_i[ja+1]; ib++)

287: 	 {

288: 	    jb = B_j[ib];

289: 	    b_entry = B_data[ib];

290: 	    if (B_marker[jb] < row_start)

291: 	    {

292: 		B_marker[jb] = counter;

293: 		C_j[B_marker[jb]] = jb;

294: 		C_data[B_marker[jb]] = a_entry*b_entry;

295: 		counter++;

296: 	    }

297: 	    else

298: 		C_data[B_marker[jb]] += a_entry*b_entry;

299: 	}

300:       }

301:    }

302:    hypre_TFree(B_marker);

0x516a20 STP	X29, X30, [SP, #848]!

0x516a24 ORR	X10, XZR, X0

0x516a28 ADD	X29, SP, #0

0x516a2c STP	X19, X20, [SP, #16]

0x516a30 STP	X21, X22, [SP, #32]

0x516a34 STP	X23, X24, [SP, #48]

0x516a38 STP	X25, X26, [SP, #64]

0x516a3c STP	X27, X28, [SP, #80]

0x516a40 LDR	X7, [X10, #80]

0x516a44 LDP	X26, X19, [X0, #16]

0x516a48 LDP	X28, X8, [X0]

0x516a4c LDP	X21, X25, [X0, #32]

0x516a50 LDP	X20, X0, [X0, #48]

0x516a54 LDP	X23, X22, [X10, #96]

0x516a58 STP	X0, X19, [SP, #120]

0x516a5c STP	X10, X7, [SP, #144]

0x516a60 STR	X8, [SP, #160]

0x516a64 BL	52c0a0

0x516a68 STR	X0, [SP, #136]

0x516a6c BL	52c080

0x516a70 SDIV	X2, X19, X0

0x516a74 LDP	X11, X3, [SP, #136]

0x516a78 ORR	X12, XZR, X0

0x516a7c LDP	X4, X5, [SP, #152]

0x516a80 MUL	X27, X11, X2

0x516a84 MSUB	X1, X2, X0, X19

0x516a88 ADD	X6, X2, X27

0x516a8c CMP	X11, X1

0x516a90 B.GE	51714c

0x516a94 ADD	X9, X11, X6

0x516a98 ADD	X27, X11, X27

0x516a9c ADD	X24, X9, #1

0x516aa0 LDR	X0, [SP, #120]

0x516aa4 MOVZ	X1, #8

0x516aa8 STP	X4, X5, [SP, #136]

0x516aac STP	X12, X11, [SP, #152]

0x516ab0 STR	X3, [SP, #168]

0x516ab4 BL	529428

0x516ab8 LDR	X13, [SP, #120]

0x516abc ORR	X19, XZR, X0

0x516ac0 LDP	X18, X8, [SP, #136]

0x516ac4 LDP	X7, X12, [SP, #152]

0x516ac8 LDR	X10, [SP, #168]

0x516acc CMP	X13, #0

0x516ad0 B.LE	516af8

0x516ad4 UBFM	X2, X13, #61, #60

0x516ad8 MOVZ	W1, #255

0x516adc STP	X18, X8, [SP, #136]

0x516ae0 STP	X7, X12, [SP, #152]

0x516ae4 STR	X10, [SP, #168]

0x516ae8 BL	410340

0x516aec LDR	X10, [SP, #168]

0x516af0 LDP	X18, X8, [SP, #136]

0x516af4 LDP	X7, X12, [SP, #152]

0x516af8 ORR	X4, XZR, X27

0x516afc MOVZ	X17, #0

0x516b00 ADD	X15, X8, #8

0x516b04 CMP	X27, X24

0x516b08 B.GE	516b94

(3208) 0x516b0c STR	X17, [X18, X4,LSL #3]

(3208) 0x516b10 CBZ	X23, 516b1c

(3208) 0x516b14 ADD	X17, X17, #1

(3208) 0x516b18 STR	X4, [X19, X4,LSL #3]

(3208) 0x516b1c LDR	X14, [X8, X4,LSL #3]

(3208) 0x516b20 LDR	X9, [X15, X4,LSL #3]

(3208) 0x516b24 CMP	X14, X9

(3208) 0x516b28 B.GE	516b88

  (3209) 0x516b2c LDR	X30, [X26, X14,LSL #3]

  (3209) 0x516b30 UBFM	X0, X30, #61, #60

  (3209) 0x516b34 ADD	X2, X0, #8

  (3209) 0x516b38 LDR	X1, [X25, X0]

  (3209) 0x516b3c ADD	X11, X25, X2

  (3209) 0x516b40 LDR	X3, [X25, X2]

  (3209) 0x516b44 CMP	X1, X3

  (3209) 0x516b48 B.GE	516b7c

    (3210) 0x516b4c LDR	X16, [X20, X1,LSL #3]

    (3210) 0x516b50 UBFM	X5, X16, #61, #60

    (3210) 0x516b54 LDR	X6, [X19, X5]

    (3210) 0x516b58 CMP	X4, X6

    (3210) 0x516b5c B.EQ	516e84

    (3210) 0x516b60 STR	X4, [X19, X5]

    (3210) 0x516b64 ADD	X1, X1, #1

    (3210) 0x516b68 ADD	X17, X17, #1

    (3210) 0x516b6c LDR	X3, [X11]

    (3210) 0x516b70 CMP	X1, X3

    (3210) 0x516b74 B.LT	516b4c

  (3209) 0x516b78 LDR	X9, [X15, X4,LSL #3]

  (3209) 0x516b7c ADD	X14, X14, #1

  (3209) 0x516b80 CMP	X14, X9

  (3209) 0x516b84 B.LT	516b2c

(3208) 0x516b88 ADD	X4, X4, #1

(3208) 0x516b8c CMP	X24, X4

(3208) 0x516b90 B.NE	516b0c

0x516b94 STR	X17, [X22, X12,LSL #3]

0x516b98 STP	X12, X18, [SP, #136]

0x516b9c STP	X8, X7, [SP, #152]

0x516ba0 STR	X10, [SP, #168]

0x516ba4 BL	410120

0x516ba8 LDP	X11, X7, [SP, #136]

0x516bac LDR	X8, [SP, #152]

0x516bb0 LDR	X10, [SP, #168]

0x516bb4 CBZ	X11, 516e94

0x516bb8 STR	D15, [SP, #96]

0x516bbc LDR	D15, [X22]

0x516bc0 CMP	X11, #1

0x516bc4 B.LE	516c84

0x516bc8 CNTH	X17, ALL

0x516bcc SUB	X30, X11, #2

0x516bd0 ADD	X0, X17, #7

0x516bd4 SUB	X2, X11, #1

0x516bd8 CMP	X30, X0

0x516bdc MOVZ	X6, #0

0x516be0 B.CC	517190

0x516be4 ADDPL	X16, X11, #60

0x516be8 ADD	X1, X22, #8

0x516bec DUP	Z30.B, #0

0x516bf0 SUB	X16, X16, #1

0x516bf4 CNTB	X5, ALL, MUL #4

0x516bf8 PTRUE	P7.B, ALL

0x516bfc ORR	Z29.D, Z30.D, Z30.D

0x516c00 ORR	Z0.D, Z30.D, Z30.D

0x516c04 ORR	Z28.D, Z30.D, Z30.D

(3207) 0x516c08 ADD	X6, X6, X17

(3207) 0x516c0c LD1D	{Z26.D}, P7/Z, [X1, MUL VL]

(3207) 0x516c10 LD1D	{Z27.D}, P7/Z, [X1, #1, MUL VL]

(3207) 0x516c14 LD1D	{Z1.D}, P7/Z, [X1, #2, MUL VL]

(3207) 0x516c18 LD1D	{Z2.D}, P7/Z, [X1, #3, MUL VL]

(3207) 0x516c1c ADD	Z28.D, Z28.D, Z26.D

(3207) 0x516c20 ADD	X1, X1, X5

(3207) 0x516c24 ADD	Z0.D, Z0.D, Z27.D

(3207) 0x516c28 ADD	Z29.D, Z29.D, Z1.D

(3207) 0x516c2c ADD	Z30.D, Z30.D, Z2.D

(3207) 0x516c30 CMP	X6, X16

(3207) 0x516c34 B.LS	516c08

0x516c38 ADD	Z3.D, Z0.D, Z28.D

0x516c3c ADD	Z4.D, Z3.D, Z29.D

0x516c40 ADD	Z31.D, Z4.D, Z30.D

0x516c44 CMP	X6, X2

0x516c48 B.EQ	516c78

0x516c4c ADD	X3, X6, #1

0x516c50 MOVZ	X11, #0

0x516c54 ADD	X14, X22, X3,LSL #3

0x516c58 CNTD	X9, ALL

0x516c5c SUB	X13, X2, X6

0x516c60 WHILELO	P0.D, XZR, X13

(3206) 0x516c64 LD1D	{Z5.D}, P0/Z, [X14, X11,LSL #3]

(3206) 0x516c68 ADD	X11, X11, X9

(3206) 0x516c6c ADD	Z31.D, P0/M, Z31.D, Z5.D

(3206) 0x516c70 WHILELO	P0.D, X11, X13

(3206) 0x516c74 B.NE	516c64

0x516c78 PTRUE	P1.B, ALL

0x516c7c UADDV	D6, P1, Z31.D

0x516c80 ADD	D15, D15, D6

0x516c84 CMP	X27, X24

0x516c88 B.GE	517158

0x516c8c SUB	X15, X24, X27

0x516c90 SUB	X4, X15, #1

0x516c94 CMP	X4, #2

0x516c98 B.LS	517188

0x516c9c UBFM	X30, X15, #2, #63

0x516ca0 ADD	X0, X7, X27,LSL #3

0x516ca4 DUP	V31.2D, V15.D[0]

0x516ca8 UBFM	X2, X30, #59, #58

0x516cac SUB	X16, X2, #32

0x516cb0 ADD	X5, X0, X30,LSL #5

0x516cb4 UBFM	X1, X16, #5, #63

0x516cb8 ADD	X3, X1, #1

0x516cbc ANDS	X9, X3, #0x7

0x516cc0 B.EQ	516d88

0x516cc4 CMP	X9, #1

0x516cc8 B.EQ	516d6c

0x516ccc CMP	X9, #2

0x516cd0 B.EQ	516d58

0x516cd4 CMP	X9, #3

0x516cd8 B.EQ	516d44

0x516cdc CMP	X9, #4

0x516ce0 B.EQ	516d30

0x516ce4 CMP	X9, #5

0x516ce8 B.EQ	516d1c

0x516cec CMP	X9, #6

0x516cf0 B.EQ	516d08

0x516cf4 LDP	Q7, Q16, [X0]

0x516cf8 ADD	X0, X0, #32

0x516cfc ADD	V17.2D, V7.2D, V31.2D

0x516d00 ADD	V18.2D, V16.2D, V31.2D

0x516d04 STP	Q17, Q18, [X0, #2016]

0x516d08 LDP	Q19, Q20, [X0]

0x516d0c ADD	X0, X0, #32

0x516d10 ADD	V21.2D, V19.2D, V31.2D

0x516d14 ADD	V22.2D, V20.2D, V31.2D

0x516d18 STP	Q21, Q22, [X0, #2016]

0x516d1c LDP	Q23, Q24, [X0]

0x516d20 ADD	X0, X0, #32

0x516d24 ADD	V25.2D, V23.2D, V31.2D

0x516d28 ADD	V26.2D, V24.2D, V31.2D

0x516d2c STP	Q25, Q26, [X0, #2016]

0x516d30 LDP	Q27, Q0, [X0]

0x516d34 ADD	X0, X0, #32

0x516d38 ADD	V28.2D, V27.2D, V31.2D

0x516d3c ADD	V1.2D, V0.2D, V31.2D

0x516d40 STP	Q28, Q1, [X0, #2016]

0x516d44 LDP	Q2, Q29, [X0]

0x516d48 ADD	X0, X0, #32

0x516d4c ADD	V30.2D, V2.2D, V31.2D

0x516d50 ADD	V3.2D, V29.2D, V31.2D

0x516d54 STP	Q30, Q3, [X0, #2016]

0x516d58 LDP	Q4, Q5, [X0]

0x516d5c ADD	X0, X0, #32

0x516d60 ADD	V6.2D, V4.2D, V31.2D

0x516d64 ADD	V7.2D, V5.2D, V31.2D

0x516d68 STP	Q6, Q7, [X0, #2016]

0x516d6c LDP	Q16, Q17, [X0]

0x516d70 ADD	X0, X0, #32

0x516d74 ADD	V18.2D, V16.2D, V31.2D

0x516d78 ADD	V19.2D, V17.2D, V31.2D

0x516d7c STP	Q18, Q19, [X0, #2016]

0x516d80 CMP	X5, X0

0x516d84 B.EQ	516e1c

(3205) 0x516d88 LDP	Q22, Q23, [X0, #32]

(3205) 0x516d8c ORR	X14, XZR, X0

(3205) 0x516d90 LDP	Q24, Q25, [X0, #64]

(3205) 0x516d94 LDP	Q26, Q27, [X0, #96]

(3205) 0x516d98 LDP	Q28, Q5, [X0, #128]

(3205) 0x516d9c LDP	Q20, Q21, [X0]

(3205) 0x516da0 ADD	V18.2D, V22.2D, V31.2D

(3205) 0x516da4 ADD	V19.2D, V23.2D, V31.2D

(3205) 0x516da8 LDP	Q2, Q3, [X0, #160]

(3205) 0x516dac ADD	V16.2D, V24.2D, V31.2D

(3205) 0x516db0 ADD	V17.2D, V25.2D, V31.2D

(3205) 0x516db4 LDP	Q0, Q1, [X0, #192]

(3205) 0x516db8 ADD	V6.2D, V26.2D, V31.2D

(3205) 0x516dbc ADD	V7.2D, V27.2D, V31.2D

(3205) 0x516dc0 LDP	Q29, Q30, [X0, #224]

(3205) 0x516dc4 ADD	X0, X0, #256

(3205) 0x516dc8 ADD	V4.2D, V28.2D, V31.2D

(3205) 0x516dcc ADD	V22.2D, V5.2D, V31.2D

(3205) 0x516dd0 STP	Q18, Q19, [X0, #1824]

(3205) 0x516dd4 ADD	V20.2D, V20.2D, V31.2D

(3205) 0x516dd8 ADD	V21.2D, V21.2D, V31.2D

(3205) 0x516ddc ADD	V23.2D, V2.2D, V31.2D

(3205) 0x516de0 ADD	V24.2D, V3.2D, V31.2D

(3205) 0x516de4 STP	Q16, Q17, [X0, #1856]

(3205) 0x516de8 ADD	V25.2D, V0.2D, V31.2D

(3205) 0x516dec ADD	V26.2D, V1.2D, V31.2D

(3205) 0x516df0 ADD	V27.2D, V29.2D, V31.2D

(3205) 0x516df4 ADD	V28.2D, V30.2D, V31.2D

(3205) 0x516df8 STP	Q20, Q21, [X0, #1792]

(3205) 0x516dfc STP	Q6, Q7, [X0, #1888]

(3205) 0x516e00 STP	Q4, Q22, [X0, #1920]

(3205) 0x516e04 STP	Q23, Q24, [X0, #1952]

(3205) 0x516e08 STP	Q25, Q26, [X0, #1984]

(3205) 0x516e0c STUR	Q27, [X0, #480]

(3205) 0x516e10 STR	Q28, [X14, #240]

(3205) 0x516e14 CMP	X5, X0

(3205) 0x516e18 B.NE	516d88

0x516e1c AND	X17, X15, #0x0

0x516e20 ANDS	XZR, X15, #0x3

0x516e24 B.EQ	516e60

0x516e28 ADD	X13, X27, X17

0x516e2c SUB	X11, X15, X17

0x516e30 DUP	Z15.D, Z15.D[0]

0x516e34 WHILELO	P2.D, XZR, X11

0x516e38 ADD	X22, X7, X13,LSL #3

0x516e3c LD1D	{Z31.D}, P2/Z, [X7, X13,LSL #3]

0x516e40 ADD	Z5.D, Z31.D, Z15.D

0x516e44 ST1D	{Z5.D}, P2, [X22, MUL VL]

0x516e48 CNTD	X18, ALL

0x516e4c WHILELO	P3.D, X18, X11

0x516e50 B.EQ	516e60

0x516e54 LD1D	{Z2.D}, P3/Z, [X22, #1, MUL VL]

0x516e58 ADD	Z3.D, Z15.D, Z2.D

0x516e5c ST1D	{Z3.D}, P3, [X22, #1, MUL VL]

0x516e60 STP	X7, X8, [SP, #128]

0x516e64 STR	X10, [SP, #144]

0x516e68 BL	410120

0x516e6c LDP	X7, X18, [SP, #120]

0x516e70 LDP	X6, X12, [SP, #136]

0x516e74 CMP	X7, #0

0x516e78 B.LE	51717c

0x516e7c LDR	D15, [SP, #96]

0x516e80 B	51701c

    (3210) 0x516e84 ADD	X1, X1, #1

    (3210) 0x516e88 CMP	X1, X3

    (3210) 0x516e8c B.LT	516b4c

  (3209) 0x516e90 B	516b78

0x516e94 LDR	X13, [SP, #128]

0x516e98 LDR	X18, [SP, #160]

0x516e9c STR	XZR, [X7, X13,LSL #3]

0x516ea0 ADD	X12, X7, X13,LSL #3

0x516ea4 ADD	X15, X22, X18,LSL #3

0x516ea8 CMP	X18, #0

0x516eac B.LE	516fc0

0x516eb0 SUB	X17, X15, X22

0x516eb4 SUB	X30, X17, #8

0x516eb8 UBFM	X0, X30, #3, #63

0x516ebc ADD	X2, X0, #1

0x516ec0 ANDS	X16, X2, #0x7

0x516ec4 B.EQ	516f50

0x516ec8 CMP	X16, #1

0x516ecc B.EQ	516f3c

0x516ed0 CMP	X16, #2

0x516ed4 B.EQ	516f30

0x516ed8 CMP	X16, #3

0x516edc B.EQ	516f24

0x516ee0 CMP	X16, #4

0x516ee4 B.EQ	516f18

0x516ee8 CMP	X16, #5

0x516eec B.EQ	516f0c

0x516ef0 CMP	X16, #6

0x516ef4 B.EQ	516f00

0x516ef8 LDR	X11, [X22], #8

0x516efc STR	X11, [X12]

0x516f00 LDR	X5, [X22], #8

0x516f04 ADD	X11, X11, X5

0x516f08 STR	X11, [X12]

0x516f0c LDR	X6, [X22], #8

0x516f10 ADD	X11, X11, X6

0x516f14 STR	X11, [X12]

0x516f18 LDR	X1, [X22], #8

0x516f1c ADD	X11, X11, X1

0x516f20 STR	X11, [X12]

0x516f24 LDR	X3, [X22], #8

0x516f28 ADD	X11, X11, X3

0x516f2c STR	X11, [X12]

0x516f30 LDR	X9, [X22], #8

0x516f34 ADD	X11, X11, X9

0x516f38 STR	X11, [X12]

0x516f3c LDR	X14, [X22], #8

0x516f40 ADD	X11, X11, X14

0x516f44 STR	X11, [X12]

0x516f48 CMP	X15, X22

0x516f4c B.EQ	516fc0

(3204) 0x516f50 ORR	X13, XZR, X22

(3204) 0x516f54 ADD	X22, X22, #64

(3204) 0x516f58 LDR	X4, [X13], #8

(3204) 0x516f5c ADD	X18, X11, X4

(3204) 0x516f60 STR	X18, [X12]

(3204) 0x516f64 LDUR	X17, [X22, #456]

(3204) 0x516f68 ADD	X30, X18, X17

(3204) 0x516f6c STR	X30, [X12]

(3204) 0x516f70 LDR	X0, [X13, #8]

(3204) 0x516f74 ADD	X2, X30, X0

(3204) 0x516f78 STR	X2, [X12]

(3204) 0x516f7c LDUR	X16, [X22, #472]

(3204) 0x516f80 ADD	X5, X2, X16

(3204) 0x516f84 STR	X5, [X12]

(3204) 0x516f88 LDUR	X6, [X22, #480]

(3204) 0x516f8c ADD	X1, X5, X6

(3204) 0x516f90 STR	X1, [X12]

(3204) 0x516f94 LDUR	X3, [X22, #488]

(3204) 0x516f98 ADD	X9, X1, X3

(3204) 0x516f9c STR	X9, [X12]

(3204) 0x516fa0 LDUR	X14, [X22, #496]

(3204) 0x516fa4 ADD	X13, X9, X14

(3204) 0x516fa8 STR	X13, [X12]

(3204) 0x516fac LDUR	X11, [X22, #504]

(3204) 0x516fb0 ADD	X11, X13, X11

(3204) 0x516fb4 STR	X11, [X12]

(3204) 0x516fb8 CMP	X15, X22

(3204) 0x516fbc B.NE	516f50

0x516fc0 LDP	X22, X0, [SP, #120]

0x516fc4 ORR	X2, XZR, X11

0x516fc8 STP	X7, X8, [SP, #136]

0x516fcc ORR	X1, XZR, X22

0x516fd0 STR	X10, [SP, #152]

0x516fd4 BL	519344

0x516fd8 LDR	X7, [SP, #136]

0x516fdc LDR	X10, [SP, #152]

0x516fe0 STR	X7, [X0]

0x516fe4 STR	X0, [X10, #64]

0x516fe8 STR	X10, [SP, #128]

0x516fec BL	51942c

0x516ff0 LDR	X12, [SP, #128]

0x516ff4 LDR	X15, [X12, #64]

0x516ff8 LDR	X4, [X15, #8]

0x516ffc LDR	X18, [X15, #48]

0x517000 STR	X4, [X12, #88]

0x517004 STR	X18, [X12, #72]

0x517008 BL	410120

0x51700c CMP	X22, #0

0x517010 LDR	X6, [SP, #144]

0x517014 LDP	X12, X18, [SP, #128]

0x517018 B.LE	517040

0x51701c MOVZ	W1, #255

0x517020 ORR	X0, XZR, X19

0x517024 STP	X18, X6, [SP, #128]

0x517028 LDR	X10, [SP, #120]

0x51702c STR	X12, [SP, #144]

0x517030 UBFM	X2, X10, #61, #60

0x517034 BL	410340

0x517038 LDR	X12, [SP, #144]

0x51703c LDP	X18, X6, [SP, #128]

0x517040 LDR	X8, [X18, X27,LSL #3]

0x517044 CMP	X27, X24

0x517048 B.GE	517104

0x51704c ADD	X4, X6, #8

0x517050 LDR	X17, [X12, #72]

0x517054 LDR	X15, [X12, #88]

0x517058 HINT	#0

0x51705c HINT	#0

(3201) 0x517060 LDR	X12, [X18, X27,LSL #3]

(3201) 0x517064 CBZ	X23, 51707c

(3201) 0x517068 UBFM	X30, X8, #61, #60

(3201) 0x51706c STR	X8, [X19, X27,LSL #3]

(3201) 0x517070 ADD	X8, X8, #1

(3201) 0x517074 STR	XZR, [X17, X30]

(3201) 0x517078 STR	X27, [X15, X30]

(3201) 0x51707c LDR	X13, [X6, X27,LSL #3]

(3201) 0x517080 LDR	X10, [X4, X27,LSL #3]

(3201) 0x517084 CMP	X13, X10

(3201) 0x517088 B.GE	5170f8

  (3202) 0x51708c LDR	X16, [X26, X13,LSL #3]

  (3202) 0x517090 LDR	D0, [X28, X13,LSL #3]

  (3202) 0x517094 UBFM	X5, X16, #61, #60

  (3202) 0x517098 ADD	X1, X5, #8

  (3202) 0x51709c LDR	X0, [X25, X5]

  (3202) 0x5170a0 ADD	X9, X25, X1

  (3202) 0x5170a4 LDR	X7, [X25, X1]

  (3202) 0x5170a8 CMP	X0, X7

  (3202) 0x5170ac B.GE	5170ec

    (3203) 0x5170b0 LDR	X3, [X20, X0,LSL #3]

    (3203) 0x5170b4 LDR	D1, [X21, X0,LSL #3]

    (3203) 0x5170b8 UBFM	X14, X3, #61, #60

    (3203) 0x5170bc LDR	X2, [X19, X14]

    (3203) 0x5170c0 FMUL	D29, D0, D1

    (3203) 0x5170c4 UBFM	X11, X2, #61, #60

    (3203) 0x5170c8 CMP	X12, X2

    (3203) 0x5170cc B.GT	517124

    (3203) 0x5170d0 LDR	D30, [X17, X11]

    (3203) 0x5170d4 ADD	X0, X0, #1

    (3203) 0x5170d8 FADD	D20, D30, D29

    (3203) 0x5170dc STR	D20, [X17, X11]

    (3203) 0x5170e0 CMP	X7, X0

    (3203) 0x5170e4 B.GT	5170b0

  (3202) 0x5170e8 LDR	X10, [X4, X27,LSL #3]

  (3202) 0x5170ec ADD	X13, X13, #1

  (3202) 0x5170f0 CMP	X13, X10

  (3202) 0x5170f4 B.LT	51708c

(3201) 0x5170f8 ADD	X27, X27, #1

(3201) 0x5170fc CMP	X24, X27

(3201) 0x517100 B.NE	517060

0x517104 LDP	X21, X22, [SP, #32]

0x517108 ORR	X0, XZR, X19

0x51710c LDP	X23, X24, [SP, #48]

0x517110 LDP	X19, X20, [SP, #16]

0x517114 LDP	X25, X26, [SP, #64]

0x517118 LDP	X27, X28, [SP, #80]

0x51711c LDP	X29, X30, [SP], #176

0x517120 B	5294c0

    (3203) 0x517124 STR	X8, [X19, X14]

    (3203) 0x517128 ADD	X0, X0, #1

    (3203) 0x51712c STR	X3, [X15, X8,LSL #3]

    (3203) 0x517130 ADD	X8, X8, #1

    (3203) 0x517134 LDR	X22, [X19, X14]

    (3203) 0x517138 LDR	X7, [X9]

    (3203) 0x51713c STR	D29, [X17, X22,LSL #3]

    (3203) 0x517140 CMP	X0, X7

    (3203) 0x517144 B.LT	5170b0

  (3202) 0x517148 B	5170e8

0x51714c ADD	X27, X1, X27

0x517150 ADD	X24, X1, X6

0x517154 B	516aa0

0x517158 STP	X7, X8, [SP, #128]

0x51715c STR	X10, [SP, #144]

0x517160 BL	410120

0x517164 LDP	X22, X18, [SP, #120]

0x517168 LDP	X6, X12, [SP, #136]

0x51716c CMP	X22, #0

0x517170 B.GT	516e7c

0x517174 LDR	D15, [SP, #96]

0x517178 B	517104

0x51717c LDR	X8, [X18, X27,LSL #3]

0x517180 LDR	D15, [SP, #96]

0x517184 B	51704c

0x517188 MOVZ	X17, #0

0x51718c B	516e28

0x517190 DUP	Z31.B, #0

0x517194 B	516c4c

0x517198 HINT	#0

0x51719c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMultiply	csr_matop.c:185	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►50.08+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMultiply	csr_matop.c:185	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec
►49.92+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

Coverage (%)	Name	Source Location	Module
►74.69+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►25.31+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMultiply	csr_matop.c:185	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►87.47+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.53+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMultiply	csr_matop.c:185	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►94.17+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.83+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMultiply	csr_matop.c:185	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►96.29+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.71+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMultiply	csr_matop.c:185	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►97.30+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.70+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMultiply	csr_matop.c:185	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►97.81+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.19+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMultiply	csr_matop.c:185	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►98.22+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.78+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMultiply	csr_matop.c:185	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►98.68+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.32+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMultiply	csr_matop.c:185	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►98.75+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.25+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_CSRMatrixMultiply	csr_matop.c:185	exec
○	hypre_ParTMatmul	par_csr_matop.c:3287	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:1227	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	csr_matop.c:185-302
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:185,192-302.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 39.50 to 9.50 cycles (4.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 41% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 39.50 to 25.00 cycles (1.58x speedup).

Details

22% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
17% of VPU stores are used in vector version.
41% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
8% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:208
hypre_CSRMatrixCreate: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:257
hypre_CSRMatrixInitialize: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:259
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:192
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:193
unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:211
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:239
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:265
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:265
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:269
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:265

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	309
nb uops	304
loop length	1236
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	23
used v registers	25
used z registers	10
nb stack references	66

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.00 cycles
front end	38.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	32.25	32.25	32.25	32.25	9.50	9.50	8.50	8.50	39.50	39.17	39.33	20.50	20.50
cycles	25.00	25.00	32.25	32.25	32.25	32.25	9.50	9.50	8.50	8.50	39.50	39.17	39.33	20.50	20.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	38.00
Dispatch	39.50
DIV/SQRT	5.00-20.00
Overall L1	39.50

Vectorization ratios

all	22%
load	25%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	41%
fma	0%
div/sqrt	0%
other	8%

Vector efficiency ratios

all	41%
load	50%
store	47%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	41%
fma	25%
div/sqrt	25%
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 39.50 cycles. At this rate:

1% of peak load performance is reached (1.62 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.62 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 516a20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X10, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X7, [X10, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X19, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X25, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X20, X0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X22, [X10, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X0, X19, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c0a0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c080 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X2, X19, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDP X11, X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X12, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X4, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MUL X27, X11, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MSUB X1, X2, X0, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X6, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51714c <hypre_CSRMatrixMultiply._omp_fn.0+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X27, X11, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X4, X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X11, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X18, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X7, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 516af8 <hypre_CSRMatrixMultiply._omp_fn.0+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X18, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X7, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410340 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X18, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X7, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X4, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X27, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 516b94 <hypre_CSRMatrixMultiply._omp_fn.0+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X17, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X12, X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X7, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X11, 516e94 <hypre_CSRMatrixMultiply._omp_fn.0+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D15, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 516c84 <hypre_CSRMatrixMultiply._omp_fn.0+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTH X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X30, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X17, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X30, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 517190 <hypre_CSRMatrixMultiply._omp_fn.0+0x770>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDPL X16, X11, #60	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X1, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z30.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTB X5, ALL, MUL #4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ORR Z29.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z0.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z28.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z3.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z4.D, Z3.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z31.D, Z4.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
CMP X6, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516c78 <hypre_CSRMatrixMultiply._omp_fn.0+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X22, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X13, X2, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, XZR, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
UADDV D6, P1, Z31.D																			vect (100.0%)
ADD D15, D15, D6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X27, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 517158 <hypre_CSRMatrixMultiply._omp_fn.0+0x738>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X15, X24, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 517188 <hypre_CSRMatrixMultiply._omp_fn.0+0x768>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X30, X15, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X7, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V31.2D, V15.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X2, X30, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X16, X2, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X0, X30,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X1, X16, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X9, X3, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d88 <hypre_CSRMatrixMultiply._omp_fn.0+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d6c <hypre_CSRMatrixMultiply._omp_fn.0+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d58 <hypre_CSRMatrixMultiply._omp_fn.0+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d44 <hypre_CSRMatrixMultiply._omp_fn.0+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d30 <hypre_CSRMatrixMultiply._omp_fn.0+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d1c <hypre_CSRMatrixMultiply._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d08 <hypre_CSRMatrixMultiply._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q7, Q16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V17.2D, V7.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V18.2D, V16.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q17, Q18, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q19, Q20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V21.2D, V19.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V22.2D, V20.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q21, Q22, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q23, Q24, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V25.2D, V23.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V26.2D, V24.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q25, Q26, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q27, Q0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V28.2D, V27.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V1.2D, V0.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q28, Q1, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q2, Q29, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V30.2D, V2.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V3.2D, V29.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q30, Q3, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q4, Q5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V6.2D, V4.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V7.2D, V5.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q6, Q7, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q16, Q17, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V18.2D, V16.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V19.2D, V17.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q18, Q19, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516e1c <hypre_CSRMatrixMultiply._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X17, X15, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS XZR, X15, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516e60 <hypre_CSRMatrixMultiply._omp_fn.0+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X27, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z15.D, Z15.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P2.D, XZR, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X22, X7, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z31.D}, P2/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
ADD Z5.D, Z31.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z5.D}, P2, [X22, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P3.D, X18, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.EQ 516e60 <hypre_CSRMatrixMultiply._omp_fn.0+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z2.D}, P3/Z, [X22, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
ADD Z3.D, Z15.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z3.D}, P3, [X22, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X7, X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X6, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 51717c <hypre_CSRMatrixMultiply._omp_fn.0+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 51701c <hypre_CSRMatrixMultiply._omp_fn.0+0x5fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X12, X7, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X22, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 516fc0 <hypre_CSRMatrixMultiply._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X17, X15, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X30, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X0, X30, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X16, X2, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f50 <hypre_CSRMatrixMultiply._omp_fn.0+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f3c <hypre_CSRMatrixMultiply._omp_fn.0+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f30 <hypre_CSRMatrixMultiply._omp_fn.0+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f24 <hypre_CSRMatrixMultiply._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f18 <hypre_CSRMatrixMultiply._omp_fn.0+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f0c <hypre_CSRMatrixMultiply._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f00 <hypre_CSRMatrixMultiply._omp_fn.0+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X15, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516fc0 <hypre_CSRMatrixMultiply._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X22, X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X2, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X7, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 519344 <hypre_CSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X10, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 51942c <hypre_CSRMatrixInitialize>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X15, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X15, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [X12, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X18, [X12, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X12, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B.LE 517040 <hypre_CSRMatrixMultiply._omp_fn.0+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X18, X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X2, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 410340 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X18, X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X18, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 517104 <hypre_CSRMatrixMultiply._omp_fn.0+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [X12, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X12, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 5294c0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 516aa0 <hypre_CSRMatrixMultiply._omp_fn.0+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X7, X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X22, X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X6, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 516e7c <hypre_CSRMatrixMultiply._omp_fn.0+0x45c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 517104 <hypre_CSRMatrixMultiply._omp_fn.0+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X18, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 51704c <hypre_CSRMatrixMultiply._omp_fn.0+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 516e28 <hypre_CSRMatrixMultiply._omp_fn.0+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z31.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
B 516c4c <hypre_CSRMatrixMultiply._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	csr_matop.c:185-302
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:185,192-302.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 39.50 to 9.50 cycles (4.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

22% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
17% of VPU stores are used in vector version.
41% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
8% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:208
hypre_CSRMatrixCreate: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:257
hypre_CSRMatrixInitialize: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:259
hypre_GetThreadNum: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:192
hypre_NumActiveThreads: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:193
unknown: 6 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:211
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:239
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:265
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:265
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:269
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c:265

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	309
nb uops	304
loop length	1236
used w registers	1
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	23
used v registers	25
used z registers	10
nb stack references	66

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	38.00 cycles
front end	38.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	25.00	25.00	32.25	32.25	32.25	32.25	9.50	9.50	8.50	8.50	39.50	39.17	39.33	20.50	20.50
cycles	25.00	25.00	32.25	32.25	32.25	32.25	9.50	9.50	8.50	8.50	39.50	39.17	39.33	20.50	20.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	38.00
Dispatch	39.50
DIV/SQRT	5.00-20.00
Overall L1	39.50

Vectorization ratios

all	22%
load	25%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	41%
fma	0%
div/sqrt	0%
other	8%

Vector efficiency ratios

all	41%
load	50%
store	47%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	41%
fma	25%
div/sqrt	25%
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 39.50 cycles. At this rate:

1% of peak load performance is reached (1.62 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.62 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 516a20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #848]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X10, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X7, [X10, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X26, X19, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X25, [X0, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X20, X0, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X22, [X10, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X0, X19, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X10, X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c0a0 <hypre_GetThreadNum>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 52c080 <hypre_NumActiveThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SDIV X2, X19, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	scal (25.0%)
LDP X11, X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X12, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X4, X5, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MUL X27, X11, X2	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MSUB X1, X2, X0, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X6, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 51714c <hypre_CSRMatrixMultiply._omp_fn.0+0x72c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X27, X11, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X4, X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X11, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X3, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X18, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X7, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 516af8 <hypre_CSRMatrixMultiply._omp_fn.0+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X18, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X7, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410340 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X18, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X7, X12, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X4, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X15, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X27, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 516b94 <hypre_CSRMatrixMultiply._omp_fn.0+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X17, [X22, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X12, X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X8, X7, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X11, X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X11, 516e94 <hypre_CSRMatrixMultiply._omp_fn.0+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR D15, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D15, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 516c84 <hypre_CSRMatrixMultiply._omp_fn.0+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTH X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X30, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X17, #7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X2, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X30, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MOVZ X6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.CC 517190 <hypre_CSRMatrixMultiply._omp_fn.0+0x770>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDPL X16, X11, #60	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X1, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z30.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X16, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTB X5, ALL, MUL #4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ORR Z29.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z0.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z28.D, Z30.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z3.D, Z0.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z4.D, Z3.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z31.D, Z4.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
CMP X6, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516c78 <hypre_CSRMatrixMultiply._omp_fn.0+0x258>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X14, X22, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X13, X2, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P0.D, XZR, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
UADDV D6, P1, Z31.D																			vect (100.0%)
ADD D15, D15, D6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X27, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 517158 <hypre_CSRMatrixMultiply._omp_fn.0+0x738>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X15, X24, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 517188 <hypre_CSRMatrixMultiply._omp_fn.0+0x768>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X30, X15, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X7, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V31.2D, V15.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X2, X30, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X16, X2, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X0, X30,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
UBFM X1, X16, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X9, X3, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d88 <hypre_CSRMatrixMultiply._omp_fn.0+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d6c <hypre_CSRMatrixMultiply._omp_fn.0+0x34c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d58 <hypre_CSRMatrixMultiply._omp_fn.0+0x338>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d44 <hypre_CSRMatrixMultiply._omp_fn.0+0x324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d30 <hypre_CSRMatrixMultiply._omp_fn.0+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d1c <hypre_CSRMatrixMultiply._omp_fn.0+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X9, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516d08 <hypre_CSRMatrixMultiply._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q7, Q16, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V17.2D, V7.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V18.2D, V16.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q17, Q18, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q19, Q20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V21.2D, V19.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V22.2D, V20.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q21, Q22, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q23, Q24, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V25.2D, V23.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V26.2D, V24.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q25, Q26, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q27, Q0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V28.2D, V27.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V1.2D, V0.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q28, Q1, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q2, Q29, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V30.2D, V2.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V3.2D, V29.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q30, Q3, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q4, Q5, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V6.2D, V4.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V7.2D, V5.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q6, Q7, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q16, Q17, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD V18.2D, V16.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
ADD V19.2D, V17.2D, V31.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP Q18, Q19, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516e1c <hypre_CSRMatrixMultiply._omp_fn.0+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X17, X15, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS XZR, X15, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516e60 <hypre_CSRMatrixMultiply._omp_fn.0+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X13, X27, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X11, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z15.D, Z15.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P2.D, XZR, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X22, X7, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z31.D}, P2/Z, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
ADD Z5.D, Z31.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z5.D}, P2, [X22, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P3.D, X18, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.EQ 516e60 <hypre_CSRMatrixMultiply._omp_fn.0+0x440>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z2.D}, P3/Z, [X22, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
ADD Z3.D, Z15.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z3.D}, P3, [X22, #1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X7, X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X7, X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X6, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 51717c <hypre_CSRMatrixMultiply._omp_fn.0+0x75c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 51701c <hypre_CSRMatrixMultiply._omp_fn.0+0x5fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR XZR, [X7, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X12, X7, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X22, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 516fc0 <hypre_CSRMatrixMultiply._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X17, X15, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SUB X30, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X0, X30, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ANDS X16, X2, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f50 <hypre_CSRMatrixMultiply._omp_fn.0+0x530>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f3c <hypre_CSRMatrixMultiply._omp_fn.0+0x51c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f30 <hypre_CSRMatrixMultiply._omp_fn.0+0x510>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f24 <hypre_CSRMatrixMultiply._omp_fn.0+0x504>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f18 <hypre_CSRMatrixMultiply._omp_fn.0+0x4f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f0c <hypre_CSRMatrixMultiply._omp_fn.0+0x4ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516f00 <hypre_CSRMatrixMultiply._omp_fn.0+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X5, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X6, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X9, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X22], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X11, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X15, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 516fc0 <hypre_CSRMatrixMultiply._omp_fn.0+0x5a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X22, X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X2, XZR, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X7, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X1, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 519344 <hypre_CSRMatrixCreate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X0, [X10, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 51942c <hypre_CSRMatrixInitialize>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X12, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X15, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X15, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X4, [X12, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X18, [X12, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X6, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X12, X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
B.LE 517040 <hypre_CSRMatrixMultiply._omp_fn.0+0x620>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W1, #255	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X18, X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
UBFM X2, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
BL 410340 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X18, X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X8, [X18, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X27, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 517104 <hypre_CSRMatrixMultiply._omp_fn.0+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X17, [X12, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X12, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X0, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP], #176	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 5294c0 <hypre_Free>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X27, X1, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X24, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 516aa0 <hypre_CSRMatrixMultiply._omp_fn.0+0x80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X7, X8, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X22, X18, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X6, X12, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 516e7c <hypre_CSRMatrixMultiply._omp_fn.0+0x45c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 517104 <hypre_CSRMatrixMultiply._omp_fn.0+0x6e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X18, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 51704c <hypre_CSRMatrixMultiply._omp_fn.0+0x62c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 516e28 <hypre_CSRMatrixMultiply._omp_fn.0+0x408>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z31.B, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
B 516c4c <hypre_CSRMatrixMultiply._omp_fn.0+0x22c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	1.84	0	3.32	0	5.72	0	10.31	0	14.17	0	17.56	0	21.34	0	23.68	0	26.8	0	28.64	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	9.520001411438	2.7506556510925
1x2	2	1.84	1.84	2	4.9900002479553	2.759993314743
1x4	4	3.32	3.32	4	2.6149995326996	2.7986023426056
1x8	8	5.72	5.72	8	1.3749998807907	2.6933059692383
1x16	16	10.31	10.31	16	0.74000000953674	1.756850361824
1x24	24	14.17	14.17	24	0.50999999046326	1.3455257415771
1x32	32	17.56	17.56	32	0.40500003099442	1.1604474782944
1x40	40	21.34	21.34	40	0.33500000834465	1.0102719068527
1x48	48	23.68	23.68	48	0.29000002145767	0.90737980604172
1x56	56	26.8	26.8	56	0.26500001549721	0.81475514173508
1x64	64	28.64	28.64	64	0.24500000476837	0.74835073947906

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMultiply._omp_fn.0–	2.75	9.52
○Loop 3204 - csr_matop.c:254-255 - exec	0.00	0.00
○Loop 3205 - csr_matop.c:248-249 - exec	0.00	0.00
○Loop 3207 - csr_matop.c:245-246 - exec	0.00	0.00
○Loop 3206 - csr_matop.c:245-246 - exec	0.00	0.00
▼Loop 3201 - csr_matop.c:272-298 - exec–	0.00	0.00
▼Loop 3202 - csr_matop.c:282-298 - exec–	0.22	0.77
○Loop 3203 - csr_matop.c:286-298 - exec	1.42	4.90
▼Loop 3208 - csr_matop.c:214-231 - exec–	0.00	0.00
▼Loop 3209 - csr_matop.c:222-231 - exec–	0.14	0.50
○Loop 3210 - csr_matop.c:225-231 - exec	0.97	3.35

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency