OV - exec - Function hypre

	Function: hypre_CSRMatrixMatvecT	Module: exec	Source: csr_matvec.c:445-648 [...]	Coverage (incl. loops): 3.11% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 445 - 648

--------------------------------------------------------------------------------

445: {

446:    HYPRE_Complex    *A_data    = hypre_CSRMatrixData(A);

447:    HYPRE_Int        *A_i       = hypre_CSRMatrixI(A);

448:    HYPRE_Int        *A_j       = hypre_CSRMatrixJ(A);

449:    HYPRE_Int         num_rows  = hypre_CSRMatrixNumRows(A);

450:    HYPRE_Int         num_cols  = hypre_CSRMatrixNumCols(A);

451:

452:    HYPRE_Complex    *x_data = hypre_VectorData(x);

453:    HYPRE_Complex    *y_data = hypre_VectorData(y);

454:    HYPRE_Int         x_size = hypre_VectorSize(x);

455:    HYPRE_Int         y_size = hypre_VectorSize(y);

456:    HYPRE_Int         num_vectors = hypre_VectorNumVectors(x);

457:    HYPRE_Int         idxstride_y = hypre_VectorIndexStride(y);

458:    HYPRE_Int         vecstride_y = hypre_VectorVectorStride(y);

459:    HYPRE_Int         idxstride_x = hypre_VectorIndexStride(x);

460:    HYPRE_Int         vecstride_x = hypre_VectorVectorStride(x);

[...]

472:    hypre_Vector     *x_tmp = NULL;

[...]

485:    hypre_assert( num_vectors == hypre_VectorNumVectors(y) );

486:

487:    if (num_rows != x_size)

488:       ierr = 1;

489:

490:    if (num_cols != y_size)

491:       ierr = 2;

492:

493:    if (num_rows != x_size && num_cols != y_size)

494:       ierr = 3;

495:    /*-----------------------------------------------------------------------

496:     * Do (alpha == 0.0) computation - RDF: USE MACHINE EPS

497:     *-----------------------------------------------------------------------*/

498:

499:    if (alpha == 0.0)

500:    {

501: #ifdef HYPRE_USING_OPENMP

502: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

503: #endif

504:       for (i = 0; i < num_cols*num_vectors; i++)

505:          y_data[i] *= beta;

506:

507:       return ierr;

508:    }

509:

510:    if (x == y)

511:    {

512:       x_tmp = hypre_SeqVectorCloneDeep(x);

513:       x_data = hypre_VectorData(x_tmp);

[...]

520:    temp = beta / alpha;

521:

522:    if (temp != 1.0)

523:    {

524:       if (temp == 0.0)

525:       {

526: #ifdef HYPRE_USING_OPENMP

527: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

535: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

545:    num_threads = hypre_NumThreads();

546:    if (num_threads > 1)

547:    {

548:       y_data_expand = hypre_CTAlloc(HYPRE_Complex, num_threads*y_size);

549:

550:       if ( num_vectors==1 )

551:       {

552:

553: #ifdef HYPRE_USING_OPENMP

554: #pragma omp parallel private(i,jj,j,my_thread_num,offset)

[...]

589:          for (i = 0; i < num_rows; i++)

590:          {

591:             for ( jv=0; jv<num_vectors; ++jv )

592:             {

593:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

594:                {

595:                   j = A_j[jj];

596:                   y_data[ j*idxstride_y + jv*vecstride_y ] +=

[...]

603:       hypre_TFree(y_data_expand);

604:

605:    }

606:    else

607:    {

608:       for (i = 0; i < num_rows; i++)

609:       {

610:          if ( num_vectors==1 )

611:          {

612:             for (jj = A_i[i]; jj < A_i[i+1]; jj++)

613:             {

614:                j = A_j[jj];

615:                y_data[j] += A_data[jj] * x_data[i];

616:             }

617:          }

618:          else

619:          {

620:             for ( jv=0; jv<num_vectors; ++jv )

621:             {

622:                for (jj = A_i[i]; jj < A_i[i+1]; jj++)

623:                {

624:                   j = A_j[jj];

625:                   y_data[ j*idxstride_y + jv*vecstride_y ] +=

[...]

636:    if (alpha != 1.0)

637:    {

638: #ifdef HYPRE_USING_OPENMP

639: #pragma omp parallel for private(i) HYPRE_SMP_SCHEDULE

[...]

645:    if (x == y) hypre_SeqVectorDestroy(x_tmp);

646:

647:    return ierr;

648: }

0x520300 STP	X29, X30, [SP, #752]!

0x520304 ORR	X15, XZR, X1

0x520308 ADD	X29, SP, #0

0x52030c STP	X19, X20, [SP, #16]

0x520310 STP	X21, X22, [SP, #32]

0x520314 STP	X23, X24, [SP, #48]

0x520318 ORR	X23, XZR, X2

0x52031c STP	X25, X26, [SP, #64]

0x520320 STP	X27, X28, [SP, #80]

0x520324 STP	D13, D14, [SP, #96]

0x520328 FMOV	D14, D1

0x52032c LDR	X11, [X0, #16]

0x520330 LDP	X27, X21, [X0]

0x520334 LDP	X19, X25, [X2]

0x520338 LDP	X14, X22, [X15]

0x52033c LDP	X26, X28, [X23, #40]

0x520340 LDR	X24, [X1, #24]

0x520344 LDR	X1, [X2, #24]

0x520348 LDR	X2, [X0, #24]

0x52034c LDR	X20, [X0, #48]

0x520350 LDR	X0, [X15, #40]

0x520354 STR	X2, [SP, #128]

0x520358 LDR	X12, [X15, #48]

0x52035c STR	D15, [SP, #112]

0x520360 FMOV	D15, D0

0x520364 STR	X0, [SP, #136]

0x520368 CMP	X1, X24

0x52036c B.EQ	5203b4

0x520370 ADRP	X3,

0x520374 ADRP	X4,

0x520378 STP	X14, X11, [SP, #144]

0x52037c ADRP	X5,

0x520380 ADD	X2, X3, #1256

0x520384 ADD	X1, X4, #2000

0x520388 LDR	X0, [X5, #1776]

0x52038c STP	X12, X15, [SP, #160]

0x520390 BL	529700

0x520394 ADRP	X6,

0x520398 MOVZ	X3, #0

0x52039c ADD	X0, X6, #1128

0x5203a0 MOVZ	X2, #1

0x5203a4 MOVZ	X1, #485

0x5203a8 BL	52cf20

0x5203ac LDP	X14, X11, [SP, #144]

0x5203b0 LDP	X12, X15, [SP, #160]

0x5203b4 LDR	X7, [SP, #128]

0x5203b8 CMP	X11, X22

0x5203bc B.EQ	520850

0x5203c0 CMP	X7, X25

0x5203c4 MOVZ	X13, #3

0x5203c8 CSINC	X22, X13, XZR, #1

0x5203cc FCMP	D15, #0

0x5203d0 B.EQ	520864

0x5203d4 STR	XZR, [SP, #176]

0x5203d8 CMP	X15, X23

0x5203dc B.EQ	5208f8

0x5203e0 FDIV	D13, D14, D15

0x5203e4 FMOV	D31, #1.0000000

0x5203e8 FCMP	D13, D31

0x5203ec B.EQ	52042c

0x5203f0 FCMP	D13, #0

0x5203f4 STP	X14, X11, [SP, #144]

0x5203f8 STP	X12, X15, [SP, #160]

0x5203fc B.NE	520890

0x520400 ADRP	X16,

0x520404 MOVZ	W3, #0

0x520408 LDR	X17, [SP, #128]

0x52040c ADD	X0, X16, #744

0x520410 MOVZ	W2, #0

0x520414 ADD	X1, SP, #192

0x520418 STR	X24, [SP, #208]

0x52041c STP	X17, X19, [SP, #192]

0x520420 BL	410430

0x520424 LDP	X14, X11, [SP, #144]

0x520428 LDP	X12, X15, [SP, #160]

0x52042c STP	X14, X11, [SP, #144]

0x520430 STP	X12, X15, [SP, #160]

0x520434 BL	52c060

0x520438 CMP	X0, #1

0x52043c LDP	X9, X11, [SP, #144]

0x520440 ORR	X18, XZR, X0

0x520444 LDP	X12, X8, [SP, #160]

0x520448 B.GT	52062c

0x52044c CMP	X11, #0

0x520450 B.LE	5205f0

0x520454 LDR	X30, [SP, #136]

0x520458 UBFM	X25, X30, #61, #60

0x52045c CMP	X28, #1

0x520460 B.NE	52091c

0x520464 CMP	X24, #1

0x520468 B.EQ	520c88

0x52046c MOVZ	X15, #0

0x520470 MOVZ	X14, #0

0x520474 ADD	X16, X27, #8

(3370) 0x520478 CMP	X24, #0

(3370) 0x52047c B.LE	5205f0

  (3373) 0x520480 LDR	X10, [X27, X14,LSL #3]

  (3373) 0x520484 LDR	X17, [X16, X14,LSL #3]

  (3373) 0x520488 CMP	X17, X10

  (3373) 0x52048c B.LE	5208e4

  (3373) 0x520490 ADD	X5, X9, X15,LSL #3

  (3373) 0x520494 MOVZ	X6, #0

  (3373) 0x520498 MOVZ	X7, #0

  (3373) 0x52049c HINT	#0

    (3372) 0x5204a0 SUB	X13, X17, X10

    (3372) 0x5204a4 ORR	X0, XZR, X10

    (3372) 0x5204a8 ANDS	X4, X13, #0x3

    (3372) 0x5204ac B.EQ	520534

    (3372) 0x5204b0 CMP	X4, #1

    (3372) 0x5204b4 B.EQ	520508

    (3372) 0x5204b8 CMP	X4, #2

    (3372) 0x5204bc B.EQ	5204e4

    (3372) 0x5204c0 LDR	X3, [X21, X10,LSL #3]

    (3372) 0x5204c4 ADD	X0, X10, #1

    (3372) 0x5204c8 LDR	D4, [X20, X10,LSL #3]

    (3372) 0x5204cc LDR	D3, [X5]

    (3372) 0x5204d0 ADD	X2, X6, X3

    (3372) 0x5204d4 UBFM	X28, X2, #61, #60

    (3372) 0x5204d8 LDR	D2, [X19, X28]

    (3372) 0x5204dc FMADD	D7, D3, D4, D2

    (3372) 0x5204e0 STR	D7, [X19, X28]

    (3372) 0x5204e4 LDR	X18, [X21, X0,LSL #3]

    (3372) 0x5204e8 LDR	D30, [X20, X0,LSL #3]

    (3372) 0x5204ec ADD	X0, X0, #1

    (3372) 0x5204f0 LDR	D17, [X5]

    (3372) 0x5204f4 ADD	X30, X6, X18

    (3372) 0x5204f8 UBFM	X1, X30, #61, #60

    (3372) 0x5204fc LDR	D16, [X19, X1]

    (3372) 0x520500 FMADD	D18, D17, D30, D16

    (3372) 0x520504 STR	D18, [X19, X1]

    (3372) 0x520508 LDR	X13, [X21, X0,LSL #3]

    (3372) 0x52050c LDR	D19, [X20, X0,LSL #3]

    (3372) 0x520510 ADD	X0, X0, #1

    (3372) 0x520514 LDR	D29, [X5]

    (3372) 0x520518 ADD	X4, X6, X13

    (3372) 0x52051c UBFM	X3, X4, #61, #60

    (3372) 0x520520 LDR	D28, [X19, X3]

    (3372) 0x520524 FMADD	D20, D29, D19, D28

    (3372) 0x520528 STR	D20, [X19, X3]

    (3372) 0x52052c CMP	X0, X17

    (3372) 0x520530 B.EQ	5205cc

      (3371) 0x520534 LDR	X2, [X21, X0,LSL #3]

      (3371) 0x520538 ADD	X30, X0, #1

      (3371) 0x52053c ADD	X18, X0, #3

      (3371) 0x520540 ADD	X28, X0, #2

      (3371) 0x520544 LDR	D27, [X20, X0,LSL #3]

      (3371) 0x520548 ADD	X0, X0, #4

      (3371) 0x52054c LDR	D26, [X5]

      (3371) 0x520550 ADD	X1, X6, X2

      (3371) 0x520554 UBFM	X13, X1, #61, #60

      (3371) 0x520558 LDR	X4, [X21, X30,LSL #3]

      (3371) 0x52055c LDR	D25, [X19, X13]

      (3371) 0x520560 LDR	X2, [X21, X28,LSL #3]

      (3371) 0x520564 ADD	X3, X6, X4

      (3371) 0x520568 UBFM	X4, X3, #61, #60

      (3371) 0x52056c LDR	X1, [X21, X18,LSL #3]

      (3371) 0x520570 FMADD	D21, D26, D27, D25

      (3371) 0x520574 ADD	X2, X6, X2

      (3371) 0x520578 UBFM	X3, X2, #61, #60

      (3371) 0x52057c ADD	X1, X6, X1

      (3371) 0x520580 UBFM	X2, X1, #61, #60

      (3371) 0x520584 STR	D21, [X19, X13]

      (3371) 0x520588 LDR	D24, [X20, X30,LSL #3]

      (3371) 0x52058c LDR	D22, [X19, X4]

      (3371) 0x520590 LDR	D23, [X5]

      (3371) 0x520594 FMADD	D14, D23, D24, D22

      (3371) 0x520598 STR	D14, [X19, X4]

      (3371) 0x52059c LDR	D13, [X20, X28,LSL #3]

      (3371) 0x5205a0 LDR	D31, [X19, X3]

      (3371) 0x5205a4 LDR	D6, [X5]

      (3371) 0x5205a8 FMADD	D5, D6, D13, D31

      (3371) 0x5205ac STR	D5, [X19, X3]

      (3371) 0x5205b0 LDR	D0, [X20, X18,LSL #3]

      (3371) 0x5205b4 LDR	D1, [X19, X2]

      (3371) 0x5205b8 LDR	D4, [X5]

      (3371) 0x5205bc FMADD	D2, D4, D0, D1

      (3371) 0x5205c0 STR	D2, [X19, X2]

      (3371) 0x5205c4 CMP	X0, X17

      (3371) 0x5205c8 B.NE	520534

    (3372) 0x5205cc ADD	X7, X7, #1

    (3372) 0x5205d0 ADD	X6, X6, X26

    (3372) 0x5205d4 ADD	X5, X5, X25

    (3372) 0x5205d8 CMP	X24, X7

    (3372) 0x5205dc B.NE	5204a0

  (3373) 0x5205e0 ADD	X14, X14, #1

  (3373) 0x5205e4 ADD	X15, X15, X12

  (3373) 0x5205e8 CMP	X11, X14

  (3373) 0x5205ec B.NE	520480

0x5205f0 FMOV	D19, #1.0000000

0x5205f4 FCMP	D15, D19

0x5205f8 B.NE	52080c

0x5205fc CMP	X8, X23

0x520600 B.EQ	520844

0x520604 LDR	D15, [SP, #112]

0x520608 ORR	X0, XZR, X22

0x52060c LDP	X19, X20, [SP, #16]

0x520610 LDP	X21, X22, [SP, #32]

0x520614 LDP	X23, X24, [SP, #48]

0x520618 LDP	X25, X26, [SP, #64]

0x52061c LDP	X27, X28, [SP, #80]

0x520620 LDP	D13, D14, [SP, #96]

0x520624 LDP	X29, X30, [SP], #272

0x520628 RET

0x52062c MUL	X0, X25, X0

0x520630 MOVZ	X1, #8

0x520634 STP	X18, X9, [SP, #144]

0x520638 STP	X11, X12, [SP, #160]

0x52063c STR	X8, [SP, #184]

0x520640 BL	529428

0x520644 CMP	X24, #1

0x520648 LDR	X11, [SP, #160]

0x52064c ORR	X6, XZR, X0

0x520650 LDP	X12, X9, [SP, #144]

0x520654 LDR	X8, [SP, #184]

0x520658 B.EQ	520ab4

0x52065c CMP	X11, #0

0x520660 B.LE	5207f0

0x520664 CMP	X24, #0

0x520668 B.LE	5207f0

0x52066c CMP	X28, #1

0x520670 LDR	X30, [SP, #168]

0x520674 B.NE	520aec

0x520678 LDR	X14, [SP, #136]

0x52067c ADD	X12, X27, X11,LSL #3

0x520680 MOVZ	X28, #0

0x520684 UBFM	X11, X14, #61, #60

(3358) 0x520688 LDP	X25, X17, [X27]

(3358) 0x52068c CMP	X17, X25

(3358) 0x520690 B.LE	5207e0

(3358) 0x520694 ADD	X5, X9, X28,LSL #3

(3358) 0x520698 MOVZ	X7, #0

(3358) 0x52069c MOVZ	X16, #0

  (3360) 0x5206a0 SUB	X1, X17, X25

  (3360) 0x5206a4 ORR	X0, XZR, X25

  (3360) 0x5206a8 ANDS	X10, X1, #0x3

  (3360) 0x5206ac B.EQ	520734

  (3360) 0x5206b0 CMP	X10, #1

  (3360) 0x5206b4 B.EQ	520708

  (3360) 0x5206b8 CMP	X10, #2

  (3360) 0x5206bc B.EQ	5206e4

  (3360) 0x5206c0 LDR	X13, [X21, X25,LSL #3]

  (3360) 0x5206c4 ADD	X0, X25, #1

  (3360) 0x5206c8 LDR	D17, [X20, X25,LSL #3]

  (3360) 0x5206cc LDR	D19, [X5]

  (3360) 0x5206d0 ADD	X15, X7, X13

  (3360) 0x5206d4 UBFM	X18, X15, #61, #60

  (3360) 0x5206d8 LDR	D18, [X19, X18]

  (3360) 0x5206dc FMADD	D28, D19, D17, D18

  (3360) 0x5206e0 STR	D28, [X19, X18]

  (3360) 0x5206e4 LDR	X4, [X21, X0,LSL #3]

  (3360) 0x5206e8 LDR	D29, [X20, X0,LSL #3]

  (3360) 0x5206ec ADD	X0, X0, #1

  (3360) 0x5206f0 LDR	D25, [X5]

  (3360) 0x5206f4 ADD	X3, X7, X4

  (3360) 0x5206f8 UBFM	X2, X3, #61, #60

  (3360) 0x5206fc LDR	D20, [X19, X2]

  (3360) 0x520700 FMADD	D27, D25, D29, D20

  (3360) 0x520704 STR	D27, [X19, X2]

  (3360) 0x520708 LDR	X14, [X21, X0,LSL #3]

  (3360) 0x52070c LDR	D26, [X20, X0,LSL #3]

  (3360) 0x520710 ADD	X0, X0, #1

  (3360) 0x520714 LDR	D22, [X5]

  (3360) 0x520718 ADD	X1, X7, X14

  (3360) 0x52071c UBFM	X10, X1, #61, #60

  (3360) 0x520720 LDR	D21, [X19, X10]

  (3360) 0x520724 FMADD	D24, D22, D26, D21

  (3360) 0x520728 STR	D24, [X19, X10]

  (3360) 0x52072c CMP	X0, X17

  (3360) 0x520730 B.EQ	5207cc

    (3359) 0x520734 LDR	X15, [X21, X0,LSL #3]

    (3359) 0x520738 ADD	X18, X0, #1

    (3359) 0x52073c ADD	X13, X0, #3

    (3359) 0x520740 ADD	X14, X0, #2

    (3359) 0x520744 LDR	D23, [X20, X0,LSL #3]

    (3359) 0x520748 ADD	X0, X0, #4

    (3359) 0x52074c LDR	D13, [X5]

    (3359) 0x520750 ADD	X4, X7, X15

    (3359) 0x520754 UBFM	X10, X4, #61, #60

    (3359) 0x520758 LDR	X3, [X21, X18,LSL #3]

    (3359) 0x52075c LDR	D14, [X19, X10]

    (3359) 0x520760 LDR	X2, [X21, X14,LSL #3]

    (3359) 0x520764 ADD	X1, X7, X3

    (3359) 0x520768 UBFM	X15, X1, #61, #60

    (3359) 0x52076c LDR	X4, [X21, X13,LSL #3]

    (3359) 0x520770 FMADD	D31, D13, D23, D14

    (3359) 0x520774 ADD	X3, X7, X2

    (3359) 0x520778 UBFM	X2, X3, #61, #60

    (3359) 0x52077c ADD	X1, X7, X4

    (3359) 0x520780 UBFM	X4, X1, #61, #60

    (3359) 0x520784 STR	D31, [X19, X10]

    (3359) 0x520788 LDR	D6, [X20, X18,LSL #3]

    (3359) 0x52078c LDR	D5, [X19, X15]

    (3359) 0x520790 LDR	D0, [X5]

    (3359) 0x520794 FMADD	D1, D0, D6, D5

    (3359) 0x520798 STR	D1, [X19, X15]

    (3359) 0x52079c LDR	D4, [X20, X14,LSL #3]

    (3359) 0x5207a0 LDR	D2, [X19, X2]

    (3359) 0x5207a4 LDR	D3, [X5]

    (3359) 0x5207a8 FMADD	D7, D3, D4, D2

    (3359) 0x5207ac STR	D7, [X19, X2]

    (3359) 0x5207b0 LDR	D30, [X20, X13,LSL #3]

    (3359) 0x5207b4 LDR	D16, [X19, X4]

    (3359) 0x5207b8 LDR	D17, [X5]

    (3359) 0x5207bc FMADD	D18, D17, D30, D16

    (3359) 0x5207c0 STR	D18, [X19, X4]

    (3359) 0x5207c4 CMP	X0, X17

    (3359) 0x5207c8 B.NE	520734

  (3360) 0x5207cc ADD	X16, X16, #1

  (3360) 0x5207d0 ADD	X7, X7, X26

  (3360) 0x5207d4 ADD	X5, X5, X11

  (3360) 0x5207d8 CMP	X24, X16

  (3360) 0x5207dc B.NE	5206a0

(3358) 0x5207e0 ADD	X27, X27, #8

(3358) 0x5207e4 ADD	X28, X28, X30

(3358) 0x5207e8 CMP	X27, X12

(3358) 0x5207ec B.NE	520688

0x5207f0 ORR	X0, XZR, X6

0x5207f4 STR	X8, [SP, #136]

0x5207f8 BL	5294c0

0x5207fc FMOV	D19, #1.0000000

0x520800 LDR	X8, [SP, #136]

0x520804 FCMP	D15, D19

0x520808 B.EQ	5205fc

0x52080c LDR	X21, [SP, #128]

0x520810 ADRP	X20,

0x520814 MOVZ	W3, #0

0x520818 ADD	X0, X20, #1512

0x52081c MOVZ	W2, #0

0x520820 STR	X8, [SP, #136]

0x520824 ADD	X1, SP, #192

0x520828 STR	D15, [SP, #192]

0x52082c STR	X24, [SP, #216]

0x520830 STP	X21, X19, [SP, #200]

0x520834 BL	410430

0x520838 LDR	X8, [SP, #136]

0x52083c CMP	X8, X23

0x520840 B.NE	520604

0x520844 LDR	X0, [SP, #176]

0x520848 BL	5222e4

0x52084c B	520604

0x520850 CMP	X7, X25

0x520854 CSINC	X10, XZR, XZR, #0

0x520858 UBFM	X22, X10, #63, #62

0x52085c FCMP	D15, #0

0x520860 B.NE	5203d4

0x520864 LDR	X27, [SP, #128]

0x520868 ADRP	X23,

0x52086c MOVZ	W3, #0

0x520870 ADD	X0, X23, #128

0x520874 MOVZ	W2, #0

0x520878 STR	D14, [SP, #192]

0x52087c ADD	X1, SP, #192

0x520880 STR	X24, [SP, #216]

0x520884 STP	X27, X19, [SP, #200]

0x520888 BL	410430

0x52088c B	520604

0x520890 LDR	X9, [SP, #128]

0x520894 ADRP	X8,

0x520898 MOVZ	W3, #0

0x52089c ADD	X0, X8, #896

0x5208a0 MOVZ	W2, #0

0x5208a4 STR	X24, [SP, #208]

0x5208a8 ADD	X1, SP, #192

0x5208ac STR	D13, [SP, #216]

0x5208b0 STP	X9, X19, [SP, #192]

0x5208b4 BL	410430

0x5208b8 LDP	X14, X11, [SP, #144]

0x5208bc LDP	X12, X15, [SP, #160]

0x5208c0 STP	X14, X11, [SP, #144]

0x5208c4 STP	X12, X15, [SP, #160]

0x5208c8 BL	52c060

0x5208cc CMP	X0, #1

0x5208d0 LDP	X9, X11, [SP, #144]

0x5208d4 ORR	X18, XZR, X0

0x5208d8 LDP	X12, X8, [SP, #160]

0x5208dc B.LE	52044c

0x5208e0 B	52062c

(3370) 0x5208e4 ADD	X14, X14, #1

(3370) 0x5208e8 ADD	X15, X15, X12

(3370) 0x5208ec CMP	X11, X14

(3370) 0x5208f0 B.NE	520478

0x5208f4 B	5205f0

0x5208f8 ORR	X0, XZR, X15

0x5208fc STP	X15, X11, [SP, #144]

0x520900 STR	X12, [SP, #160]

0x520904 BL	522b40

0x520908 LDR	X14, [X0]

0x52090c LDP	X15, X11, [SP, #144]

0x520910 STR	X0, [SP, #176]

0x520914 LDR	X12, [SP, #160]

0x520918 B	5203e0

0x52091c CMP	X24, #1

0x520920 B.EQ	520dd8

0x520924 MOVZ	X17, #0

0x520928 MOVZ	X15, #0

0x52092c ADD	X1, X27, #8

(3363) 0x520930 CMP	X24, #0

(3363) 0x520934 B.LE	5205f0

  (3366) 0x520938 LDR	X13, [X27, X15,LSL #3]

  (3366) 0x52093c LDR	X16, [X1, X15,LSL #3]

  (3366) 0x520940 CMP	X13, X16

  (3366) 0x520944 B.GE	520c74

  (3366) 0x520948 ADD	X6, X9, X17,LSL #3

  (3366) 0x52094c MOVZ	X7, #0

  (3366) 0x520950 MOVZ	X10, #0

  (3366) 0x520954 HINT	#0

  (3366) 0x520958 HINT	#0

  (3366) 0x52095c HINT	#0

    (3365) 0x520960 SUB	X2, X16, X13

    (3365) 0x520964 ORR	X0, XZR, X13

    (3365) 0x520968 ANDS	X3, X2, #0x3

    (3365) 0x52096c B.EQ	5209f4

    (3365) 0x520970 CMP	X3, #1

    (3365) 0x520974 B.EQ	5209c8

    (3365) 0x520978 CMP	X3, #2

    (3365) 0x52097c B.EQ	5209a4

    (3365) 0x520980 LDR	X4, [X21, X13,LSL #3]

    (3365) 0x520984 ADD	X0, X13, #1

    (3365) 0x520988 LDR	D6, [X20, X13,LSL #3]

    (3365) 0x52098c LDR	D0, [X6]

    (3365) 0x520990 MADD	X5, X28, X4, X7

    (3365) 0x520994 UBFM	X14, X5, #61, #60

    (3365) 0x520998 LDR	D5, [X19, X14]

    (3365) 0x52099c FMADD	D1, D6, D0, D5

    (3365) 0x5209a0 STR	D1, [X19, X14]

    (3365) 0x5209a4 LDR	X18, [X21, X0,LSL #3]

    (3365) 0x5209a8 LDR	D4, [X20, X0,LSL #3]

    (3365) 0x5209ac ADD	X0, X0, #1

    (3365) 0x5209b0 LDR	D3, [X6]

    (3365) 0x5209b4 MADD	X30, X28, X18, X7

    (3365) 0x5209b8 UBFM	X2, X30, #61, #60

    (3365) 0x5209bc LDR	D2, [X19, X2]

    (3365) 0x5209c0 FMADD	D7, D4, D3, D2

    (3365) 0x5209c4 STR	D7, [X19, X2]

    (3365) 0x5209c8 LDR	X3, [X21, X0,LSL #3]

    (3365) 0x5209cc LDR	D30, [X20, X0,LSL #3]

    (3365) 0x5209d0 ADD	X0, X0, #1

    (3365) 0x5209d4 LDR	D17, [X6]

    (3365) 0x5209d8 MADD	X4, X28, X3, X7

    (3365) 0x5209dc UBFM	X5, X4, #61, #60

    (3365) 0x5209e0 LDR	D16, [X19, X5]

    (3365) 0x5209e4 FMADD	D18, D30, D17, D16

    (3365) 0x5209e8 STR	D18, [X19, X5]

    (3365) 0x5209ec CMP	X0, X16

    (3365) 0x5209f0 B.EQ	520a8c

      (3364) 0x5209f4 LDR	X2, [X21, X0,LSL #3]

      (3364) 0x5209f8 ADD	X14, X0, #1

      (3364) 0x5209fc ADD	X30, X0, #2

      (3364) 0x520a00 ADD	X18, X0, #3

      (3364) 0x520a04 LDR	D19, [X20, X0,LSL #3]

      (3364) 0x520a08 ADD	X0, X0, #4

      (3364) 0x520a0c LDR	D29, [X6]

      (3364) 0x520a10 MADD	X3, X28, X2, X7

      (3364) 0x520a14 LDR	X4, [X21, X14,LSL #3]

      (3364) 0x520a18 UBFM	X5, X3, #61, #60

      (3364) 0x520a1c LDR	X2, [X21, X30,LSL #3]

      (3364) 0x520a20 LDR	D28, [X19, X5]

      (3364) 0x520a24 MADD	X4, X28, X4, X7

      (3364) 0x520a28 MADD	X3, X28, X2, X7

      (3364) 0x520a2c LDR	X2, [X21, X18,LSL #3]

      (3364) 0x520a30 UBFM	X4, X4, #61, #60

      (3364) 0x520a34 FMADD	D20, D19, D29, D28

      (3364) 0x520a38 UBFM	X3, X3, #61, #60

      (3364) 0x520a3c MADD	X2, X28, X2, X7

      (3364) 0x520a40 UBFM	X2, X2, #61, #60

      (3364) 0x520a44 STR	D20, [X19, X5]

      (3364) 0x520a48 LDR	D27, [X20, X14,LSL #3]

      (3364) 0x520a4c LDR	D25, [X19, X4]

      (3364) 0x520a50 LDR	D26, [X6]

      (3364) 0x520a54 FMADD	D21, D27, D26, D25

      (3364) 0x520a58 STR	D21, [X19, X4]

      (3364) 0x520a5c LDR	D24, [X20, X30,LSL #3]

      (3364) 0x520a60 LDR	D22, [X19, X3]

      (3364) 0x520a64 LDR	D23, [X6]

      (3364) 0x520a68 FMADD	D14, D24, D23, D22

      (3364) 0x520a6c STR	D14, [X19, X3]

      (3364) 0x520a70 LDR	D13, [X20, X18,LSL #3]

      (3364) 0x520a74 LDR	D31, [X19, X2]

      (3364) 0x520a78 LDR	D6, [X6]

      (3364) 0x520a7c FMADD	D5, D13, D6, D31

      (3364) 0x520a80 STR	D5, [X19, X2]

      (3364) 0x520a84 CMP	X0, X16

      (3364) 0x520a88 B.NE	5209f4

    (3365) 0x520a8c ADD	X10, X10, #1

    (3365) 0x520a90 ADD	X7, X7, X26

    (3365) 0x520a94 ADD	X6, X6, X25

    (3365) 0x520a98 CMP	X24, X10

    (3365) 0x520a9c B.NE	520960

  (3366) 0x520aa0 ADD	X15, X15, #1

  (3366) 0x520aa4 ADD	X17, X17, X12

  (3366) 0x520aa8 CMP	X11, X15

  (3366) 0x520aac B.NE	520938

0x520ab0 B	5205f0

0x520ab4 ADRP	X26,

0x520ab8 MOVZ	W3, #0

0x520abc STP	X6, X8, [SP, #136]

0x520ac0 ADD	X0, X26, #2128

0x520ac4 MOVZ	W2, #0

0x520ac8 ADD	X1, SP, #192

0x520acc STP	X20, X27, [SP, #192]

0x520ad0 STP	X21, X11, [SP, #208]

0x520ad4 STP	X9, X19, [SP, #224]

0x520ad8 STP	X25, X6, [SP, #240]

0x520adc STR	X12, [SP, #256]

0x520ae0 BL	410430

0x520ae4 LDP	X6, X8, [SP, #136]

0x520ae8 B	5207f0

0x520aec LDR	X25, [SP, #136]

0x520af0 ADD	X1, X27, X11,LSL #3

0x520af4 MOVZ	X14, #0

0x520af8 UBFM	X12, X25, #61, #60

(3355) 0x520afc LDP	X13, X16, [X27]

(3355) 0x520b00 ADD	X10, X9, X14,LSL #3

(3355) 0x520b04 MOVZ	X7, #0

(3355) 0x520b08 MOVZ	X11, #0

(3355) 0x520b0c CMP	X13, X16

(3355) 0x520b10 B.GE	520c60

(3355) 0x520b14 HINT	#0

(3355) 0x520b18 HINT	#0

(3355) 0x520b1c HINT	#0

  (3357) 0x520b20 SUB	X15, X16, X13

  (3357) 0x520b24 ORR	X0, XZR, X13

  (3357) 0x520b28 ANDS	X18, X15, #0x3

  (3357) 0x520b2c B.EQ	520bb4

  (3357) 0x520b30 CMP	X18, #1

  (3357) 0x520b34 B.EQ	520b88

  (3357) 0x520b38 CMP	X18, #2

  (3357) 0x520b3c B.EQ	520b64

  (3357) 0x520b40 LDR	X5, [X21, X13,LSL #3]

  (3357) 0x520b44 ADD	X0, X13, #1

  (3357) 0x520b48 LDR	D30, [X20, X13,LSL #3]

  (3357) 0x520b4c LDR	D17, [X10]

  (3357) 0x520b50 MADD	X4, X28, X5, X7

  (3357) 0x520b54 UBFM	X3, X4, #61, #60

  (3357) 0x520b58 LDR	D16, [X19, X3]

  (3357) 0x520b5c FMADD	D18, D30, D17, D16

  (3357) 0x520b60 STR	D18, [X19, X3]

  (3357) 0x520b64 LDR	X2, [X21, X0,LSL #3]

  (3357) 0x520b68 LDR	D19, [X20, X0,LSL #3]

  (3357) 0x520b6c ADD	X0, X0, #1

  (3357) 0x520b70 LDR	D29, [X10]

  (3357) 0x520b74 MADD	X17, X28, X2, X7

  (3357) 0x520b78 UBFM	X25, X17, #61, #60

  (3357) 0x520b7c LDR	D28, [X19, X25]

  (3357) 0x520b80 FMADD	D20, D19, D29, D28

  (3357) 0x520b84 STR	D20, [X19, X25]

  (3357) 0x520b88 LDR	X15, [X21, X0,LSL #3]

  (3357) 0x520b8c LDR	D25, [X20, X0,LSL #3]

  (3357) 0x520b90 ADD	X0, X0, #1

  (3357) 0x520b94 LDR	D26, [X10]

  (3357) 0x520b98 MADD	X18, X28, X15, X7

  (3357) 0x520b9c UBFM	X5, X18, #61, #60

  (3357) 0x520ba0 LDR	D27, [X19, X5]

  (3357) 0x520ba4 FMADD	D21, D25, D26, D27

  (3357) 0x520ba8 STR	D21, [X19, X5]

  (3357) 0x520bac CMP	X0, X16

  (3357) 0x520bb0 B.EQ	520c4c

    (3356) 0x520bb4 LDR	X4, [X21, X0,LSL #3]

    (3356) 0x520bb8 ADD	X25, X0, #1

    (3356) 0x520bbc ADD	X15, X0, #2

    (3356) 0x520bc0 ADD	X17, X0, #3

    (3356) 0x520bc4 LDR	D22, [X20, X0,LSL #3]

    (3356) 0x520bc8 ADD	X0, X0, #4

    (3356) 0x520bcc LDR	D23, [X10]

    (3356) 0x520bd0 MADD	X3, X28, X4, X7

    (3356) 0x520bd4 LDR	X2, [X21, X25,LSL #3]

    (3356) 0x520bd8 UBFM	X18, X3, #61, #60

    (3356) 0x520bdc LDR	X5, [X21, X15,LSL #3]

    (3356) 0x520be0 LDR	D24, [X19, X18]

    (3356) 0x520be4 MADD	X4, X28, X2, X7

    (3356) 0x520be8 LDR	X2, [X21, X17,LSL #3]

    (3356) 0x520bec MADD	X3, X28, X5, X7

    (3356) 0x520bf0 UBFM	X5, X4, #61, #60

    (3356) 0x520bf4 FMADD	D14, D22, D23, D24

    (3356) 0x520bf8 UBFM	X4, X3, #61, #60

    (3356) 0x520bfc MADD	X3, X28, X2, X7

    (3356) 0x520c00 UBFM	X2, X3, #61, #60

    (3356) 0x520c04 STR	D14, [X19, X18]

    (3356) 0x520c08 LDR	D13, [X20, X25,LSL #3]

    (3356) 0x520c0c LDR	D31, [X19, X5]

    (3356) 0x520c10 LDR	D6, [X10]

    (3356) 0x520c14 FMADD	D5, D13, D6, D31

    (3356) 0x520c18 STR	D5, [X19, X5]

    (3356) 0x520c1c LDR	D0, [X20, X15,LSL #3]

    (3356) 0x520c20 LDR	D1, [X19, X4]

    (3356) 0x520c24 LDR	D4, [X10]

    (3356) 0x520c28 FMADD	D2, D0, D4, D1

    (3356) 0x520c2c STR	D2, [X19, X4]

    (3356) 0x520c30 LDR	D3, [X20, X17,LSL #3]

    (3356) 0x520c34 LDR	D7, [X19, X2]

    (3356) 0x520c38 LDR	D30, [X10]

    (3356) 0x520c3c FMADD	D16, D3, D30, D7

    (3356) 0x520c40 STR	D16, [X19, X2]

    (3356) 0x520c44 CMP	X0, X16

    (3356) 0x520c48 B.NE	520bb4

  (3357) 0x520c4c ADD	X11, X11, #1

  (3357) 0x520c50 ADD	X7, X7, X26

  (3357) 0x520c54 ADD	X10, X10, X12

  (3357) 0x520c58 CMP	X24, X11

  (3357) 0x520c5c B.NE	520b20

(3355) 0x520c60 ADD	X27, X27, #8

(3355) 0x520c64 ADD	X14, X14, X30

(3355) 0x520c68 CMP	X27, X1

(3355) 0x520c6c B.NE	520afc

0x520c70 B	5207f0

(3363) 0x520c74 ADD	X15, X15, #1

(3363) 0x520c78 ADD	X17, X17, X12

(3363) 0x520c7c CMP	X11, X15

(3363) 0x520c80 B.NE	520930

0x520c84 B	5205f0

0x520c88 MOVZ	X26, #0

0x520c8c ADD	X25, X27, #8

(3367) 0x520c90 LDR	X0, [X27, X26,LSL #3]

(3367) 0x520c94 LDR	X12, [X25, X26,LSL #3]

(3367) 0x520c98 CMP	X12, X0

(3367) 0x520c9c B.LE	520dc8

  (3369) 0x520ca0 SUB	X16, X12, X0

  (3369) 0x520ca4 ANDS	X10, X16, #0x3

  (3369) 0x520ca8 B.EQ	520d24

  (3369) 0x520cac CMP	X10, #1

  (3369) 0x520cb0 B.EQ	520cfc

  (3369) 0x520cb4 CMP	X10, #2

  (3369) 0x520cb8 B.EQ	520cdc

  (3369) 0x520cbc LDR	X17, [X21, X0,LSL #3]

  (3369) 0x520cc0 LDR	D7, [X20, X0,LSL #3]

  (3369) 0x520cc4 ADD	X0, X0, #1

  (3369) 0x520cc8 LDR	D3, [X9, X26,LSL #3]

  (3369) 0x520ccc UBFM	X14, X17, #61, #60

  (3369) 0x520cd0 LDR	D30, [X19, X14]

  (3369) 0x520cd4 FMADD	D16, D3, D7, D30

  (3369) 0x520cd8 STR	D16, [X19, X14]

  (3369) 0x520cdc LDR	X15, [X21, X0,LSL #3]

  (3369) 0x520ce0 LDR	D18, [X20, X0,LSL #3]

  (3369) 0x520ce4 ADD	X0, X0, #1

  (3369) 0x520ce8 LDR	D17, [X9, X26,LSL #3]

  (3369) 0x520cec UBFM	X30, X15, #61, #60

  (3369) 0x520cf0 LDR	D19, [X19, X30]

  (3369) 0x520cf4 FMADD	D28, D17, D18, D19

  (3369) 0x520cf8 STR	D28, [X19, X30]

  (3369) 0x520cfc LDR	X18, [X21, X0,LSL #3]

  (3369) 0x520d00 LDR	D20, [X20, X0,LSL #3]

  (3369) 0x520d04 ADD	X0, X0, #1

  (3369) 0x520d08 LDR	D29, [X9, X26,LSL #3]

  (3369) 0x520d0c UBFM	X28, X18, #61, #60

  (3369) 0x520d10 LDR	D27, [X19, X28]

  (3369) 0x520d14 FMADD	D25, D29, D20, D27

  (3369) 0x520d18 STR	D25, [X19, X28]

  (3369) 0x520d1c CMP	X0, X12

  (3369) 0x520d20 B.EQ	520dac

    (3368) 0x520d24 LDR	X13, [X21, X0,LSL #3]

    (3368) 0x520d28 ADD	X1, X0, #1

    (3368) 0x520d2c ADD	X7, X0, #3

    (3368) 0x520d30 ADD	X6, X0, #2

    (3368) 0x520d34 LDR	D21, [X20, X0,LSL #3]

    (3368) 0x520d38 ADD	X0, X0, #4

    (3368) 0x520d3c LDR	D26, [X9, X26,LSL #3]

    (3368) 0x520d40 UBFM	X5, X13, #61, #60

    (3368) 0x520d44 LDR	X4, [X21, X1,LSL #3]

    (3368) 0x520d48 LDR	D24, [X19, X5]

    (3368) 0x520d4c LDR	X3, [X21, X6,LSL #3]

    (3368) 0x520d50 UBFM	X16, X4, #61, #60

    (3368) 0x520d54 LDR	X2, [X21, X7,LSL #3]

    (3368) 0x520d58 FMADD	D22, D26, D21, D24

    (3368) 0x520d5c UBFM	X10, X3, #61, #60

    (3368) 0x520d60 UBFM	X17, X2, #61, #60

    (3368) 0x520d64 STR	D22, [X19, X5]

    (3368) 0x520d68 LDR	D23, [X9, X26,LSL #3]

    (3368) 0x520d6c LDR	D14, [X20, X1,LSL #3]

    (3368) 0x520d70 LDR	D13, [X19, X16]

    (3368) 0x520d74 FMADD	D31, D23, D14, D13

    (3368) 0x520d78 STR	D31, [X19, X16]

    (3368) 0x520d7c LDR	D6, [X9, X26,LSL #3]

    (3368) 0x520d80 LDR	D5, [X20, X6,LSL #3]

    (3368) 0x520d84 LDR	D0, [X19, X10]

    (3368) 0x520d88 FMADD	D1, D6, D5, D0

    (3368) 0x520d8c STR	D1, [X19, X10]

    (3368) 0x520d90 LDR	D4, [X9, X26,LSL #3]

    (3368) 0x520d94 LDR	D2, [X20, X7,LSL #3]

    (3368) 0x520d98 LDR	D3, [X19, X17]

    (3368) 0x520d9c FMADD	D7, D4, D2, D3

    (3368) 0x520da0 STR	D7, [X19, X17]

    (3368) 0x520da4 CMP	X0, X12

    (3368) 0x520da8 B.NE	520d24

  (3369) 0x520dac ADD	X26, X26, #1

  (3369) 0x520db0 CMP	X26, X11

  (3369) 0x520db4 B.EQ	5205f0

  (3369) 0x520db8 LDR	X0, [X27, X26,LSL #3]

  (3369) 0x520dbc LDR	X12, [X25, X26,LSL #3]

  (3369) 0x520dc0 CMP	X12, X0

  (3369) 0x520dc4 B.GT	520ca0

(3367) 0x520dc8 ADD	X26, X26, #1

(3367) 0x520dcc CMP	X11, X26

(3367) 0x520dd0 B.NE	520c90

0x520dd4 B	5205f0

0x520dd8 MOVZ	X1, #0

0x520ddc ADD	X13, X27, #8

(3361) 0x520de0 LDR	X0, [X27, X1,LSL #3]

(3361) 0x520de4 LDR	X16, [X13, X1,LSL #3]

(3361) 0x520de8 CMP	X0, X16

(3361) 0x520dec B.GE	520efc

(3361) 0x520df0 SUB	X14, X16, X0

(3361) 0x520df4 ANDS	X18, X14, #0x3

(3361) 0x520df8 B.EQ	520e74

(3361) 0x520dfc CMP	X18, #1

(3361) 0x520e00 B.EQ	520e4c

(3361) 0x520e04 CMP	X18, #2

(3361) 0x520e08 B.EQ	520e2c

(3361) 0x520e0c LDR	X30, [X21, X0,LSL #3]

(3361) 0x520e10 LDR	D0, [X20, X0,LSL #3]

(3361) 0x520e14 ADD	X0, X0, #1

(3361) 0x520e18 LDR	D1, [X9, X1,LSL #3]

(3361) 0x520e1c UBFM	X5, X30, #61, #60

(3361) 0x520e20 LDR	D4, [X19, X5]

(3361) 0x520e24 FMADD	D2, D0, D1, D4

(3361) 0x520e28 STR	D2, [X19, X5]

(3361) 0x520e2c LDR	X4, [X21, X0,LSL #3]

(3361) 0x520e30 LDR	D3, [X20, X0,LSL #3]

(3361) 0x520e34 ADD	X0, X0, #1

(3361) 0x520e38 LDR	D7, [X9, X1,LSL #3]

(3361) 0x520e3c UBFM	X3, X4, #61, #60

(3361) 0x520e40 LDR	D30, [X19, X3]

(3361) 0x520e44 FMADD	D16, D3, D7, D30

(3361) 0x520e48 STR	D16, [X19, X3]

(3361) 0x520e4c LDR	X2, [X21, X0,LSL #3]

(3361) 0x520e50 LDR	D17, [X20, X0,LSL #3]

(3361) 0x520e54 ADD	X0, X0, #1

(3361) 0x520e58 LDR	D18, [X9, X1,LSL #3]

(3361) 0x520e5c UBFM	X10, X2, #61, #60

(3361) 0x520e60 LDR	D19, [X19, X10]

(3361) 0x520e64 FMADD	D28, D17, D18, D19

(3361) 0x520e68 STR	D28, [X19, X10]

(3361) 0x520e6c CMP	X0, X16

(3361) 0x520e70 B.EQ	520efc

  (3362) 0x520e74 LDR	X7, [X21, X0,LSL #3]

  (3362) 0x520e78 ADD	X6, X0, #1

  (3362) 0x520e7c ADD	X25, X0, #3

  (3362) 0x520e80 ADD	X12, X0, #2

  (3362) 0x520e84 LDR	D29, [X20, X0,LSL #3]

  (3362) 0x520e88 ADD	X0, X0, #4

  (3362) 0x520e8c LDR	D20, [X9, X1,LSL #3]

  (3362) 0x520e90 UBFM	X26, X7, #61, #60

  (3362) 0x520e94 LDR	X28, [X21, X6,LSL #3]

  (3362) 0x520e98 LDR	D27, [X19, X26]

  (3362) 0x520e9c LDR	X17, [X21, X12,LSL #3]

  (3362) 0x520ea0 UBFM	X15, X28, #61, #60

  (3362) 0x520ea4 LDR	X18, [X21, X25,LSL #3]

  (3362) 0x520ea8 FMADD	D25, D29, D20, D27

  (3362) 0x520eac UBFM	X14, X17, #61, #60

  (3362) 0x520eb0 UBFM	X30, X18, #61, #60

  (3362) 0x520eb4 STR	D25, [X19, X26]

  (3362) 0x520eb8 LDR	D26, [X20, X6,LSL #3]

  (3362) 0x520ebc LDR	D21, [X9, X1,LSL #3]

  (3362) 0x520ec0 LDR	D24, [X19, X15]

  (3362) 0x520ec4 FMADD	D22, D26, D21, D24

  (3362) 0x520ec8 STR	D22, [X19, X15]

  (3362) 0x520ecc LDR	D23, [X20, X12,LSL #3]

  (3362) 0x520ed0 LDR	D14, [X9, X1,LSL #3]

  (3362) 0x520ed4 LDR	D13, [X19, X14]

  (3362) 0x520ed8 FMADD	D31, D23, D14, D13

  (3362) 0x520edc STR	D31, [X19, X14]

  (3362) 0x520ee0 LDR	D6, [X20, X25,LSL #3]

  (3362) 0x520ee4 LDR	D5, [X9, X1,LSL #3]

  (3362) 0x520ee8 LDR	D0, [X19, X30]

  (3362) 0x520eec FMADD	D1, D6, D5, D0

  (3362) 0x520ef0 STR	D1, [X19, X30]

  (3362) 0x520ef4 CMP	X0, X16

  (3362) 0x520ef8 B.NE	520e74

(3361) 0x520efc ADD	X1, X1, #1

(3361) 0x520f00 CMP	X1, X11

(3361) 0x520f04 B.NE	520de0

0x520f08 B	5205f0

Coverage (%)	Name	Source Location	Module
►95.86+	hypre_ParCSRMatrixMatvecT	par_csr_matvec.c:439	exec
○	hypre_BoomerAMGCycle	par_cycle.c:435	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec
►4.14+	hypre_ParCSRMatrixMatvecT	par_csr_matvec.c:439	exec
○	hypre_BoomerAMGCycle	par_cycle.c:435	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:424	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	csr_matvec.c:445-648
Module	exec

The function is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:445-460,472,485-513,520-527,535,545-554,589-596,603-625,636-639,645-648.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.00 to 3.50 cycles (8.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 32% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 31.00 to 10.88 cycles (2.85x speedup).

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

2% of VPU loads are used in vector version.
2% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:548
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:603
hypre_NumThreads: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:545
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:545
hypre_SeqVectorCloneDeep: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:512
hypre_SeqVectorDestroy: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:645
hypre_error_handler: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:485
hypre_fprintf: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:485
unknown: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:527
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:639
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:502
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:535
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: divide

The binary function does not load or store any data.

General properties

nb instructions	235
nb uops	235
loop length	940
used w registers	2
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	80

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	29.38 cycles
front end	29.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	23.00	23.00	24.50	24.50	24.50	24.50	6.00	5.00	3.00	3.00	31.00	31.00	31.00	19.50	19.50
cycles	23.00	23.00	24.50	24.50	24.50	24.50	6.00	5.00	3.00	3.00	31.00	31.00	31.00	19.50	19.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	29.38
Dispatch	31.00
DIV/SQRT	1.75-3.50
Overall L1	31.00

Vectorization ratios

INT

all	1%
load	2%
store	2%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	1%
load	2%
store	2%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	33%
load	36%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	32%
load	36%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 520300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X15, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV D14, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X11, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X27, X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X14, X22, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X28, [X23, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X24, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X1, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X15, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X15, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR D15, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
FMOV D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X1, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5203b4 <hypre_CSRMatrixMatvecT+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <543370>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X4, <542374>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X5, <57037c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X3, #1256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X4, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X5, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X6, <543394>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X6, #1128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #485	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 520850 <hypre_CSRMatrixMatvecT+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MOVZ X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC X22, X13, XZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 520864 <hypre_CSRMatrixMatvecT+0x564>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X15, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5208f8 <hypre_CSRMatrixMatvecT+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D13, D14, D15	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D13, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 52042c <hypre_CSRMatrixMatvecT+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D13, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.NE 520890 <hypre_CSRMatrixMatvecT+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X16, <20051e400>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X16, #744	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X17, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410430 <@plt_start@+0x410>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52c060 <hypre_NumThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDP X9, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B.GT 52062c <hypre_CSRMatrixMatvecT+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X25, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 52091c <hypre_CSRMatrixMatvecT+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 520c88 <hypre_CSRMatrixMatvecT+0x988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D19, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D15, D19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 52080c <hypre_CSRMatrixMatvecT+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 520844 <hypre_CSRMatrixMatvecT+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP], #272	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X0, X25, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X18, X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X11, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X6, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B.EQ 520ab4 <hypre_CSRMatrixMatvecT+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 5207f0 <hypre_CSRMatrixMatvecT+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 5207f0 <hypre_CSRMatrixMatvecT+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X30, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B.NE 520aec <hypre_CSRMatrixMatvecT+0x7ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X12, X27, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X11, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 5294c0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D19, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FCMP D15, D19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 5205fc <hypre_CSRMatrixMatvecT+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X20, <20051e810>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X0, X20, #1512	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D15, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STR X24, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X21, X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410430 <@plt_start@+0x410>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 520604 <hypre_CSRMatrixMatvecT+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 5222e4 <hypre_SeqVectorDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 520604 <hypre_CSRMatrixMatvecT+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC X10, XZR, XZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X22, X10, #63, #62	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 5203d4 <hypre_CSRMatrixMatvecT+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X23, <20051e868>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X0, X23, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D14, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X27, X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410430 <@plt_start@+0x410>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 520604 <hypre_CSRMatrixMatvecT+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X8, <20051e894>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X0, X8, #896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D13, [SP, #216]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP X9, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410430 <@plt_start@+0x410>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52c060 <hypre_NumThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDP X9, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B.LE 52044c <hypre_CSRMatrixMatvecT+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 52062c <hypre_CSRMatrixMatvecT+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 522b40 <hypre_SeqVectorCloneDeep>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 5203e0 <hypre_CSRMatrixMatvecT+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 520dd8 <hypre_CSRMatrixMatvecT+0xad8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X26, <20051eab4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X6, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X0, X26, #2128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X20, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X11, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410430 <@plt_start@+0x410>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X6, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 5207f0 <hypre_CSRMatrixMatvecT+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X27, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X12, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 5207f0 <hypre_CSRMatrixMatvecT+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X25, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	csr_matvec.c:445-648
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 31.00 to 3.50 cycles (8.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

2% of VPU loads are used in vector version.
2% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

hypre_CAlloc: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:548
hypre_Free: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:603
hypre_NumThreads: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:545
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:545
hypre_SeqVectorCloneDeep: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:512
hypre_SeqVectorDestroy: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:645
hypre_error_handler: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:485
hypre_fprintf: 1 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:485
unknown: 5 occurrences►
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:527
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:639
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:502
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:535
- /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c:554

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: divide

The binary function does not load or store any data.

General properties

nb instructions	235
nb uops	235
loop length	940
used w registers	2
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	7
used q registers	0
used v registers	0
used z registers	0
nb stack references	80

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	29.38 cycles
front end	29.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	23.00	23.00	24.50	24.50	24.50	24.50	6.00	5.00	3.00	3.00	31.00	31.00	31.00	19.50	19.50
cycles	23.00	23.00	24.50	24.50	24.50	24.50	6.00	5.00	3.00	3.00	31.00	31.00	31.00	19.50	19.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	29.38
Dispatch	31.00
DIV/SQRT	1.75-3.50
Overall L1	31.00

Vectorization ratios

INT

all	1%
load	2%
store	2%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	1%
load	2%
store	2%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	33%
load	36%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	32%
load	36%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 31.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 520300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X15, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV D14, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X11, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X27, X21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X25, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X14, X22, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X28, [X23, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X24, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X1, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X15, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X15, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR D15, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
FMOV D15, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X1, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5203b4 <hypre_CSRMatrixMatvecT+0xb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X3, <543370>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X4, <542374>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X5, <57037c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X3, #1256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X4, #2000	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X5, #1776]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 529700 <hypre_fprintf>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X6, <543394>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X6, #1128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X1, #485	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 52cf20 <hypre_error_handler>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X7, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X11, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 520850 <hypre_CSRMatrixMatvecT+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
MOVZ X13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSINC X22, X13, XZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 520864 <hypre_CSRMatrixMatvecT+0x564>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR XZR, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X15, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 5208f8 <hypre_CSRMatrixMatvecT+0x5f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D13, D14, D15	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
FMOV D31, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D13, D31	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 52042c <hypre_CSRMatrixMatvecT+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D13, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
STP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.NE 520890 <hypre_CSRMatrixMatvecT+0x590>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X16, <20051e400>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X0, X16, #744	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X17, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410430 <@plt_start@+0x410>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52c060 <hypre_NumThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDP X9, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B.GT 52062c <hypre_CSRMatrixMatvecT+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
UBFM X25, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 52091c <hypre_CSRMatrixMatvecT+0x61c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 520c88 <hypre_CSRMatrixMatvecT+0x988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FMOV D19, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMP D15, D19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 52080c <hypre_CSRMatrixMatvecT+0x50c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 520844 <hypre_CSRMatrixMatvecT+0x544>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X0, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X29, X30, [SP], #272	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MUL X0, X25, X0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
MOVZ X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X18, X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X11, X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 529428 <hypre_CAlloc>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X11, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X6, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR X8, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B.EQ 520ab4 <hypre_CSRMatrixMatvecT+0x7b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 5207f0 <hypre_CSRMatrixMatvecT+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X24, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 5207f0 <hypre_CSRMatrixMatvecT+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR X30, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B.NE 520aec <hypre_CSRMatrixMatvecT+0x7ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X12, X27, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X28, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X11, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X0, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 5294c0 <hypre_Free>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D19, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FCMP D15, D19	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 5205fc <hypre_CSRMatrixMatvecT+0x2fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X20, <20051e810>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X0, X20, #1512	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D15, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STR X24, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X21, X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410430 <@plt_start@+0x410>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 520604 <hypre_CSRMatrixMatvecT+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 5222e4 <hypre_SeqVectorDestroy>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 520604 <hypre_CSRMatrixMatvecT+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSINC X10, XZR, XZR, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X22, X10, #63, #62	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
FCMP D15, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 5203d4 <hypre_CSRMatrixMatvecT+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X23, <20051e868>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X0, X23, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D14, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X27, X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410430 <@plt_start@+0x410>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 520604 <hypre_CSRMatrixMatvecT+0x304>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X8, <20051e894>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X0, X8, #896	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X24, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X1, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D13, [SP, #216]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP X9, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410430 <@plt_start@+0x410>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STP X14, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X12, X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 52c060 <hypre_NumThreads>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDP X9, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X18, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDP X12, X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B.LE 52044c <hypre_CSRMatrixMatvecT+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 52062c <hypre_CSRMatrixMatvecT+0x32c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 522b40 <hypre_SeqVectorCloneDeep>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X15, X11, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR X0, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 5203e0 <hypre_CSRMatrixMatvecT+0xe0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 520dd8 <hypre_CSRMatrixMatvecT+0xad8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X26, <20051eab4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X6, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X0, X26, #2128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X20, X27, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X21, X11, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X9, X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X25, X6, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X12, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410430 <@plt_start@+0x410>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X6, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 5207f0 <hypre_CSRMatrixMatvecT+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X1, X27, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UBFM X12, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 5207f0 <hypre_CSRMatrixMatvecT+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X25, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X27, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 5205f0 <hypre_CSRMatrixMatvecT+0x2f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	10.750002861023	3.1060452461243
1x2
1x4
1x8
1x16
1x24
1x32
1x40
1x48
1x56
1x64

Name	Coverage (%)	Time (s)
▼hypre_CSRMatrixMatvecT–	3.11	10.75
▼Loop 3370 - csr_matvec.c:608-625 - exec–	0.00	0.00
▼Loop 3373 - csr_matvec.c:608-625 - exec–	0.00	0.00
▼Loop 3372 - csr_matvec.c:620-625 - exec–	0.00	0.00
○Loop 3371 - csr_matvec.c:622-625 - exec	0.00	0.00
▼Loop 3363 - csr_matvec.c:608-625 - exec–	0.00	0.00
▼Loop 3366 - csr_matvec.c:608-625 - exec–	0.00	0.00
▼Loop 3365 - csr_matvec.c:620-625 - exec–	0.00	0.00
○Loop 3364 - csr_matvec.c:622-625 - exec	0.00	0.00
▼Loop 3355 - csr_matvec.c:589-596 - exec–	0.00	0.00
▼Loop 3357 - csr_matvec.c:591-596 - exec–	0.00	0.00
○Loop 3356 - csr_matvec.c:593-596 - exec	0.00	0.00
▼Loop 3358 - csr_matvec.c:589-596 - exec–	0.00	0.00
▼Loop 3360 - csr_matvec.c:591-596 - exec–	0.00	0.00
○Loop 3359 - csr_matvec.c:593-596 - exec	0.00	0.00
▼Loop 3361 - csr_matvec.c:608-615 - exec–	0.00	0.00
○Loop 3362 - csr_matvec.c:612-615 - exec	0.00	0.00
▼Loop 3367 - csr_matvec.c:608-615 - exec–	0.00	0.00
▼Loop 3369 - csr_matvec.c:608-615 - exec–	2.83	9.80
○Loop 3368 - csr_matvec.c:612-615 - exec	0.27	0.95

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency