OV - exec - Loop 3379

	Loop Id: 3379	Module: exec	Source: vector.c:337-337	Coverage: 0.56%

0x521770 LDR	Q20, [X17, X19]    [3]

0x521774 ADD	X2, X19, #32

0x521778 ADD	X6, X19, #64

0x52177c ADD	X5, X19, #96

0x521780 ADD	X0, X19, #128

0x521784 LDR	Q21, [X30, X19]    [2]

0x521788 ADD	X7, X19, #160

0x52178c ADD	X10, X19, #192

0x521790 ADD	X11, X19, #224

0x521794 STR	Q20, [X3, X19]    [4]

0x521798 STR	Q21, [X20, X19]    [1]

0x52179c ADD	X19, X19, #256

0x5217a0 LDR	Q22, [X17, X2]    [3]

0x5217a4 LDR	Q23, [X30, X2]    [2]

0x5217a8 STR	Q22, [X3, X2]    [4]

0x5217ac STR	Q23, [X20, X2]    [1]

0x5217b0 LDR	Q24, [X17, X6]    [3]

0x5217b4 LDR	Q25, [X30, X6]    [2]

0x5217b8 STR	Q24, [X3, X6]    [4]

0x5217bc STR	Q25, [X20, X6]    [1]

0x5217c0 LDR	Q26, [X17, X5]    [3]

0x5217c4 LDR	Q27, [X30, X5]    [2]

0x5217c8 STR	Q26, [X3, X5]    [4]

0x5217cc STR	Q27, [X20, X5]    [1]

0x5217d0 LDR	Q28, [X17, X0]    [3]

0x5217d4 LDR	Q29, [X30, X0]    [2]

0x5217d8 STR	Q28, [X3, X0]    [4]

0x5217dc STR	Q29, [X20, X0]    [1]

0x5217e0 LDR	Q30, [X17, X7]    [3]

0x5217e4 LDR	Q31, [X30, X7]    [2]

0x5217e8 STR	Q30, [X3, X7]    [4]

0x5217ec STR	Q31, [X20, X7]    [1]

0x5217f0 LDR	Q0, [X17, X10]    [3]

0x5217f4 LDR	Q1, [X30, X10]    [2]

0x5217f8 STR	Q0, [X3, X10]    [4]

0x5217fc STR	Q1, [X20, X10]    [1]

0x521800 LDR	Q2, [X17, X11]    [3]

0x521804 LDR	Q3, [X30, X11]    [2]

0x521808 STR	Q2, [X3, X11]    [4]

0x52180c STR	Q3, [X20, X11]    [1]

0x521810 CMP	X18, X19

0x521814 B.NE	521770

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 337 - 337

--------------------------------------------------------------------------------

337:       y_data[i] = x_data[i];

Coverage (%)	Name	Source Location	Module
►94.10+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_SeqVectorCopy	vector.c:343	exec
○	hypre_ParCSRRelax	ams.c:76	exec
○	hypre_BoomerAMGCycle	par_cycle.c:394	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:545	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec
►5.13+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_SeqVectorCopy	vector.c:343	exec
○	hypre_ParCSRRelax	ams.c:76	exec
○	hypre_BoomerAMGCycle	par_cycle.c:394	exec
○	hypre_BoomerAMGSolve	par_amg_solve.c:235	exec
○	hypre_PCGSolve	pcg.c:424	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►55.56+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►44.44+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_SeqVectorCopy	vector.c:343	exec
○	hypre_PCGSolve	pcg.c:417	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►92.31+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►7.69+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_SeqVectorCopy	vector.c:343	exec
○	hypre_PCGSolve	pcg.c:417	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Source Location	Module
►88.89+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►11.11+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_SeqVectorCopy	vector.c:343	exec
○	hypre_PCGSolve	pcg.c:417	exec
○	main	amg.c:419	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P10, P11, P12,
Function	hypre_SeqVectorCopy._omp_fn.0
Source	vector.c:337-337
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	5.33
Front-end cycles	5.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	2.25
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	10.67
P11 cycles	10.67
P12 cycles	10.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks	P10, P11, P12,
Function	hypre_SeqVectorCopy._omp_fn.0
Source	vector.c:337-337
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.67
CQA cycles if no scalar integer	10.67
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	5.33
Front-end cycles	5.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	2.25
P6 cycles	8.00
P7 cycles	8.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	10.67
P11 cycles	10.67
P12 cycles	10.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	42.00
Nb loads	NA
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	4.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_SeqVectorCopy._omp_fn.0
Source file and lines	vector.c:337-337
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:337.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 128 out of 256 bits (SSE/AVX-128 instructions on AVX/AVX2 processors). By fully vectorizing your loop, you can lower the cost of an iteration from 10.67 to 5.33 cycles (2.00x speedup).

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	42
nb uops	42
loop length	168
used w registers	0
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	16
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Dispatch	10.67
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 521770

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR Q20, [X17, X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X2, X19, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X6, X19, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X19, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X19, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q21, [X30, X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X7, X19, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X10, X19, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X11, X19, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR Q20, [X3, X19]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q21, [X20, X19]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X19, X19, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q22, [X17, X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q23, [X30, X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q22, [X3, X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q23, [X20, X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q24, [X17, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q25, [X30, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q24, [X3, X6]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q25, [X20, X6]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q26, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q27, [X30, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q26, [X3, X5]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q27, [X20, X5]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q28, [X17, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q29, [X30, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q28, [X3, X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q29, [X20, X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q30, [X17, X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q31, [X30, X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q30, [X3, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q31, [X20, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q0, [X17, X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q1, [X30, X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q0, [X3, X10]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q1, [X20, X10]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q2, [X17, X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q3, [X30, X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q2, [X3, X11]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q3, [X20, X11]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 521770 <hypre_SeqVectorCopy._omp_fn.0+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_SeqVectorCopy._omp_fn.0
Source file and lines	vector.c:337-337
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/seq_mv/vector.c:337.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	42
nb uops	42
loop length	168
used w registers	0
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	16
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.25 cycles
front end	5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	8.00	8.00	0.00	0.00	10.67	10.67	10.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.25
Dispatch	10.67
Data deps.	1.00
Overall L1	10.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.67 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 521770

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput	Vectorization
LDR Q20, [X17, X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X2, X19, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X6, X19, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X19, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X0, X19, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q21, [X30, X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
ADD X7, X19, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X10, X19, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X11, X19, #224	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR Q20, [X3, X19]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q21, [X20, X19]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
ADD X19, X19, #256	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR Q22, [X17, X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q23, [X30, X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q22, [X3, X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q23, [X20, X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q24, [X17, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q25, [X30, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q24, [X3, X6]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q25, [X20, X6]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q26, [X17, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q27, [X30, X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q26, [X3, X5]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q27, [X20, X5]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q28, [X17, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q29, [X30, X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q28, [X3, X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q29, [X20, X0]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q30, [X17, X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q31, [X30, X7]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q30, [X3, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q31, [X20, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q0, [X17, X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q1, [X30, X10]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q0, [X3, X10]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q1, [X20, X10]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
LDR Q2, [X17, X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDR Q3, [X30, X11]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
STR Q2, [X3, X11]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
STR Q3, [X20, X11]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	vect (50.0%)
CMP X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.NE 521770 <hypre_SeqVectorCopy._omp_fn.0+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	83.48	0	468.17	0	506.73	0	955.87	0	529.38	0	1786.46	0	1396.88	0	1450.16	0	1399.78	0	2163.13	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	1.9499999284744	0.56342202425003
1x2	2	83.48	83.48	2	0.024999998509884	0.012463591061532
1x4	1	468.17	468.17	4	0.014999999664724	0.0040637995116413
1x8	3	506.73	506.73	8	0.010000000707805	0.0062258583493531
1x16	4	955.87	955.87	16	0.0099999997764826	0.0038816842716187
1x24	13	529.38	529.38	24	0.0050000003539026	0.0073774079792202
1x32	5	1786.46	1786.46	32	0.0050000003539026	0.0023358445614576
1x40	7	1396.88	1396.88	40	0.0099999997764826	0.003160803578794
1x48	8	1450.16	1450.16	48	0.0099999997764826	0.0030347148422152
1x56	10	1399.78	1399.78	56	0.010000000707805	0.0031951183918864
1x64	8	2163.13	2163.13	64	0.0050000003539026	0.0020294256974012

Report Configuration

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency