OV - exec - Loop 710

	Loop Id: 710	Module: exec	Source: par_multi_interp.c:1593-1660 [...]	Coverage: 0.21%

0x45accc LDR	X16, [SP, #152]

0x45acd0 LDR	X30, [SP, #144]

0x45acd4 LDR	X3, [X16, X18,LSL #3]

0x45acd8 UBFM	X5, X3, #61, #60

0x45acdc ADD	X16, X5, #8

0x45ace0 LDR	X0, [X30, X5]

0x45ace4 LDR	X17, [X11, X16]

0x45ace8 LDR	X2, [X11, X5]

0x45acec ADD	X14, X0, X17

0x45acf0 SUB	X1, X14, X2

0x45acf4 CMP	X0, X1

0x45acf8 B.GE	45ae2c

0x45acfc LDR	X4, [SP, #192]

0x45ad00 UBFM	X17, X0, #61, #60

0x45ad04 LDR	X30, [X4, #8]

0x45ad08 ADD	X2, X30, X1,LSL #3

0x45ad0c ADD	X0, X30, X0,LSL #3

0x45ad10 SUB	X14, X2, X0

0x45ad14 SUB	X1, X14, #8

0x45ad18 UBFM	X4, X1, #3, #63

0x45ad1c ADD	X14, X4, #1

0x45ad20 ANDS	X1, X14, #0x7

0x45ad24 B.EQ	45adb8

0x45ad28 CMP	X1, #1

0x45ad2c B.EQ	45ada4

0x45ad30 CMP	X1, #2

0x45ad34 B.EQ	45ad98

0x45ad38 CMP	X1, #3

0x45ad3c B.EQ	45ad8c

0x45ad40 CMP	X1, #4

0x45ad44 B.EQ	45ad80

0x45ad48 CMP	X1, #5

0x45ad4c B.EQ	45ad74

0x45ad50 CMP	X1, #6

0x45ad54 B.EQ	45ad68

0x45ad58 LDR	X17, [X30, X17]

0x45ad5c ADD	X0, X0, #8

0x45ad60 LDR	X30, [X22, X17,LSL #3]

0x45ad64 STR	X3, [X20, X30,LSL #3]

0x45ad68 LDR	X4, [X0], #8

0x45ad6c LDR	X14, [X22, X4,LSL #3]

0x45ad70 STR	X3, [X20, X14,LSL #3]

0x45ad74 LDR	X1, [X0], #8

0x45ad78 LDR	X17, [X22, X1,LSL #3]

0x45ad7c STR	X3, [X20, X17,LSL #3]

0x45ad80 LDR	X30, [X0], #8

0x45ad84 LDR	X4, [X22, X30,LSL #3]

0x45ad88 STR	X3, [X20, X4,LSL #3]

0x45ad8c LDR	X14, [X0], #8

0x45ad90 LDR	X1, [X22, X14,LSL #3]

0x45ad94 STR	X3, [X20, X1,LSL #3]

0x45ad98 LDR	X17, [X0], #8

0x45ad9c LDR	X30, [X22, X17,LSL #3]

0x45ada0 STR	X3, [X20, X30,LSL #3]

0x45ada4 LDR	X4, [X0], #8

0x45ada8 LDR	X14, [X22, X4,LSL #3]

0x45adac STR	X3, [X20, X14,LSL #3]

0x45adb0 CMP	X0, X2

0x45adb4 B.EQ	45ae28

  (719) 0x45adb8 ORR	X1, XZR, X0

  (719) 0x45adbc ADD	X0, X0, #64

  (719) 0x45adc0 LDR	X17, [X1], #8

  (719) 0x45adc4 LDR	X30, [X22, X17,LSL #3]

  (719) 0x45adc8 STR	X3, [X20, X30,LSL #3]

  (719) 0x45adcc LDUR	X4, [X0, #456]

  (719) 0x45add0 LDR	X14, [X22, X4,LSL #3]

  (719) 0x45add4 STR	X3, [X20, X14,LSL #3]

  (719) 0x45add8 LDR	X1, [X1, #8]

  (719) 0x45addc LDR	X17, [X22, X1,LSL #3]

  (719) 0x45ade0 STR	X3, [X20, X17,LSL #3]

  (719) 0x45ade4 LDUR	X30, [X0, #472]

  (719) 0x45ade8 LDR	X4, [X22, X30,LSL #3]

  (719) 0x45adec STR	X3, [X20, X4,LSL #3]

  (719) 0x45adf0 LDUR	X14, [X0, #480]

  (719) 0x45adf4 LDR	X1, [X22, X14,LSL #3]

  (719) 0x45adf8 STR	X3, [X20, X1,LSL #3]

  (719) 0x45adfc LDUR	X17, [X0, #488]

  (719) 0x45ae00 LDR	X30, [X22, X17,LSL #3]

  (719) 0x45ae04 STR	X3, [X20, X30,LSL #3]

  (719) 0x45ae08 LDUR	X4, [X0, #496]

  (719) 0x45ae0c LDR	X14, [X22, X4,LSL #3]

  (719) 0x45ae10 STR	X3, [X20, X14,LSL #3]

  (719) 0x45ae14 LDUR	X1, [X0, #504]

  (719) 0x45ae18 LDR	X17, [X22, X1,LSL #3]

  (719) 0x45ae1c STR	X3, [X20, X17,LSL #3]

  (719) 0x45ae20 CMP	X0, X2

  (719) 0x45ae24 B.NE	45adb8

0x45ae28 LDR	X2, [X11, X5]

0x45ae2c MOVI	D3, #0

0x45ae30 ADD	X30, X10, X16

0x45ae34 LDR	X0, [X10, X5]

0x45ae38 LDR	X14, [X10, X16]

0x45ae3c FMOV	D29, D3

0x45ae40 ADD	X0, X0, #1

0x45ae44 CMP	X0, X14

0x45ae48 B.GE	45aed8

0x45ae4c CMP	X7, #1

0x45ae50 B.EQ	45b5ac

0x45ae54 ORR	X17, XZR, X19

0x45ae58 LDR	X19, [SP, #168]

0x45ae5c STP	X6, X7, [SP, #112]

  (718) 0x45ae60 LDR	X4, [X25, X0,LSL #3]

  (718) 0x45ae64 UBFM	X1, X4, #61, #60

  (718) 0x45ae68 LDR	X7, [X26, X1]

  (718) 0x45ae6c CMN	X7, #3

  (718) 0x45ae70 B.EQ	45ae8c

  (718) 0x45ae74 LDR	X6, [X27, X5]

  (718) 0x45ae78 LDR	X7, [X27, X1]

  (718) 0x45ae7c CMP	X6, X7

  (718) 0x45ae80 B.NE	45ae8c

  (718) 0x45ae84 LDR	D21, [X28, X0,LSL #3]

  (718) 0x45ae88 FADD	D3, D3, D21

  (718) 0x45ae8c CMN	X4, #1

  (718) 0x45ae90 B.EQ	45aec4

  (718) 0x45ae94 LDR	X4, [X20, X1]

  (718) 0x45ae98 CMP	X3, X4

  (718) 0x45ae9c B.NE	45aec4

  (718) 0x45aea0 LDR	D20, [X28, X0,LSL #3]

  (718) 0x45aea4 UBFM	X14, X2, #61, #60

  (718) 0x45aea8 ADD	X2, X2, #1

  (718) 0x45aeac LDR	X1, [X19, X1]

  (718) 0x45aeb0 LDR	X6, [SP, #104]

  (718) 0x45aeb4 FADD	D29, D29, D20

  (718) 0x45aeb8 STR	D20, [X9, X14]

  (718) 0x45aebc STR	X1, [X6, X14]

  (718) 0x45aec0 LDR	X14, [X30]

  (718) 0x45aec4 ADD	X0, X0, #1

  (718) 0x45aec8 CMP	X0, X14

  (718) 0x45aecc B.LT	45ae60

0x45aed0 LDP	X6, X7, [SP, #112]

0x45aed4 ORR	X19, XZR, X17

0x45aed8 LDR	X0, [SP, #136]

0x45aedc LDR	X30, [X12, X16]

0x45aee0 LDR	X1, [X12, X5]

0x45aee4 LDR	X0, [X0, X5]

0x45aee8 ADD	X17, X0, X30

0x45aeec SUB	X4, X17, X1

0x45aef0 CMP	X0, X4

0x45aef4 B.GE	45b028

0x45aef8 LDR	X14, [SP, #184]

0x45aefc UBFM	X30, X0, #61, #60

0x45af00 LDR	X17, [X14, #8]

0x45af04 ADD	X4, X17, X4,LSL #3

0x45af08 ADD	X0, X17, X0,LSL #3

0x45af0c SUB	X1, X4, X0

0x45af10 SUB	X14, X1, #8

0x45af14 UBFM	X1, X14, #3, #63

0x45af18 ADD	X14, X1, #1

0x45af1c ANDS	X1, X14, #0x7

0x45af20 B.EQ	45afb4

0x45af24 CMP	X1, #1

0x45af28 B.EQ	45afa0

0x45af2c CMP	X1, #2

0x45af30 B.EQ	45af94

0x45af34 CMP	X1, #3

0x45af38 B.EQ	45af88

0x45af3c CMP	X1, #4

0x45af40 B.EQ	45af7c

0x45af44 CMP	X1, #5

0x45af48 B.EQ	45af70

0x45af4c CMP	X1, #6

0x45af50 B.EQ	45af64

0x45af54 LDR	X30, [X17, X30]

0x45af58 ADD	X0, X0, #8

0x45af5c LDR	X17, [X21, X30,LSL #3]

0x45af60 STR	X3, [X19, X17,LSL #3]

0x45af64 LDR	X14, [X0], #8

0x45af68 LDR	X1, [X21, X14,LSL #3]

0x45af6c STR	X3, [X19, X1,LSL #3]

0x45af70 LDR	X30, [X0], #8

0x45af74 LDR	X17, [X21, X30,LSL #3]

0x45af78 STR	X3, [X19, X17,LSL #3]

0x45af7c LDR	X14, [X0], #8

0x45af80 LDR	X1, [X21, X14,LSL #3]

0x45af84 STR	X3, [X19, X1,LSL #3]

0x45af88 LDR	X30, [X0], #8

0x45af8c LDR	X17, [X21, X30,LSL #3]

0x45af90 STR	X3, [X19, X17,LSL #3]

0x45af94 LDR	X14, [X0], #8

0x45af98 LDR	X1, [X21, X14,LSL #3]

0x45af9c STR	X3, [X19, X1,LSL #3]

0x45afa0 LDR	X30, [X0], #8

0x45afa4 LDR	X17, [X21, X30,LSL #3]

0x45afa8 STR	X3, [X19, X17,LSL #3]

0x45afac CMP	X4, X0

0x45afb0 B.EQ	45b024

  (716) 0x45afb4 ORR	X1, XZR, X0

  (716) 0x45afb8 ADD	X0, X0, #64

  (716) 0x45afbc LDR	X14, [X1], #8

  (716) 0x45afc0 LDR	X30, [X21, X14,LSL #3]

  (716) 0x45afc4 STR	X3, [X19, X30,LSL #3]

  (716) 0x45afc8 LDUR	X17, [X0, #456]

  (716) 0x45afcc LDR	X14, [X21, X17,LSL #3]

  (716) 0x45afd0 STR	X3, [X19, X14,LSL #3]

  (716) 0x45afd4 LDR	X1, [X1, #8]

  (716) 0x45afd8 LDR	X30, [X21, X1,LSL #3]

  (716) 0x45afdc STR	X3, [X19, X30,LSL #3]

  (716) 0x45afe0 LDUR	X17, [X0, #472]

  (716) 0x45afe4 LDR	X14, [X21, X17,LSL #3]

  (716) 0x45afe8 STR	X3, [X19, X14,LSL #3]

  (716) 0x45afec LDUR	X1, [X0, #480]

  (716) 0x45aff0 LDR	X30, [X21, X1,LSL #3]

  (716) 0x45aff4 STR	X3, [X19, X30,LSL #3]

  (716) 0x45aff8 LDUR	X17, [X0, #488]

  (716) 0x45affc LDR	X14, [X21, X17,LSL #3]

  (716) 0x45b000 STR	X3, [X19, X14,LSL #3]

  (716) 0x45b004 LDUR	X1, [X0, #496]

  (716) 0x45b008 LDR	X30, [X21, X1,LSL #3]

  (716) 0x45b00c STR	X3, [X19, X30,LSL #3]

  (716) 0x45b010 LDUR	X17, [X0, #504]

  (716) 0x45b014 LDR	X14, [X21, X17,LSL #3]

  (716) 0x45b018 STR	X3, [X19, X14,LSL #3]

  (716) 0x45b01c CMP	X4, X0

  (716) 0x45b020 B.NE	45afb4

0x45b024 LDR	X1, [X12, X5]

0x45b028 LDR	X4, [SP, #160]

0x45b02c LDR	X0, [X4, X5]

0x45b030 ADD	X17, X4, X16

0x45b034 LDR	X16, [X4, X16]

0x45b038 CMP	X0, X16

0x45b03c B.GE	45b6bc

0x45b040 LDR	X30, [SP, #200]

0x45b044 CBZ	X30, 45b628

0x45b048 ORR	X30, XZR, X21

0x45b04c LDR	X21, [SP, #176]

0x45b050 STP	X9, X2, [SP, #112]

0x45b054 B	45b0ac

  (715) 0x45b058 LDR	X2, [X27, X5]

  (715) 0x45b05c LDR	X9, [X13, X4]

  (715) 0x45b060 CMP	X2, X9

  (715) 0x45b064 B.EQ	45b0cc

  (715) 0x45b068 CMN	X14, #1

  (715) 0x45b06c B.EQ	45b0a0

  (715) 0x45b070 LDR	X14, [X19, X4]

  (715) 0x45b074 CMP	X3, X14

  (715) 0x45b078 B.NE	45b0a0

  (715) 0x45b07c LDR	D5, [X8, X0,LSL #3]

  (715) 0x45b080 UBFM	X16, X1, #61, #60

  (715) 0x45b084 ADD	X1, X1, #1

  (715) 0x45b088 LDR	X4, [X21, X4]

  (715) 0x45b08c LDR	X2, [SP, #96]

  (715) 0x45b090 FADD	D29, D29, D5

  (715) 0x45b094 STR	D5, [X15, X16]

  (715) 0x45b098 STR	X4, [X2, X16]

  (715) 0x45b09c LDR	X16, [X17]

  (715) 0x45b0a0 ADD	X0, X0, #1

  (715) 0x45b0a4 CMP	X0, X16

  (715) 0x45b0a8 B.GE	45b160

  (715) 0x45b0ac LDR	X9, [X24, X0,LSL #3]

  (715) 0x45b0b0 LDR	X14, [X6, X9,LSL #3]

  (715) 0x45b0b4 UBFM	X4, X14, #61, #60

  (715) 0x45b0b8 LDR	X2, [X23, X4]

  (715) 0x45b0bc CMN	X2, #3

  (715) 0x45b0c0 B.EQ	45b068

  (715) 0x45b0c4 CMP	X7, #1

  (715) 0x45b0c8 B.NE	45b058

  (715) 0x45b0cc LDR	D6, [X8, X0,LSL #3]

  (715) 0x45b0d0 FADD	D3, D3, D6

  (715) 0x45b0d4 B	45b068

0x45b160 LDP	X9, X2, [SP, #112]

0x45b164 ORR	X21, XZR, X30

0x45b168 LDR	X17, [X12, X5]

0x45b16c LDR	X3, [X10, X5]

0x45b170 LDR	D4, [X28, X3,LSL #3]

0x45b174 FMUL	D0, D29, D4

0x45b178 FCMP	D0, #0

0x45b17c B.EQ	45b188

0x45b180 FNEG	D1, D3

0x45b184 FDIV	D31, D1, D0

0x45b188 LDR	X4, [X11, X5]

0x45b18c CMP	X4, X2

0x45b190 B.GE	45b384

0x45b194 SUB	X2, X2, X4

0x45b198 SUB	X5, X2, #1

0x45b19c CMP	X5, #2

0x45b1a0 B.LS	45b734

0x45b1a4 UBFM	X30, X2, #2, #63

0x45b1a8 ADD	X0, X9, X4,LSL #3

0x45b1ac DUP	V26.2D, V31.D[0]

0x45b1b0 UBFM	X14, X30, #59, #58

0x45b1b4 UBFM	X16, X4, #61, #60

0x45b1b8 SUB	X3, X14, #32

0x45b1bc ADD	X5, X0, X30,LSL #5

0x45b1c0 UBFM	X30, X3, #5, #63

0x45b1c4 ADD	X14, X30, #1

0x45b1c8 ANDS	X3, X14, #0x7

0x45b1cc B.EQ	45b29c

0x45b1d0 CMP	X3, #1

0x45b1d4 B.EQ	45b280

0x45b1d8 CMP	X3, #2

0x45b1dc B.EQ	45b26c

0x45b1e0 CMP	X3, #3

0x45b1e4 B.EQ	45b258

0x45b1e8 CMP	X3, #4

0x45b1ec B.EQ	45b244

0x45b1f0 CMP	X3, #5

0x45b1f4 B.EQ	45b230

0x45b1f8 CMP	X3, #6

0x45b1fc B.EQ	45b21c

0x45b200 LDR	Q27, [X9, X16]

0x45b204 ADD	X0, X0, #32

0x45b208 LDUR	Q2, [X0, #496]

0x45b20c FMUL	V22.2D, V27.2D, V26.2D

0x45b210 FMUL	V23.2D, V2.2D, V26.2D

0x45b214 STR	Q22, [X9, X16]

0x45b218 STUR	Q23, [X0, #496]

0x45b21c LDP	Q24, Q30, [X0]

0x45b220 ADD	X0, X0, #32

0x45b224 FMUL	V25.2D, V24.2D, V26.2D

0x45b228 FMUL	V19.2D, V30.2D, V26.2D

0x45b22c STP	Q25, Q19, [X0, #2016]

0x45b230 LDP	Q3, Q28, [X0]

0x45b234 ADD	X0, X0, #32

0x45b238 FMUL	V29.2D, V3.2D, V26.2D

0x45b23c FMUL	V21.2D, V28.2D, V26.2D

0x45b240 STP	Q29, Q21, [X0, #2016]

0x45b244 LDP	Q20, Q6, [X0]

0x45b248 ADD	X0, X0, #32

0x45b24c FMUL	V5.2D, V20.2D, V26.2D

0x45b250 FMUL	V16.2D, V6.2D, V26.2D

0x45b254 STP	Q5, Q16, [X0, #2016]

0x45b258 LDP	Q7, Q18, [X0]

0x45b25c ADD	X0, X0, #32

0x45b260 FMUL	V17.2D, V7.2D, V26.2D

0x45b264 FMUL	V4.2D, V18.2D, V26.2D

0x45b268 STP	Q17, Q4, [X0, #2016]

0x45b26c LDP	Q0, Q1, [X0]

0x45b270 ADD	X0, X0, #32

0x45b274 FMUL	V27.2D, V0.2D, V26.2D

0x45b278 FMUL	V22.2D, V1.2D, V26.2D

0x45b27c STP	Q27, Q22, [X0, #2016]

0x45b280 LDP	Q2, Q23, [X0]

0x45b284 ADD	X0, X0, #32

0x45b288 FMUL	V24.2D, V2.2D, V26.2D

0x45b28c FMUL	V30.2D, V23.2D, V26.2D

0x45b290 STP	Q24, Q30, [X0, #2016]

0x45b294 CMP	X5, X0

0x45b298 B.EQ	45b33c

0x45b29c STP	X19, X6, [SP, #112]

  (712) 0x45b2a0 ORR	X19, XZR, X0

  (712) 0x45b2a4 LDP	Q25, Q19, [X0]

  (712) 0x45b2a8 LDP	Q3, Q28, [X0, #32]

  (712) 0x45b2ac LDP	Q29, Q21, [X0, #64]

  (712) 0x45b2b0 LDP	Q17, Q4, [X0, #96]

  (712) 0x45b2b4 LDP	Q30, Q27, [X0, #128]

  (712) 0x45b2b8 FMUL	V20.2D, V25.2D, V26.2D

  (712) 0x45b2bc LDP	Q0, Q1, [X0, #160]

  (712) 0x45b2c0 FMUL	V16.2D, V19.2D, V26.2D

  (712) 0x45b2c4 LDP	Q24, Q25, [X0, #192]

  (712) 0x45b2c8 FMUL	V6.2D, V3.2D, V26.2D

  (712) 0x45b2cc LDP	Q22, Q23, [X0, #224]

  (712) 0x45b2d0 ADD	X0, X0, #256

  (712) 0x45b2d4 FMUL	V7.2D, V28.2D, V26.2D

  (712) 0x45b2d8 FMUL	V18.2D, V29.2D, V26.2D

  (712) 0x45b2dc FMUL	V5.2D, V21.2D, V26.2D

  (712) 0x45b2e0 FMUL	V2.2D, V17.2D, V26.2D

  (712) 0x45b2e4 FMUL	V19.2D, V4.2D, V26.2D

  (712) 0x45b2e8 FMUL	V3.2D, V30.2D, V26.2D

  (712) 0x45b2ec FMUL	V28.2D, V27.2D, V26.2D

  (712) 0x45b2f0 STUR	Q18, [X0, #320]

  (712) 0x45b2f4 FMUL	V29.2D, V0.2D, V26.2D

  (712) 0x45b2f8 STUR	Q5, [X0, #336]

  (712) 0x45b2fc FMUL	V21.2D, V1.2D, V26.2D

  (712) 0x45b300 STP	Q20, Q16, [X0, #1792]

  (712) 0x45b304 FMUL	V20.2D, V24.2D, V26.2D

  (712) 0x45b308 FMUL	V16.2D, V25.2D, V26.2D

  (712) 0x45b30c STP	Q6, Q7, [X0, #1824]

  (712) 0x45b310 FMUL	V6.2D, V22.2D, V26.2D

  (712) 0x45b314 FMUL	V7.2D, V23.2D, V26.2D

  (712) 0x45b318 STP	Q2, Q19, [X0, #1888]

  (712) 0x45b31c STP	Q3, Q28, [X0, #1920]

  (712) 0x45b320 STP	Q29, Q21, [X0, #1952]

  (712) 0x45b324 STP	Q20, Q16, [X0, #1984]

  (712) 0x45b328 STUR	Q6, [X0, #480]

  (712) 0x45b32c STR	Q7, [X19, #240]

  (712) 0x45b330 CMP	X5, X0

  (712) 0x45b334 B.NE	45b2a0

0x45b338 LDP	X19, X6, [SP, #112]

0x45b33c AND	X0, X2, #0x0

0x45b340 ANDS	XZR, X2, #0x3

0x45b344 B.EQ	45b384

0x45b348 ADD	X4, X4, X0

0x45b34c SUB	X16, X2, X0

0x45b350 DUP	Z26.D, Z31.D[0]

0x45b354 WHILELO	P7.D, XZR, X16

0x45b358 ADD	X2, X9, X4,LSL #3

0x45b35c LD1D	{Z18.D}, P7/Z, [X9, X4,LSL #3]

0x45b360 FMUL	Z5.D, Z18.D, Z26.D

0x45b364 ST1D	{Z5.D}, P7, [X2, MUL VL]

0x45b368 CNTD	X5, ALL

0x45b36c WHILELO	P0.D, X5, X16

0x45b370 B.EQ	45b384

0x45b374 LD1D	{Z17.D}, P0/Z, [X2, #1, MUL VL]

0x45b378 INCB	X2, ALL

0x45b37c FMUL	Z4.D, Z17.D, Z26.D

0x45b380 ST1D	{Z4.D}, P0, [X2, MUL VL]

0x45b384 CMP	X1, X17

0x45b388 B.LE	45b574

0x45b38c SUB	X1, X1, X17

0x45b390 SUB	X30, X1, #1

0x45b394 CMP	X30, #2

0x45b398 B.LS	45b73c

0x45b39c UBFM	X4, X1, #2, #63

0x45b3a0 ADD	X0, X15, X17,LSL #3

0x45b3a4 DUP	V28.2D, V31.D[0]

0x45b3a8 UBFM	X3, X4, #59, #58

0x45b3ac UBFM	X16, X17, #61, #60

0x45b3b0 SUB	X5, X3, #32

0x45b3b4 ADD	X2, X0, X4,LSL #5

0x45b3b8 UBFM	X30, X5, #5, #63

0x45b3bc ADD	X14, X30, #1

0x45b3c0 ANDS	X4, X14, #0x7

0x45b3c4 B.EQ	45b494

0x45b3c8 CMP	X4, #1

0x45b3cc B.EQ	45b478

0x45b3d0 CMP	X4, #2

0x45b3d4 B.EQ	45b464

0x45b3d8 CMP	X4, #3

0x45b3dc B.EQ	45b450

0x45b3e0 CMP	X4, #4

0x45b3e4 B.EQ	45b43c

0x45b3e8 CMP	X4, #5

0x45b3ec B.EQ	45b428

0x45b3f0 CMP	X4, #6

0x45b3f4 B.EQ	45b414

0x45b3f8 LDR	Q30, [X15, X16]

0x45b3fc ADD	X0, X0, #32

0x45b400 LDUR	Q0, [X0, #496]

0x45b404 FMUL	V27.2D, V30.2D, V28.2D

0x45b408 FMUL	V1.2D, V0.2D, V28.2D

0x45b40c STR	Q27, [X15, X16]

0x45b410 STUR	Q1, [X0, #496]

0x45b414 LDP	Q24, Q25, [X0]

0x45b418 ADD	X0, X0, #32

0x45b41c FMUL	V22.2D, V24.2D, V28.2D

0x45b420 FMUL	V23.2D, V25.2D, V28.2D

0x45b424 STP	Q22, Q23, [X0, #2016]

0x45b428 LDP	Q2, Q19, [X0]

0x45b42c ADD	X0, X0, #32

0x45b430 FMUL	V3.2D, V2.2D, V28.2D

0x45b434 FMUL	V29.2D, V19.2D, V28.2D

0x45b438 STP	Q3, Q29, [X0, #2016]

0x45b43c LDP	Q21, Q20, [X0]

0x45b440 ADD	X0, X0, #32

0x45b444 FMUL	V16.2D, V21.2D, V28.2D

0x45b448 FMUL	V6.2D, V20.2D, V28.2D

0x45b44c STP	Q16, Q6, [X0, #2016]

0x45b450 LDP	Q7, Q26, [X0]

0x45b454 ADD	X0, X0, #32

0x45b458 FMUL	V18.2D, V7.2D, V28.2D

0x45b45c FMUL	V5.2D, V26.2D, V28.2D

0x45b460 STP	Q18, Q5, [X0, #2016]

0x45b464 LDP	Q17, Q4, [X0]

0x45b468 ADD	X0, X0, #32

0x45b46c FMUL	V30.2D, V17.2D, V28.2D

0x45b470 FMUL	V27.2D, V4.2D, V28.2D

0x45b474 STP	Q30, Q27, [X0, #2016]

0x45b478 LDP	Q1, Q0, [X0]

0x45b47c ADD	X0, X0, #32

0x45b480 FMUL	V24.2D, V1.2D, V28.2D

0x45b484 FMUL	V25.2D, V0.2D, V28.2D

0x45b488 STP	Q24, Q25, [X0, #2016]

0x45b48c CMP	X0, X2

0x45b490 B.EQ	45b52c

  (711) 0x45b494 LDP	Q23, Q2, [X0]

  (711) 0x45b498 ORR	X16, XZR, X0

  (711) 0x45b49c LDP	Q3, Q22, [X0, #32]

  (711) 0x45b4a0 LDP	Q19, Q29, [X0, #64]

  (711) 0x45b4a4 LDP	Q17, Q18, [X0, #96]

  (711) 0x45b4a8 LDP	Q30, Q27, [X0, #128]

  (711) 0x45b4ac FMUL	V16.2D, V23.2D, V28.2D

  (711) 0x45b4b0 LDP	Q5, Q0, [X0, #160]

  (711) 0x45b4b4 FMUL	V6.2D, V2.2D, V28.2D

  (711) 0x45b4b8 LDP	Q24, Q4, [X0, #192]

  (711) 0x45b4bc FMUL	V21.2D, V3.2D, V28.2D

  (711) 0x45b4c0 LDP	Q1, Q25, [X0, #224]

  (711) 0x45b4c4 ADD	X0, X0, #256

  (711) 0x45b4c8 FMUL	V7.2D, V22.2D, V28.2D

  (711) 0x45b4cc FMUL	V26.2D, V19.2D, V28.2D

  (711) 0x45b4d0 FMUL	V20.2D, V29.2D, V28.2D

  (711) 0x45b4d4 FMUL	V23.2D, V17.2D, V28.2D

  (711) 0x45b4d8 FMUL	V22.2D, V18.2D, V28.2D

  (711) 0x45b4dc FMUL	V19.2D, V30.2D, V28.2D

  (711) 0x45b4e0 FMUL	V29.2D, V27.2D, V28.2D

  (711) 0x45b4e4 STUR	Q26, [X0, #320]

  (711) 0x45b4e8 FMUL	V3.2D, V24.2D, V28.2D

  (711) 0x45b4ec STUR	Q20, [X0, #336]

  (711) 0x45b4f0 STP	Q16, Q6, [X0, #1792]

  (711) 0x45b4f4 FMUL	V16.2D, V5.2D, V28.2D

  (711) 0x45b4f8 FMUL	V6.2D, V0.2D, V28.2D

  (711) 0x45b4fc STP	Q21, Q7, [X0, #1824]

  (711) 0x45b500 FMUL	V21.2D, V4.2D, V28.2D

  (711) 0x45b504 FMUL	V7.2D, V1.2D, V28.2D

  (711) 0x45b508 FMUL	V2.2D, V25.2D, V28.2D

  (711) 0x45b50c STP	Q23, Q22, [X0, #1888]

  (711) 0x45b510 STP	Q19, Q29, [X0, #1920]

  (711) 0x45b514 STP	Q16, Q6, [X0, #1952]

  (711) 0x45b518 STP	Q3, Q21, [X0, #1984]

  (711) 0x45b51c STUR	Q7, [X0, #480]

  (711) 0x45b520 STR	Q2, [X16, #240]

  (711) 0x45b524 CMP	X0, X2

  (711) 0x45b528 B.NE	45b494

0x45b52c AND	X14, X1, #0x0

0x45b530 ANDS	XZR, X1, #0x3

0x45b534 B.EQ	45b574

0x45b538 ADD	X17, X14, X17

0x45b53c SUB	X5, X1, X14

0x45b540 DUP	Z28.D, Z31.D[0]

0x45b544 WHILELO	P1.D, XZR, X5

0x45b548 ADD	X1, X15, X17,LSL #3

0x45b54c LD1D	{Z26.D}, P1/Z, [X15, X17,LSL #3]

0x45b550 FMUL	Z20.D, Z28.D, Z26.D

0x45b554 ST1D	{Z20.D}, P1, [X1, MUL VL]

0x45b558 CNTD	X2, ALL

0x45b55c WHILELO	P2.D, X2, X5

0x45b560 B.EQ	45b574

0x45b564 LD1D	{Z17.D}, P2/Z, [X1, #1, MUL VL]

0x45b568 INCB	X1, ALL

0x45b56c FMUL	Z18.D, Z17.D, Z28.D

0x45b570 ST1D	{Z18.D}, P2, [X1, MUL VL]

0x45b574 LDR	X30, [SP, #128]

0x45b578 ADD	X18, X18, #1

0x45b57c CMP	X30, X18

0x45b580 B.NE	45accc

0x45b5ac LDR	X17, [SP, #168]

0x45b5b0 STR	X5, [SP, #112]

0x45b5b4 HINT	#0

0x45b5b8 HINT	#0

0x45b5bc HINT	#0

  (717) 0x45b5c0 LDR	X1, [X25, X0,LSL #3]

  (717) 0x45b5c4 UBFM	X4, X1, #61, #60

  (717) 0x45b5c8 LDR	X5, [X26, X4]

  (717) 0x45b5cc CMN	X5, #3

  (717) 0x45b5d0 B.EQ	45b5dc

  (717) 0x45b5d4 LDR	D19, [X28, X0,LSL #3]

  (717) 0x45b5d8 FADD	D3, D3, D19

  (717) 0x45b5dc CMN	X1, #1

  (717) 0x45b5e0 B.EQ	45b614

  (717) 0x45b5e4 LDR	X1, [X20, X4]

  (717) 0x45b5e8 CMP	X3, X1

  (717) 0x45b5ec B.NE	45b614

  (717) 0x45b5f0 LDR	D28, [X28, X0,LSL #3]

  (717) 0x45b5f4 UBFM	X14, X2, #61, #60

  (717) 0x45b5f8 ADD	X2, X2, #1

  (717) 0x45b5fc LDR	X4, [X17, X4]

  (717) 0x45b600 LDR	X5, [SP, #104]

  (717) 0x45b604 FADD	D29, D29, D28

  (717) 0x45b608 STR	D28, [X9, X14]

  (717) 0x45b60c STR	X4, [X5, X14]

  (717) 0x45b610 LDR	X14, [X30]

  (717) 0x45b614 ADD	X0, X0, #1

  (717) 0x45b618 CMP	X0, X14

  (717) 0x45b61c B.LT	45b5c0

0x45b620 LDR	X5, [SP, #112]

0x45b624 B	45aed8

0x45b628 CMP	X7, #1

0x45b62c B.EQ	45b6c4

0x45b630 LDR	X30, [SP, #176]

0x45b634 ORR	X14, XZR, X6

0x45b638 STP	X7, X2, [SP, #112]

0x45b63c HINT	#0

  (714) 0x45b640 LDR	X6, [X24, X0,LSL #3]

  (714) 0x45b644 UBFM	X4, X6, #61, #60

  (714) 0x45b648 LDR	X7, [X23, X4]

  (714) 0x45b64c CMN	X7, #3

  (714) 0x45b650 B.EQ	45b66c

  (714) 0x45b654 LDR	X2, [X13, X4]

  (714) 0x45b658 LDR	X7, [X27, X5]

  (714) 0x45b65c CMP	X2, X7

  (714) 0x45b660 B.NE	45b66c

  (714) 0x45b664 LDR	D18, [X8, X0,LSL #3]

  (714) 0x45b668 FADD	D3, D3, D18

  (714) 0x45b66c CMN	X6, #1

  (714) 0x45b670 B.EQ	45b6a4

  (714) 0x45b674 LDR	X6, [X19, X4]

  (714) 0x45b678 CMP	X3, X6

  (714) 0x45b67c B.NE	45b6a4

  (714) 0x45b680 LDR	D17, [X8, X0,LSL #3]

  (714) 0x45b684 UBFM	X16, X1, #61, #60

  (714) 0x45b688 ADD	X1, X1, #1

  (714) 0x45b68c LDR	X4, [X30, X4]

  (714) 0x45b690 LDR	X2, [SP, #96]

  (714) 0x45b694 FADD	D29, D29, D17

  (714) 0x45b698 STR	D17, [X15, X16]

  (714) 0x45b69c STR	X4, [X2, X16]

  (714) 0x45b6a0 LDR	X16, [X17]

  (714) 0x45b6a4 ADD	X0, X0, #1

  (714) 0x45b6a8 CMP	X16, X0

  (714) 0x45b6ac B.GT	45b640

0x45b6b0 LDP	X7, X2, [SP, #112]

0x45b6b4 ORR	X6, XZR, X14

0x45b6b8 B	45b168

0x45b6bc ORR	X17, XZR, X1

0x45b6c0 B	45b16c

0x45b6c4 LDR	X30, [SP, #176]

0x45b6c8 STR	X2, [SP, #112]

  (713) 0x45b6cc LDR	X4, [X24, X0,LSL #3]

  (713) 0x45b6d0 UBFM	X14, X4, #61, #60

  (713) 0x45b6d4 LDR	X2, [X23, X14]

  (713) 0x45b6d8 CMN	X2, #3

  (713) 0x45b6dc B.EQ	45b6e8

  (713) 0x45b6e0 LDR	D16, [X8, X0,LSL #3]

  (713) 0x45b6e4 FADD	D3, D3, D16

  (713) 0x45b6e8 CMN	X4, #1

  (713) 0x45b6ec B.EQ	45b720

  (713) 0x45b6f0 LDR	X4, [X19, X14]

  (713) 0x45b6f4 CMP	X3, X4

  (713) 0x45b6f8 B.NE	45b720

  (713) 0x45b6fc LDR	D7, [X8, X0,LSL #3]

  (713) 0x45b700 UBFM	X16, X1, #61, #60

  (713) 0x45b704 ADD	X1, X1, #1

  (713) 0x45b708 LDR	X14, [X30, X14]

  (713) 0x45b70c LDR	X2, [SP, #96]

  (713) 0x45b710 FADD	D29, D29, D7

  (713) 0x45b714 STR	D7, [X15, X16]

  (713) 0x45b718 STR	X14, [X2, X16]

  (713) 0x45b71c LDR	X16, [X17]

  (713) 0x45b720 ADD	X0, X0, #1

  (713) 0x45b724 CMP	X16, X0

  (713) 0x45b728 B.GT	45b6cc

0x45b72c LDR	X2, [SP, #112]

0x45b730 B	45b168

0x45b734 MOVZ	X0, #0

0x45b738 B	45b348

0x45b73c MOVZ	X14, #0

0x45b740 B	45b538

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1593 - 1660

--------------------------------------------------------------------------------

1593:            {   tmp_marker_offd[i] = -1; }

[...]

1605:            for (i=thread_start; i < thread_stop; i++)

1606:            {

1607:              i1 = pass_array[i];

1608:              sum_C = 0;

1609:              sum_N = 0;

1610:              j_start = P_diag_start[i1];

1611:              j_end = j_start+P_diag_i[i1+1]-P_diag_i[i1];

1612:              for (j=j_start; j < j_end; j++)

1613:              {

1614:                 k1 = P_diag_pass[1][j];

1615:                 tmp_marker[C_array[k1]] = i1;

1616:              }

1617:              cnt = P_diag_i[i1];

1618:              for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++)

1619:              {

1620:                 j1 = A_diag_j[j];

1621:                 if (CF_marker[j1] != -3 &&

1622:                    (num_functions == 1 || dof_func[i1] == dof_func[j1]))

1623:                    sum_N += A_diag_data[j];

1624:                 if (j1 != -1 && tmp_marker[j1] == i1)

1625:                 {

1626:                    P_diag_data[cnt] = A_diag_data[j];

1627:                    P_diag_j[cnt++] = fine_to_coarse[j1];

1628:                    sum_C += A_diag_data[j];

1629:                 }

1630:              }

1631:              j_start = P_offd_start[i1];

1632:              j_end = j_start+P_offd_i[i1+1]-P_offd_i[i1];

1633:              for (j=j_start; j < j_end; j++)

1634:              {

1635:                 k1 = P_offd_pass[1][j];

1636:                 tmp_marker_offd[C_array_offd[k1]] = i1;

1637:              }

1638:              cnt_offd = P_offd_i[i1];

1639:              for (j=A_offd_i[i1]; j < A_offd_i[i1+1]; j++)

1640:              {

1641:                 if (col_offd_S_to_A)

1642:                     j1 = map_A_to_S[A_offd_j[j]];

1643:                 else

1644:                     j1 = A_offd_j[j];

1645:                 if (CF_marker_offd[j1] != -3 &&

1646:                   (num_functions == 1 || dof_func[i1] == dof_func_offd[j1]))

1647:                     sum_N += A_offd_data[j];

1648:                 if (j1 != -1 && tmp_marker_offd[j1] == i1)

1649:                 {

1650:                    P_offd_data[cnt_offd] = A_offd_data[j];

1651:                    P_offd_j[cnt_offd++] = map_S_to_new[j1];

1652:                    sum_C += A_offd_data[j];

1653:                 }

1654:              }

1655:              diagonal = A_diag_data[A_diag_i[i1]];

1656:              if (sum_C*diagonal) alfa = -sum_N/(sum_C*diagonal);

1657:              for (j=P_diag_i[i1]; j < cnt; j++)

1658:                 P_diag_data[j] *= alfa;

1659:              for (j=P_offd_i[i1]; j < cnt_offd; j++)

1660:                 P_offd_data[j] *= alfa;

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1667	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►51.59+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1667	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec
►48.41+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

Coverage (%)	Name	Source Location	Module
►71.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►28.57+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1667	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►87.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►12.57+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1667	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►93.97+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►6.03+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1667	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►96.83+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.17+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1667	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►97.06+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.94+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1667	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►98.69+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.31+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1667	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►97.98+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.02+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1667	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►98.01+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.99+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildMultipass	par_multi_interp.c:1667	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:737	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Module
►99.52+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.09
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	1.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source	par_multi_interp.c:1593-1593,par_multi_interp.c:1605-1618,par_multi_interp.c:1631-1639,par_multi_interp.c:1655-1660
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	44.25
CQA cycles if no scalar integer	14.33
CQA cycles if FP arith vectorized	42.33
CQA cycles if fully vectorized	35.91
Front-end cycles	44.25
P0 cycles	28.00
P1 cycles	28.00
P2 cycles	35.50
P3 cycles	35.50
P4 cycles	35.50
P5 cycles	35.50
P6 cycles	15.50
P7 cycles	15.50
P8 cycles	15.50
P9 cycles	15.50
P10 cycles	42.00
P11 cycles	42.00
P12 cycles	42.00
P13 cycles	10.00
P14 cycles	10.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	358.00
Nb uops	354.00
Nb loads	NA
Nb stores	40.00
Nb stack references	25.00
FLOP/cycle	1.67
Nb FLOP add-sub	0.00
Nb FLOP mul	73.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.79
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	52.78
Vectorization ratio load	95.24
Vectorization ratio store	50.00
Vectorization ratio mul	96.97
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	8.16
Vector-efficiency ratio all	52.08
Vector-efficiency ratio load	86.90
Vector-efficiency ratio store	60.00
Vector-efficiency ratio mul	55.30
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	29.08

Metric	Value
CQA speedup if no scalar integer	3.09
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	1.23
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source	par_multi_interp.c:1593-1593,par_multi_interp.c:1605-1618,par_multi_interp.c:1631-1639,par_multi_interp.c:1655-1660
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	44.25
CQA cycles if no scalar integer	14.33
CQA cycles if FP arith vectorized	42.33
CQA cycles if fully vectorized	35.91
Front-end cycles	44.25
P0 cycles	28.00
P1 cycles	28.00
P2 cycles	35.50
P3 cycles	35.50
P4 cycles	35.50
P5 cycles	35.50
P6 cycles	15.50
P7 cycles	15.50
P8 cycles	15.50
P9 cycles	15.50
P10 cycles	42.00
P11 cycles	42.00
P12 cycles	42.00
P13 cycles	10.00
P14 cycles	10.00
DIV/SQRT cycles	1.75 - 3.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	358.00
Nb uops	354.00
Nb loads	NA
Nb stores	40.00
Nb stack references	25.00
FLOP/cycle	1.67
Nb FLOP add-sub	0.00
Nb FLOP mul	73.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.79
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	52.78
Vectorization ratio load	95.24
Vectorization ratio store	50.00
Vectorization ratio mul	96.97
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	8.16
Vector-efficiency ratio all	52.08
Vector-efficiency ratio load	86.90
Vector-efficiency ratio store	60.00
Vector-efficiency ratio mul	55.30
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	29.08

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source file and lines	par_multi_interp.c:1593-1660
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593,1605-1660.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c:1593,1605-1618,1631-1639,1655-1660.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 44.25 to 14.33 cycles (3.09x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 52% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 44.25 to 35.91 cycles (1.23x speedup).

Details

52% of VPU instructions are used in vector version (process two or more data elements in vector registers):

95% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
96% of VPU multiply instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
8% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 74 FP arithmetical operations:

73: multiply
1: divide

The binary loop is loading 128 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	358
nb uops	354
loop length	1432
used w registers	0
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	6
used q registers	23
used v registers	24
used z registers	8
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	44.25 cycles
front end	44.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	28.00	28.00	35.50	35.50	35.50	35.50	15.50	15.50	15.50	15.50	42.00	42.00	42.00	10.00	10.00
cycles	28.00	28.00	35.50	35.50	35.50	35.50	15.50	15.50	15.50	15.50	42.00	42.00	42.00	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	44.25
Dispatch	42.00
DIV/SQRT	1.75-3.50
Overall L1	44.25

Vectorization ratios

INT

all	41%
load	95%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	86%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	96%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	52%
load	95%
store	50%
mul	96%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	52%
load	86%
store	60%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	29%

all	52%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	55%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	52%
load	86%
store	60%
mul	55%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.25 cycles. At this rate:

3% of peak load performance is reached (2.89 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (2.89 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 44.25 to 42.00 cycles (1.05x speedup).

ASM code

In the binary file, the address of the loop is: 45accc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X16, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X30, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X14, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45ae2c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X17, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X30, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X30, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X4, X1, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X1, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45adb8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ada4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ad98 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ad8c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ad80 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ad74 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ad68 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X30, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X22, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X22, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ae28 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X11, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D3, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X30, X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X10, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X10, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D29, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45aed8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b5ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xa08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X17, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X19, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X6, X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X6, X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X19, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X12, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X0, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45b028 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X30, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X17, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X17, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X1, X14, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X1, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45afb4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45afa0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45af94 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45af88 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45af7c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45af70 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45af64 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X17, X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b024 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X4, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X4, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X4, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45b6bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X30, 45b628 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X30, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X9, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45b0ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X21, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X10, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D0, D29, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 45b188 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FNEG D1, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDIV D31, D1, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR X4, [X11, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45b384 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X2, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 45b734 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X30, X2, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X9, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V26.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X14, X30, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X14, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X0, X30,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X30, X3, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X3, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45b29c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b280 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b26c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b258 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b244 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b230 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x68c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b21c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q27, [X9, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR Q2, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL V22.2D, V27.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V23.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q22, [X9, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q23, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP Q24, Q30, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V25.2D, V24.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V19.2D, V30.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q25, Q19, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q3, Q28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V29.2D, V3.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V21.2D, V28.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q29, Q21, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q20, Q6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V5.2D, V20.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V16.2D, V6.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q5, Q16, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q7, Q18, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V17.2D, V7.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V4.2D, V18.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q17, Q4, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q0, Q1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V27.2D, V0.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V22.2D, V1.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q27, Q22, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q2, Q23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V24.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V30.2D, V23.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q24, Q30, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b33c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
AND X0, X2, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS XZR, X2, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b384 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z26.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P7.D, XZR, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X2, X9, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z18.D}, P7/Z, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z5.D, Z18.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z5.D}, P7, [X2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P0.D, X5, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.EQ 45b384 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z17.D}, P0/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
INCB X2, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMUL Z4.D, Z17.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z4.D}, P0, [X2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b574 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X1, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X30, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 45b73c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X4, X1, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X15, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V28.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X3, X4, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X3, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X0, X4,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X30, X5, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X4, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45b494 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b478 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b464 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b450 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b43c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x898>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b428 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x884>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b414 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X15, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR Q0, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL V27.2D, V30.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V1.2D, V0.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q27, [X15, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q1, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP Q24, Q25, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V22.2D, V24.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V23.2D, V25.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q22, Q23, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q2, Q19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V3.2D, V2.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V29.2D, V19.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q3, Q29, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q21, Q20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V16.2D, V21.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V20.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q16, Q6, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q7, Q26, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V18.2D, V7.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V5.2D, V26.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q18, Q5, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q17, Q4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V30.2D, V17.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V27.2D, V4.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q30, Q27, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q1, Q0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V24.2D, V1.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V25.2D, V0.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q24, Q25, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b52c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X14, X1, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS XZR, X1, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b574 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X14, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z28.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P1.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X1, X15, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z20.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z20.D}, P1, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X2, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P2.D, X2, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.EQ 45b574 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z17.D}, P2/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
INCB X1, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMUL Z18.D, Z17.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z18.D}, P2, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45accc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45aed8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45b6c4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X14, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																			N/A
LDP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X6, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 45b168 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X17, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b16c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45b168 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b348 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b538 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildMultipass._omp_fn.9
Source file and lines	par_multi_interp.c:1593-1660
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

52% of VPU instructions are used in vector version (process two or more data elements in vector registers):

95% of VPU loads are used in vector version.
50% of VPU stores are used in vector version.
96% of VPU multiply instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
8% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 74 FP arithmetical operations:

73: multiply
1: divide

The binary loop is loading 128 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	358
nb uops	354
loop length	1432
used w registers	0
used x registers	24
used b registers	0
used h registers	0
used s registers	1
used d registers	6
used q registers	23
used v registers	24
used z registers	8
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	44.25 cycles
front end	44.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	28.00	28.00	35.50	35.50	35.50	35.50	15.50	15.50	15.50	15.50	42.00	42.00	42.00	10.00	10.00
cycles	28.00	28.00	35.50	35.50	35.50	35.50	15.50	15.50	15.50	15.50	42.00	42.00	42.00	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.75-3.50

Cycles summary

Front-end	44.25
Dispatch	42.00
DIV/SQRT	1.75-3.50
Overall L1	44.25

Vectorization ratios

INT

all	41%
load	95%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	86%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	96%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	52%
load	95%
store	50%
mul	96%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	52%
load	86%
store	60%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	29%

all	52%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	55%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	52%
load	86%
store	60%
mul	55%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	29%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 44.25 cycles. At this rate:

3% of peak load performance is reached (2.89 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (2.89 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 45accc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X16, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X16, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X30, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X11, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X14, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45ae2c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X17, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X30, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X30, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X4, X1, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X1, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45adb8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x214>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ada4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ad98 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ad8c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ad80 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ad74 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ad68 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x1c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [X30, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X30, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X22, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X1, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X22, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X17, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X22, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X22, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X20, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ae28 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x284>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X11, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVI D3, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X30, X10, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [X10, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X10, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D29, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45aed8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b5ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xa08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X17, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X19, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X6, X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X6, X7, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X19, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X30, [X12, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X0, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X0, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45b028 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X30, X0, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X17, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X17, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X1, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X14, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X1, X14, #3, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X1, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45afb4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x410>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45afa0 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45af94 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45af88 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45af7c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45af70 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X1, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45af64 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x3c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [X17, X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X14, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X21, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X30, [X0], #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X21, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [X19, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b024 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X4, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X17, X4, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X4, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45b6bc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X30, 45b628 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xa84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X30, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X9, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 45b0ac <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X21, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X17, [X12, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X10, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X28, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D0, D29, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMP D0, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 45b188 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FNEG D1, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FDIV D31, D1, D0	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR X4, [X11, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X4, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 45b384 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X2, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 45b734 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb90>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X30, X2, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X9, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V26.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X14, X30, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X3, X14, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X0, X30,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X30, X3, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X3, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45b29c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b280 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6dc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b26c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b258 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b244 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x6a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b230 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x68c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X3, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b21c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x678>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q27, [X9, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR Q2, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL V22.2D, V27.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V23.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q22, [X9, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q23, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP Q24, Q30, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V25.2D, V24.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V19.2D, V30.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q25, Q19, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q3, Q28, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V29.2D, V3.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V21.2D, V28.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q29, Q21, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q20, Q6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V5.2D, V20.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V16.2D, V6.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q5, Q16, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q7, Q18, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V17.2D, V7.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V4.2D, V18.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q17, Q4, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q0, Q1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V27.2D, V0.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V22.2D, V1.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q27, Q22, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q2, Q23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V24.2D, V2.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V30.2D, V23.2D, V26.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q24, Q30, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X5, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b33c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X19, X6, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
AND X0, X2, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS XZR, X2, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b384 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z26.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P7.D, XZR, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X2, X9, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z18.D}, P7/Z, [X9, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z5.D, Z18.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z5.D}, P7, [X2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P0.D, X5, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.EQ 45b384 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z17.D}, P0/Z, [X2, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
INCB X2, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMUL Z4.D, Z17.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z4.D}, P0, [X2, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45b574 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X1, X1, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X30, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LS 45b73c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X4, X1, #2, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X15, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V28.2D, V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
UBFM X3, X4, #59, #58	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UBFM X16, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X3, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X2, X0, X4,LSL #5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
UBFM X30, X5, #5, #63	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X4, X14, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45b494 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b478 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b464 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b450 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x8ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b43c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x898>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b428 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x884>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X4, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b414 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q30, [X15, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDUR Q0, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMUL V27.2D, V30.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V1.2D, V0.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STR Q27, [X15, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STUR Q1, [X0, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
LDP Q24, Q25, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V22.2D, V24.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V23.2D, V25.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q22, Q23, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q2, Q19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V3.2D, V2.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V29.2D, V19.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q3, Q29, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q21, Q20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V16.2D, V21.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V6.2D, V20.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q16, Q6, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q7, Q26, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V18.2D, V7.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V5.2D, V26.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q18, Q5, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q17, Q4, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V30.2D, V17.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V27.2D, V4.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q30, Q27, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP Q1, Q0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ADD X0, X0, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V24.2D, V1.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
FMUL V25.2D, V0.2D, V28.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	vect (50.0%)
STP Q24, Q25, [X0, #2016]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b52c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x988>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X14, X1, #0x0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS XZR, X1, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b574 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X17, X14, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z28.D, Z31.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P1.D, XZR, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
ADD X1, X15, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z26.D}, P1/Z, [X15, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
FMUL Z20.D, Z28.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z20.D}, P1, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CNTD X2, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
WHILELO P2.D, X2, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B.EQ 45b574 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x9d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LD1D {Z17.D}, P2/Z, [X1, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
INCB X1, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
FMUL Z18.D, Z17.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z18.D}, P2, [X1, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X30, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X30, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 45accc <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X17, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR X5, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45aed8 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 45b6c4 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0xb20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X14, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																			N/A
LDP X7, X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X6, XZR, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B 45b168 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X17, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b16c <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X30, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 45b168 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x5c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b348 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x7a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 45b538 <hypre_BoomerAMGBuildMultipass._omp_fn.9+0x994>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	1.79	0	3.27	0	5.68	0	8.99	0	13.63	0	14.05	0	18.27	0	24.68	0	28.68	0	31.3	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.73000001907349	0.21092209219933
1x2	2	1.79	1.79	2	0.40499997138977	0.21742044389248
1x4	4	3.27	3.27	4	0.22999998927116	0.21809056401253
1x8	8	5.68	5.68	8	0.13000001013279	0.20794366300106
1x16	16	8.99	8.99	16	0.089999996125698	0.15449103713036
1x24	24	13.63	13.63	24	0.060000002384186	0.10725617408752
1x32	32	14.05	14.05	32	0.069999992847443	0.11118619889021
1x40	40	18.27	18.27	40	0.054999999701977	0.090477995574474
1x48	48	24.68	24.68	48	0.03999999910593	0.066763736307621
1x56	55	28.68	28.68	56	0.035000000149012	0.058383520692587
1x64	63	31.3	31.3	64	0.030000001192093	0.052511386573315

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency