OV - exec - Loop 808

	Loop Id: 808	Module: exec	Source: par_lr_interp.c:1609-1707 [...]	Coverage: 0.18%

0x461ad8 UBFM	X3, X10, #61, #60

0x461adc LDR	D28, [X18, X1,LSL #3]

0x461ae0 LDR	D26, [X4, X3]

0x461ae4 FADD	D17, D26, D28

0x461ae8 STR	D17, [X4, X3]

0x461aec ADD	X1, X1, #1

0x461af0 CMP	X1, X12

0x461af4 B.EQ	461b50

0x461af8 LDR	X5, [X7, X1,LSL #3]

0x461afc UBFM	X2, X5, #61, #60

0x461b00 LDR	X10, [X19, X2]

0x461b04 CMP	X0, X10

0x461b08 B.LE	461ad8

0x461b0c CMP	X10, X30

0x461b10 B.EQ	4620b0

0x461b14 LDR	X9, [X20, X2]

0x461b18 CMN	X9, #3

0x461b1c B.EQ	461aec

0x461b20 LDR	X11, [SP, #168]

0x461b24 CMP	X11, #1

0x461b28 B.EQ	461b3c

0x461b2c LDR	X16, [X8, X2]

0x461b30 LDR	X25, [X8, X21,LSL #3]

0x461b34 CMP	X25, X16

0x461b38 B.NE	461aec

0x461b3c LDR	D26, [X18, X1,LSL #3]

0x461b40 ADD	X1, X1, #1

0x461b44 FADD	D29, D29, D26

0x461b48 CMP	X1, X12

0x461b4c B.NE	461af8

0x4620b0 LDR	X14, [SP, #216]

0x4620b4 ADD	X13, X2, #8

0x4620b8 STR	X13, [SP, #320]

0x4620bc LDR	X3, [X14, X2]

0x4620c0 LDR	X14, [X14, X13]

0x4620c4 UBFM	X5, X3, #61, #60

0x4620c8 ADD	X10, X3, #1

0x4620cc LDR	D27, [X18, X5]

0x4620d0 FCMPE	D27, #0

0x4620d4 FCSEL	D28, D0, D1, #4

0x4620d8 CMP	X10, X14

0x4620dc B.GE	463bb4

0x4620e0 SUB	X25, X14, X3

0x4620e4 CNTD	X11, ALL

0x4620e8 SUB	X13, X25, #2

0x4620ec ADD	X3, X11, #2

0x4620f0 SUB	X16, X25, #1

0x4620f4 CMP	X13, X3

0x4620f8 B.CC	463be8

0x4620fc ADD	X9, X5, #8

0x462100 ADDPL	X13, X25, #63

0x462104 DUP	Z2.D, X21

0x462108 ADD	X5, X18, X5

0x46210c MOVZ	X3, #0

0x462110 DUP	Z3.D, X0

0x462114 SUB	X13, X13, #1

0x462118 ADD	X9, X7, X9

0x46211c DUP	Z5.D, Z28.D[0]

0x462120 ADD	X5, X5, #8

0x462124 CNTB	X25, ALL

0x462128 DUP	Z31.D, #0

0x46212c PTRUE	P4.B, ALL

  (814) 0x462130 LD1D	{Z30.D}, P4/Z, [X9, X3,LSL #3]

  (814) 0x462134 ADD	X3, X3, X11

  (814) 0x462138 LD1D	{Z6.D}, P4/Z, [X19, Z30.D,LSL #3]

  (814) 0x46213c CMPEQ	P5.D, P4/Z, Z30.D, Z2.D

  (814) 0x462140 CMPGE	P15.D, P4/Z, Z6.D, Z3.D

  (814) 0x462144 ORR	P6.B, P4/Z, P5.B, P15.B

  (814) 0x462148 LD1D	{Z7.D}, P6/Z, [X5, MUL VL]

  (814) 0x46214c ADD	X5, X5, X25

  (814) 0x462150 FMUL	Z16.D, Z7.D, Z5.D

  (814) 0x462154 FCMLT	P7.D, P6/Z, Z16.D, #0.0000000

  (814) 0x462158 FADD	Z31.D, P7/M, Z31.D, Z7.D

  (814) 0x46215c CMP	X13, X3

  (814) 0x462160 B.CS	462130

0x462164 FADDV	D17, P4, Z31.D

0x462168 ADD	X9, X3, X10

0x46216c FADD	D31, D14, D17

0x462170 CMP	X16, X3

0x462174 B.EQ	462310

0x462178 LDR	X16, [X7, X9,LSL #3]

0x46217c ORN	X11, XZR, X9

0x462180 ADD	X13, X11, X14

0x462184 AND	X25, X13, #0x3

0x462188 LDR	X3, [X19, X16,LSL #3]

0x46218c CMP	X0, X3

0x462190 CCMP	X21, X16, #4, #12

0x462194 B.NE	4621ac

0x462198 LDR	D18, [X18, X9,LSL #3]

0x46219c FMUL	D19, D28, D18

0x4621a0 FADD	D20, D31, D18

0x4621a4 FCMPE	D19, #0

0x4621a8 FCSEL	D31, D20, D31, #4

0x4621ac ADD	X3, X9, #1

0x4621b0 CMP	X14, X3

0x4621b4 B.LE	462310

0x4621b8 CBZ	X25, 462258

0x4621bc CMP	X25, #1

0x4621c0 B.EQ	462224

0x4621c4 CMP	X25, #2

0x4621c8 B.EQ	4621f8

0x4621cc LDR	X5, [X7, X3,LSL #3]

0x4621d0 LDR	X9, [X19, X5,LSL #3]

0x4621d4 CMP	X0, X9

0x4621d8 CCMP	X21, X5, #4, #12

0x4621dc B.NE	4621f4

0x4621e0 LDR	D21, [X18, X3,LSL #3]

0x4621e4 FMUL	D22, D28, D21

0x4621e8 FADD	D13, D31, D21

0x4621ec FCMPE	D22, #0

0x4621f0 FCSEL	D31, D13, D31, #4

0x4621f4 ADD	X3, X3, #1

0x4621f8 LDR	X16, [X7, X3,LSL #3]

0x4621fc LDR	X11, [X19, X16,LSL #3]

0x462200 CMP	X0, X11

0x462204 CCMP	X21, X16, #4, #12

0x462208 B.NE	462220

0x46220c LDR	D4, [X18, X3,LSL #3]

0x462210 FMUL	D23, D28, D4

0x462214 FADD	D24, D31, D4

0x462218 FCMPE	D23, #0

0x46221c FCSEL	D31, D24, D31, #4

0x462220 ADD	X3, X3, #1

0x462224 LDR	X13, [X7, X3,LSL #3]

0x462228 LDR	X25, [X19, X13,LSL #3]

0x46222c CMP	X0, X25

0x462230 CCMP	X21, X13, #4, #12

0x462234 B.NE	46224c

0x462238 LDR	D25, [X18, X3,LSL #3]

0x46223c FMUL	D26, D28, D25

0x462240 FADD	D27, D31, D25

0x462244 FCMPE	D26, #0

0x462248 FCSEL	D31, D27, D31, #4

0x46224c ADD	X3, X3, #1

0x462250 CMP	X14, X3

0x462254 B.LE	462310

  (813) 0x462258 LDR	X5, [X7, X3,LSL #3]

  (813) 0x46225c LDR	X9, [X19, X5,LSL #3]

  (813) 0x462260 CMP	X0, X9

  (813) 0x462264 CCMP	X21, X5, #4, #12

  (813) 0x462268 B.NE	462280

  (813) 0x46226c LDR	D2, [X18, X3,LSL #3]

  (813) 0x462270 FMUL	D3, D28, D2

  (813) 0x462274 FADD	D5, D31, D2

  (813) 0x462278 FCMPE	D3, #0

  (813) 0x46227c FCSEL	D31, D5, D31, #4

  (813) 0x462280 ADD	X3, X3, #1

  (813) 0x462284 LDR	X16, [X7, X3,LSL #3]

  (813) 0x462288 LDR	X11, [X19, X16,LSL #3]

  (813) 0x46228c CMP	X0, X11

  (813) 0x462290 CCMP	X21, X16, #4, #12

  (813) 0x462294 B.NE	4622ac

  (813) 0x462298 LDR	D30, [X18, X3,LSL #3]

  (813) 0x46229c FMUL	D6, D28, D30

  (813) 0x4622a0 FADD	D7, D31, D30

  (813) 0x4622a4 FCMPE	D6, #0

  (813) 0x4622a8 FCSEL	D31, D7, D31, #4

  (813) 0x4622ac ADD	X25, X3, #1

  (813) 0x4622b0 ADD	X9, X3, #2

  (813) 0x4622b4 LDR	X5, [X7, X25,LSL #3]

  (813) 0x4622b8 ADD	X3, X3, #3

  (813) 0x4622bc LDR	X13, [X19, X5,LSL #3]

  (813) 0x4622c0 CMP	X0, X13

  (813) 0x4622c4 CCMP	X21, X5, #4, #12

  (813) 0x4622c8 B.NE	4622e0

  (813) 0x4622cc LDR	D16, [X18, X25,LSL #3]

  (813) 0x4622d0 FMUL	D17, D28, D16

  (813) 0x4622d4 FADD	D18, D31, D16

  (813) 0x4622d8 FCMPE	D17, #0

  (813) 0x4622dc FCSEL	D31, D18, D31, #4

  (813) 0x4622e0 LDR	X16, [X7, X9,LSL #3]

  (813) 0x4622e4 LDR	X11, [X19, X16,LSL #3]

  (813) 0x4622e8 CMP	X0, X11

  (813) 0x4622ec CCMP	X21, X16, #4, #12

  (813) 0x4622f0 B.NE	462308

  (813) 0x4622f4 LDR	D19, [X18, X9,LSL #3]

  (813) 0x4622f8 FMUL	D20, D28, D19

  (813) 0x4622fc FADD	D21, D31, D19

  (813) 0x462300 FCMPE	D20, #0

  (813) 0x462304 FCSEL	D31, D21, D31, #4

  (813) 0x462308 CMP	X14, X3

  (813) 0x46230c B.GT	462258

0x462310 LDR	X25, [SP, #144]

0x462314 LDR	D13, [X18, X1,LSL #3]

0x462318 CMP	X25, #1

0x46231c B.GT	462c90

0x462320 FCMP	D31, #0

0x462324 B.NE	4633bc

0x462328 FADD	D29, D29, D13

0x46232c B	461aec

0x462c8c FMOV	D31, D14

0x462c90 LDR	X9, [SP, #320]

0x462c94 LDR	X5, [SP, #336]

0x462c98 LDR	X3, [X5, X9]

0x462c9c LDR	X25, [X5, X2]

0x462ca0 STR	X3, [SP, #312]

0x462ca4 CMP	X25, X3

0x462ca8 B.GE	464008

0x462cac SUB	X13, X3, X25

0x462cb0 CNTD	X9, ALL

0x462cb4 SUB	X16, X13, #1

0x462cb8 ADD	X11, X9, #2

0x462cbc STR	X13, [SP, #328]

0x462cc0 CMP	X16, X11

0x462cc4 B.CC	464048

0x462cc8 LDR	X5, [SP, #280]

0x462ccc ADD	X16, X17, X25,LSL #3

0x462cd0 MOVZ	X3, #0

0x462cd4 SUB	X13, X13, X9

0x462cd8 CNTB	X11, ALL

0x462cdc DUP	Z22.D, X6

0x462ce0 DUP	Z4.D, Z28.D[0]

0x462ce4 DUP	Z23.D, #0

0x462ce8 PTRUE	P0.B, ALL

0x462cec ADD	X5, X5, X25,LSL #3

  (812) 0x462cf0 LD1D	{Z24.D}, P0/Z, [X16, X3,LSL #3]

  (812) 0x462cf4 ADD	X3, X3, X9

  (812) 0x462cf8 LD1D	{Z25.D}, P0/Z, [X24, Z24.D,LSL #3]

  (812) 0x462cfc CMPGE	P1.D, P0/Z, Z25.D, Z22.D

  (812) 0x462d00 LD1D	{Z26.D}, P1/Z, [X5, MUL VL]

  (812) 0x462d04 ADD	X5, X5, X11

  (812) 0x462d08 FMUL	Z27.D, Z26.D, Z4.D

  (812) 0x462d0c FCMLT	P2.D, P1/Z, Z27.D, #0.0000000

  (812) 0x462d10 FADD	Z23.D, P2/M, Z23.D, Z26.D

  (812) 0x462d14 CMP	X13, X3

  (812) 0x462d18 B.CS	462cf0

0x462d1c LDR	X9, [SP, #328]

0x462d20 FADDV	D2, P0, Z23.D

0x462d24 ADD	X5, X3, X25

0x462d28 FADD	D31, D31, D2

0x462d2c CMP	X9, X3

0x462d30 B.EQ	46300c

0x462d34 LDR	X16, [X17, X5,LSL #3]

0x462d38 ORN	X13, XZR, X5

0x462d3c LDR	X11, [SP, #312]

0x462d40 LDR	X3, [X24, X16,LSL #3]

0x462d44 ADD	X9, X13, X11

0x462d48 AND	X16, X9, #0x7

0x462d4c CMP	X6, X3

0x462d50 B.GT	462d6c

0x462d54 LDR	X13, [SP, #280]

0x462d58 LDR	D3, [X13, X5,LSL #3]

0x462d5c FMUL	D5, D3, D28

0x462d60 FADD	D30, D31, D3

0x462d64 FCMPE	D5, #0

0x462d68 FCSEL	D31, D30, D31, #4

0x462d6c LDR	X11, [SP, #312]

0x462d70 ADD	X3, X5, #1

0x462d74 CMP	X3, X11

0x462d78 B.GE	46300c

0x462d7c CBZ	X16, 462ec0

0x462d80 CMP	X16, #1

0x462d84 B.EQ	462e88

0x462d88 CMP	X16, #2

0x462d8c B.EQ	462e5c

0x462d90 CMP	X16, #3

0x462d94 B.EQ	462e30

0x462d98 CMP	X16, #4

0x462d9c B.EQ	462e1c

0x462da0 CMP	X16, #5

0x462da4 B.EQ	462e08

0x462da8 CMP	X16, #6

0x462dac B.EQ	462ddc

0x462db0 LDR	X5, [X17, X3,LSL #3]

0x462db4 LDR	X11, [X24, X5,LSL #3]

0x462db8 CMP	X6, X11

0x462dbc B.GT	462dd8

0x462dc0 LDR	X9, [SP, #280]

0x462dc4 LDR	D6, [X9, X3,LSL #3]

0x462dc8 FMUL	D7, D6, D28

0x462dcc FADD	D16, D31, D6

0x462dd0 FCMPE	D7, #0

0x462dd4 FCSEL	D31, D16, D31, #4

0x462dd8 ADD	X3, X3, #1

0x462ddc LDR	X16, [X17, X3,LSL #3]

0x462de0 LDR	X13, [X24, X16,LSL #3]

0x462de4 CMP	X6, X13

0x462de8 B.GT	462e04

0x462dec LDR	X5, [SP, #280]

0x462df0 LDR	D17, [X5, X3,LSL #3]

0x462df4 FMUL	D18, D17, D28

0x462df8 FADD	D19, D31, D17

0x462dfc FCMPE	D18, #0

0x462e00 FCSEL	D31, D19, D31, #4

0x462e04 ADD	X3, X3, #1

0x462e08 LDR	X11, [X17, X3,LSL #3]

0x462e0c LDR	X9, [X24, X11,LSL #3]

0x462e10 CMP	X6, X9

0x462e14 B.LE	463e5c

0x462e18 ADD	X3, X3, #1

0x462e1c LDR	X13, [X17, X3,LSL #3]

0x462e20 LDR	X5, [X24, X13,LSL #3]

0x462e24 CMP	X6, X5

0x462e28 B.LE	463de0

0x462e2c ADD	X3, X3, #1

0x462e30 LDR	X9, [X17, X3,LSL #3]

0x462e34 LDR	X16, [X24, X9,LSL #3]

0x462e38 CMP	X6, X16

0x462e3c B.GT	462e58

0x462e40 LDR	X13, [SP, #280]

0x462e44 LDR	D25, [X13, X3,LSL #3]

0x462e48 FMUL	D26, D25, D28

0x462e4c FADD	D27, D31, D25

0x462e50 FCMPE	D26, #0

0x462e54 FCSEL	D31, D27, D31, #4

0x462e58 ADD	X3, X3, #1

0x462e5c LDR	X5, [X17, X3,LSL #3]

0x462e60 LDR	X11, [X24, X5,LSL #3]

0x462e64 CMP	X6, X11

0x462e68 B.GT	462e84

0x462e6c LDR	X9, [SP, #280]

0x462e70 LDR	D2, [X9, X3,LSL #3]

0x462e74 FMUL	D3, D2, D28

0x462e78 FADD	D5, D31, D2

0x462e7c FCMPE	D3, #0

0x462e80 FCSEL	D31, D5, D31, #4

0x462e84 ADD	X3, X3, #1

0x462e88 LDR	X16, [X17, X3,LSL #3]

0x462e8c LDR	X13, [X24, X16,LSL #3]

0x462e90 CMP	X6, X13

0x462e94 B.GT	462eb0

0x462e98 LDR	X5, [SP, #280]

0x462e9c LDR	D30, [X5, X3,LSL #3]

0x462ea0 FMUL	D6, D30, D28

0x462ea4 FADD	D7, D31, D30

0x462ea8 FCMPE	D6, #0

0x462eac FCSEL	D31, D7, D31, #4

0x462eb0 LDR	X11, [SP, #312]

0x462eb4 ADD	X3, X3, #1

0x462eb8 CMP	X3, X11

0x462ebc B.GE	46300c

0x462ec0 LDR	X16, [SP, #280]

  (811) 0x462ec4 LDR	X9, [X17, X3,LSL #3]

  (811) 0x462ec8 LDR	X13, [X24, X9,LSL #3]

  (811) 0x462ecc CMP	X6, X13

  (811) 0x462ed0 B.GT	462ee8

  (811) 0x462ed4 LDR	D16, [X16, X3,LSL #3]

  (811) 0x462ed8 FMUL	D17, D16, D28

  (811) 0x462edc FADD	D18, D31, D16

  (811) 0x462ee0 FCMPE	D17, #0

  (811) 0x462ee4 FCSEL	D31, D18, D31, #4

  (811) 0x462ee8 ADD	X3, X3, #1

  (811) 0x462eec LDR	X5, [X17, X3,LSL #3]

  (811) 0x462ef0 LDR	X9, [X24, X5,LSL #3]

  (811) 0x462ef4 CMP	X6, X9

  (811) 0x462ef8 B.GT	462f10

  (811) 0x462efc LDR	D19, [X16, X3,LSL #3]

  (811) 0x462f00 FMUL	D20, D19, D28

  (811) 0x462f04 FADD	D21, D31, D19

  (811) 0x462f08 FCMPE	D20, #0

  (811) 0x462f0c FCSEL	D31, D21, D31, #4

  (811) 0x462f10 ADD	X5, X3, #1

  (811) 0x462f14 LDR	X13, [X17, X5,LSL #3]

  (811) 0x462f18 LDR	X9, [X24, X13,LSL #3]

  (811) 0x462f1c CMP	X6, X9

  (811) 0x462f20 B.GT	462f38

  (811) 0x462f24 LDR	D22, [X16, X5,LSL #3]

  (811) 0x462f28 FMUL	D4, D22, D28

  (811) 0x462f2c FADD	D23, D31, D22

  (811) 0x462f30 FCMPE	D4, #0

  (811) 0x462f34 FCSEL	D31, D23, D31, #4

  (811) 0x462f38 ADD	X5, X3, #2

  (811) 0x462f3c LDR	X13, [X17, X5,LSL #3]

  (811) 0x462f40 LDR	X9, [X24, X13,LSL #3]

  (811) 0x462f44 CMP	X6, X9

  (811) 0x462f48 B.GT	462f60

  (811) 0x462f4c LDR	D24, [X16, X5,LSL #3]

  (811) 0x462f50 FMUL	D25, D24, D28

  (811) 0x462f54 FADD	D26, D31, D24

  (811) 0x462f58 FCMPE	D25, #0

  (811) 0x462f5c FCSEL	D31, D26, D31, #4

  (811) 0x462f60 ADD	X5, X3, #3

  (811) 0x462f64 LDR	X13, [X17, X5,LSL #3]

  (811) 0x462f68 LDR	X9, [X24, X13,LSL #3]

  (811) 0x462f6c CMP	X6, X9

  (811) 0x462f70 B.GT	462f88

  (811) 0x462f74 LDR	D2, [X16, X5,LSL #3]

  (811) 0x462f78 FMUL	D27, D2, D28

  (811) 0x462f7c FADD	D3, D31, D2

  (811) 0x462f80 FCMPE	D27, #0

  (811) 0x462f84 FCSEL	D31, D3, D31, #4

  (811) 0x462f88 ADD	X5, X3, #4

  (811) 0x462f8c LDR	X13, [X17, X5,LSL #3]

  (811) 0x462f90 LDR	X9, [X24, X13,LSL #3]

  (811) 0x462f94 CMP	X6, X9

  (811) 0x462f98 B.GT	462fb0

  (811) 0x462f9c LDR	D5, [X16, X5,LSL #3]

  (811) 0x462fa0 FMUL	D6, D5, D28

  (811) 0x462fa4 FADD	D30, D31, D5

  (811) 0x462fa8 FCMPE	D6, #0

  (811) 0x462fac FCSEL	D31, D30, D31, #4

  (811) 0x462fb0 ADD	X5, X3, #5

  (811) 0x462fb4 LDR	X13, [X17, X5,LSL #3]

  (811) 0x462fb8 LDR	X9, [X24, X13,LSL #3]

  (811) 0x462fbc CMP	X6, X9

  (811) 0x462fc0 B.GT	462fd8

  (811) 0x462fc4 LDR	D7, [X16, X5,LSL #3]

  (811) 0x462fc8 FMUL	D16, D7, D28

  (811) 0x462fcc FADD	D17, D31, D7

  (811) 0x462fd0 FCMPE	D16, #0

  (811) 0x462fd4 FCSEL	D31, D17, D31, #4

  (811) 0x462fd8 ADD	X5, X3, #6

  (811) 0x462fdc LDR	X13, [X17, X5,LSL #3]

  (811) 0x462fe0 LDR	X9, [X24, X13,LSL #3]

  (811) 0x462fe4 CMP	X6, X9

  (811) 0x462fe8 B.GT	463000

  (811) 0x462fec LDR	D18, [X16, X5,LSL #3]

  (811) 0x462ff0 FMUL	D19, D18, D28

  (811) 0x462ff4 FADD	D20, D31, D18

  (811) 0x462ff8 FCMPE	D19, #0

  (811) 0x462ffc FCSEL	D31, D20, D31, #4

  (811) 0x463000 ADD	X3, X3, #7

  (811) 0x463004 CMP	X3, X11

  (811) 0x463008 B.LT	462ec4

0x46300c FCMP	D31, #0

0x463010 B.EQ	462328

0x463014 FDIV	D26, D13, D31

0x463018 CMP	X10, X14

0x46301c B.LT	4633c0

0x463020 LDR	X5, [SP, #312]

0x463024 B	4634b8

0x4633bc FDIV	D26, D13, D31

0x4633c0 LDR	X25, [X7, X10,LSL #3]

0x4633c4 ORN	X11, XZR, X10

0x4633c8 ADD	X16, X11, X14

0x4633cc AND	X5, X16, #0x3

0x4633d0 LDR	X13, [X19, X25,LSL #3]

0x4633d4 CMP	X0, X13

0x4633d8 B.GT	463b24

0x4633dc LDR	D31, [X18, X10,LSL #3]

0x4633e0 FMUL	D13, D31, D28

0x4633e4 FCMPE	D13, #0

0x4633e8 B.MI	463b14

0x4633ec ADD	X3, X10, #1

0x4633f0 CMP	X14, X3

0x4633f4 B.LE	463498

0x4633f8 CBZ	X5, 463860

0x4633fc CMP	X5, #1

0x463400 B.EQ	46346c

0x463404 CMP	X5, #2

0x463408 B.EQ	463430

0x46340c LDR	X10, [X7, X3,LSL #3]

0x463410 LDR	X25, [X19, X10,LSL #3]

0x463414 CMP	X0, X25

0x463418 B.GT	463f60

0x46341c LDR	D25, [X18, X3,LSL #3]

0x463420 FMUL	D2, D25, D28

0x463424 FCMPE	D2, #0

0x463428 B.MI	463f50

0x46342c ADD	X3, X3, #1

0x463430 LDR	X16, [X7, X3,LSL #3]

0x463434 LDR	X5, [X19, X16,LSL #3]

0x463438 CMP	X0, X5

0x46343c B.GT	463460

0x463440 LDR	D7, [X18, X3,LSL #3]

0x463444 FMUL	D16, D7, D28

0x463448 FCMPE	D16, #0

0x46344c B.GE	463468

0x463450 UBFM	X13, X5, #61, #60

0x463454 LDR	D17, [X4, X13]

0x463458 FMADD	D18, D26, D7, D17

0x46345c STR	D18, [X4, X13]

0x463460 CMP	X21, X16

0x463464 B.EQ	463f30

0x463468 ADD	X3, X3, #1

0x46346c LDR	X10, [X7, X3,LSL #3]

0x463470 LDR	X9, [X19, X10,LSL #3]

0x463474 CMP	X0, X9

0x463478 B.GT	463b94

0x46347c LDR	D13, [X18, X3,LSL #3]

0x463480 FMUL	D21, D13, D28

0x463484 FCMPE	D21, #0

0x463488 B.MI	463b84

0x46348c ADD	X3, X3, #1

0x463490 CMP	X14, X3

0x463494 B.GT	463860

0x463498 LDR	X14, [SP, #144]

0x46349c CMP	X14, #1

0x4634a0 B.LE	461aec

0x4634a4 LDR	X16, [SP, #320]

0x4634a8 LDR	X11, [SP, #336]

0x4634ac LDR	X5, [X11, X16]

0x4634b0 LDR	X25, [X11, X2]

0x4634b4 STR	X5, [SP, #312]

0x4634b8 CMP	X25, X5

0x4634bc B.GE	461aec

0x4634c0 LDR	X9, [SP, #192]

0x4634c4 SUB	X13, X5, X25

0x4634c8 ANDS	X10, X13, #0x7

0x4634cc LDR	X3, [X9, #200]

0x4634d0 B.EQ	464084

0x4634d4 CMP	X10, #1

0x4634d8 B.EQ	463604

0x4634dc CMP	X10, #2

0x4634e0 B.EQ	4635cc

0x4634e4 CMP	X10, #3

0x4634e8 B.EQ	4635a4

0x4634ec CMP	X10, #4

0x4634f0 B.EQ	46357c

0x4634f4 CMP	X10, #5

0x4634f8 B.EQ	463554

0x4634fc CMP	X10, #6

0x463500 B.EQ	46352c

0x463504 LDR	X14, [X17, X25,LSL #3]

0x463508 LDR	X11, [X24, X14,LSL #3]

0x46350c CMP	X6, X11

0x463510 B.GT	463528

0x463514 LDR	X2, [SP, #280]

0x463518 LDR	D17, [X2, X25,LSL #3]

0x46351c FMUL	D18, D17, D28

0x463520 FCMPE	D18, #0

0x463524 B.MI	463ff4

0x463528 ADD	X25, X25, #1

0x46352c LDR	X5, [X17, X25,LSL #3]

0x463530 LDR	X13, [X24, X5,LSL #3]

0x463534 CMP	X6, X13

0x463538 B.GT	463550

0x46353c LDR	X10, [SP, #280]

0x463540 LDR	D13, [X10, X25,LSL #3]

0x463544 FMUL	D31, D13, D28

0x463548 FCMPE	D31, #0

0x46354c B.MI	463fd4

0x463550 ADD	X25, X25, #1

0x463554 LDR	X14, [X17, X25,LSL #3]

0x463558 LDR	X11, [X24, X14,LSL #3]

0x46355c CMP	X6, X11

0x463560 B.GT	463578

0x463564 LDR	X2, [SP, #280]

0x463568 LDR	D4, [X2, X25,LSL #3]

0x46356c FMUL	D23, D4, D28

0x463570 FCMPE	D23, #0

0x463574 B.MI	463fc0

0x463578 ADD	X25, X25, #1

0x46357c LDR	X5, [X17, X25,LSL #3]

0x463580 LDR	X13, [X24, X5,LSL #3]

0x463584 CMP	X6, X13

0x463588 B.GT	4635a0

0x46358c LDR	X10, [SP, #280]

0x463590 LDR	D2, [X10, X25,LSL #3]

0x463594 FMUL	D27, D2, D28

0x463598 FCMPE	D27, #0

0x46359c B.MI	463fac

0x4635a0 ADD	X25, X25, #1

0x4635a4 LDR	X14, [X17, X25,LSL #3]

0x4635a8 LDR	X11, [X24, X14,LSL #3]

0x4635ac CMP	X6, X11

0x4635b0 B.GT	4635c8

0x4635b4 LDR	X2, [SP, #280]

0x4635b8 LDR	D6, [X2, X25,LSL #3]

0x4635bc FMUL	D7, D6, D28

0x4635c0 FCMPE	D7, #0

0x4635c4 B.MI	463f94

0x4635c8 ADD	X25, X25, #1

0x4635cc LDR	X5, [X17, X25,LSL #3]

0x4635d0 LDR	X13, [X24, X5,LSL #3]

0x4635d4 CMP	X6, X13

0x4635d8 B.GT	463600

0x4635dc LDR	X10, [SP, #280]

0x4635e0 LDR	D17, [X10, X25,LSL #3]

0x4635e4 FMUL	D18, D17, D28

0x4635e8 FCMPE	D18, #0

0x4635ec B.GE	463600

0x4635f0 UBFM	X9, X13, #61, #60

0x4635f4 LDR	D19, [X3, X9]

0x4635f8 FMADD	D20, D26, D17, D19

0x4635fc STR	D20, [X3, X9]

0x463600 ADD	X25, X25, #1

0x463604 LDR	X14, [X17, X25,LSL #3]

0x463608 LDR	X11, [X24, X14,LSL #3]

0x46360c CMP	X6, X11

0x463610 B.LE	463e94

0x463614 LDR	X5, [SP, #312]

0x463618 ADD	X25, X25, #1

0x46361c CMP	X25, X5

0x463620 B.EQ	461aec

0x463624 LDR	X10, [SP, #280]

0x463628 ORR	X13, XZR, X5

  (809) 0x46362c LDR	X9, [X17, X25,LSL #3]

  (809) 0x463630 LDR	X14, [X24, X9,LSL #3]

  (809) 0x463634 CMP	X6, X14

  (809) 0x463638 B.GT	46365c

  (809) 0x46363c LDR	D4, [X10, X25,LSL #3]

  (809) 0x463640 FMUL	D23, D4, D28

  (809) 0x463644 FCMPE	D23, #0

  (809) 0x463648 B.GE	46365c

  (809) 0x46364c UBFM	X11, X14, #61, #60

  (809) 0x463650 LDR	D24, [X3, X11]

  (809) 0x463654 FMADD	D25, D26, D4, D24

  (809) 0x463658 STR	D25, [X3, X11]

  (809) 0x46365c ADD	X25, X25, #1

  (809) 0x463660 LDR	X2, [X17, X25,LSL #3]

  (809) 0x463664 LDR	X16, [X24, X2,LSL #3]

  (809) 0x463668 CMP	X6, X16

  (809) 0x46366c B.GT	463690

  (809) 0x463670 LDR	D2, [X10, X25,LSL #3]

  (809) 0x463674 FMUL	D27, D2, D28

  (809) 0x463678 FCMPE	D27, #0

  (809) 0x46367c B.GE	463690

  (809) 0x463680 UBFM	X5, X16, #61, #60

  (809) 0x463684 LDR	D3, [X3, X5]

  (809) 0x463688 FMADD	D5, D26, D2, D3

  (809) 0x46368c STR	D5, [X3, X5]

  (809) 0x463690 ADD	X14, X25, #1

  (809) 0x463694 LDR	X9, [X17, X14,LSL #3]

  (809) 0x463698 LDR	X11, [X24, X9,LSL #3]

  (809) 0x46369c CMP	X6, X11

  (809) 0x4636a0 B.GT	4636c4

  (809) 0x4636a4 LDR	D6, [X10, X14,LSL #3]

  (809) 0x4636a8 FMUL	D7, D6, D28

  (809) 0x4636ac FCMPE	D7, #0

  (809) 0x4636b0 B.GE	4636c4

  (809) 0x4636b4 UBFM	X2, X11, #61, #60

  (809) 0x4636b8 LDR	D30, [X3, X2]

  (809) 0x4636bc FMADD	D16, D26, D6, D30

  (809) 0x4636c0 STR	D16, [X3, X2]

  (809) 0x4636c4 ADD	X16, X25, #2

  (809) 0x4636c8 LDR	X5, [X17, X16,LSL #3]

  (809) 0x4636cc LDR	X14, [X24, X5,LSL #3]

  (809) 0x4636d0 CMP	X6, X14

  (809) 0x4636d4 B.GT	4636f8

  (809) 0x4636d8 LDR	D17, [X10, X16,LSL #3]

  (809) 0x4636dc FMUL	D18, D17, D28

  (809) 0x4636e0 FCMPE	D18, #0

  (809) 0x4636e4 B.GE	4636f8

  (809) 0x4636e8 UBFM	X9, X14, #61, #60

  (809) 0x4636ec LDR	D19, [X3, X9]

  (809) 0x4636f0 FMADD	D20, D26, D17, D19

  (809) 0x4636f4 STR	D20, [X3, X9]

  (809) 0x4636f8 ADD	X11, X25, #3

  (809) 0x4636fc LDR	X2, [X17, X11,LSL #3]

  (809) 0x463700 LDR	X16, [X24, X2,LSL #3]

  (809) 0x463704 CMP	X6, X16

  (809) 0x463708 B.GT	46372c

  (809) 0x46370c LDR	D13, [X10, X11,LSL #3]

  (809) 0x463710 FMUL	D31, D13, D28

  (809) 0x463714 FCMPE	D31, #0

  (809) 0x463718 B.GE	46372c

  (809) 0x46371c UBFM	X5, X16, #61, #60

  (809) 0x463720 LDR	D21, [X3, X5]

  (809) 0x463724 FMADD	D22, D26, D13, D21

  (809) 0x463728 STR	D22, [X3, X5]

  (809) 0x46372c ADD	X14, X25, #4

  (809) 0x463730 LDR	X9, [X17, X14,LSL #3]

  (809) 0x463734 LDR	X11, [X24, X9,LSL #3]

  (809) 0x463738 CMP	X6, X11

  (809) 0x46373c B.GT	463760

  (809) 0x463740 LDR	D4, [X10, X14,LSL #3]

  (809) 0x463744 FMUL	D23, D4, D28

  (809) 0x463748 FCMPE	D23, #0

  (809) 0x46374c B.GE	463760

  (809) 0x463750 UBFM	X2, X11, #61, #60

  (809) 0x463754 LDR	D24, [X3, X2]

  (809) 0x463758 FMADD	D25, D26, D4, D24

  (809) 0x46375c STR	D25, [X3, X2]

  (809) 0x463760 ADD	X16, X25, #5

  (809) 0x463764 LDR	X5, [X17, X16,LSL #3]

  (809) 0x463768 LDR	X14, [X24, X5,LSL #3]

  (809) 0x46376c CMP	X6, X14

  (809) 0x463770 B.GT	463794

  (809) 0x463774 LDR	D2, [X10, X16,LSL #3]

  (809) 0x463778 FMUL	D27, D2, D28

  (809) 0x46377c FCMPE	D27, #0

  (809) 0x463780 B.GE	463794

  (809) 0x463784 UBFM	X9, X14, #61, #60

  (809) 0x463788 LDR	D3, [X3, X9]

  (809) 0x46378c FMADD	D5, D26, D2, D3

  (809) 0x463790 STR	D5, [X3, X9]

  (809) 0x463794 ADD	X11, X25, #6

  (809) 0x463798 LDR	X2, [X17, X11,LSL #3]

  (809) 0x46379c LDR	X16, [X24, X2,LSL #3]

  (809) 0x4637a0 CMP	X6, X16

  (809) 0x4637a4 B.GT	4637c8

  (809) 0x4637a8 LDR	D6, [X10, X11,LSL #3]

  (809) 0x4637ac FMUL	D7, D6, D28

  (809) 0x4637b0 FCMPE	D7, #0

  (809) 0x4637b4 B.GE	4637c8

  (809) 0x4637b8 UBFM	X5, X16, #61, #60

  (809) 0x4637bc LDR	D30, [X3, X5]

  (809) 0x4637c0 FMADD	D16, D26, D6, D30

  (809) 0x4637c4 STR	D16, [X3, X5]

  (809) 0x4637c8 ADD	X25, X25, #7

  (809) 0x4637cc CMP	X25, X13

  (809) 0x4637d0 B.NE	46362c

0x4637d4 B	461aec

  (810) 0x4637d8 LDR	D2, [X18, X3,LSL #3]

  (810) 0x4637dc FMUL	D27, D2, D28

  (810) 0x4637e0 FCMPE	D27, #0

  (810) 0x4637e4 B.MI	463bd4

  (810) 0x4637e8 ADD	X3, X3, #1

  (810) 0x4637ec LDR	X13, [X7, X3,LSL #3]

  (810) 0x4637f0 LDR	X10, [X19, X13,LSL #3]

  (810) 0x4637f4 CMP	X0, X10

  (810) 0x4637f8 B.GT	463af4

  (810) 0x4637fc LDR	D16, [X18, X3,LSL #3]

  (810) 0x463800 FMUL	D17, D16, D28

  (810) 0x463804 FCMPE	D17, #0

  (810) 0x463808 B.MI	463ae4

  (810) 0x46380c ADD	X25, X3, #1

  (810) 0x463810 LDR	X11, [X7, X25,LSL #3]

  (810) 0x463814 LDR	X16, [X19, X11,LSL #3]

  (810) 0x463818 CMP	X0, X16

  (810) 0x46381c B.GT	463ac4

  (810) 0x463820 LDR	D21, [X18, X25,LSL #3]

  (810) 0x463824 FMUL	D22, D21, D28

  (810) 0x463828 FCMPE	D22, #0

  (810) 0x46382c B.MI	463ab4

  (810) 0x463830 ADD	X13, X3, #2

  (810) 0x463834 LDR	X10, [X7, X13,LSL #3]

  (810) 0x463838 LDR	X9, [X19, X10,LSL #3]

  (810) 0x46383c CMP	X0, X9

  (810) 0x463840 B.GT	463a94

  (810) 0x463844 LDR	D27, [X18, X13,LSL #3]

  (810) 0x463848 FMUL	D3, D27, D28

  (810) 0x46384c FCMPE	D3, #0

  (810) 0x463850 B.MI	463a84

  (810) 0x463854 ADD	X3, X3, #3

  (810) 0x463858 CMP	X14, X3

  (810) 0x46385c B.LE	463498

  (810) 0x463860 LDR	X11, [X7, X3,LSL #3]

  (810) 0x463864 LDR	X16, [X19, X11,LSL #3]

  (810) 0x463868 CMP	X0, X16

  (810) 0x46386c B.LE	4637d8

  (810) 0x463870 CMP	X21, X11

  (810) 0x463874 B.NE	4637e8

  (810) 0x463878 LDR	D6, [X18, X3,LSL #3]

  (810) 0x46387c FMUL	D30, D6, D28

  (810) 0x463880 FMADD	D7, D26, D6, D29

  (810) 0x463884 FCMPE	D30, #0

  (810) 0x463888 FCSEL	D29, D7, D29, #4

  (810) 0x46388c B	4637e8

  (810) 0x463a84 UBFM	X25, X9, #61, #60

  (810) 0x463a88 LDR	D5, [X4, X25]

  (810) 0x463a8c FMADD	D6, D26, D27, D5

  (810) 0x463a90 STR	D6, [X4, X25]

  (810) 0x463a94 CMP	X21, X10

  (810) 0x463a98 B.NE	463854

  (810) 0x463a9c LDR	D7, [X18, X13,LSL #3]

  (810) 0x463aa0 FMUL	D30, D7, D28

  (810) 0x463aa4 FMADD	D16, D26, D7, D29

  (810) 0x463aa8 FCMPE	D30, #0

  (810) 0x463aac FCSEL	D29, D16, D29, #4

  (810) 0x463ab0 B	463854

  (810) 0x463ab4 UBFM	X5, X16, #61, #60

  (810) 0x463ab8 LDR	D4, [X4, X5]

  (810) 0x463abc FMADD	D23, D26, D21, D4

  (810) 0x463ac0 STR	D23, [X4, X5]

  (810) 0x463ac4 CMP	X21, X11

  (810) 0x463ac8 B.NE	463830

  (810) 0x463acc LDR	D24, [X18, X25,LSL #3]

  (810) 0x463ad0 FMUL	D25, D24, D28

  (810) 0x463ad4 FMADD	D2, D26, D24, D29

  (810) 0x463ad8 FCMPE	D25, #0

  (810) 0x463adc FCSEL	D29, D2, D29, #4

  (810) 0x463ae0 B	463830

  (810) 0x463ae4 UBFM	X9, X10, #61, #60

  (810) 0x463ae8 LDR	D18, [X4, X9]

  (810) 0x463aec FMADD	D19, D26, D16, D18

  (810) 0x463af0 STR	D19, [X4, X9]

  (810) 0x463af4 CMP	X21, X13

  (810) 0x463af8 B.NE	46380c

  (810) 0x463afc LDR	D20, [X18, X3,LSL #3]

  (810) 0x463b00 FMUL	D13, D20, D28

  (810) 0x463b04 FMADD	D31, D26, D20, D29

  (810) 0x463b08 FCMPE	D13, #0

  (810) 0x463b0c FCSEL	D29, D31, D29, #4

  (810) 0x463b10 B	46380c

0x463b14 UBFM	X9, X13, #61, #60

0x463b18 LDR	D21, [X4, X9]

0x463b1c FMADD	D22, D26, D31, D21

0x463b20 STR	D22, [X4, X9]

0x463b24 CMP	X21, X25

0x463b28 B.NE	4633ec

0x463b2c LDR	D4, [X18, X10,LSL #3]

0x463b30 FMUL	D23, D4, D28

0x463b34 FMADD	D24, D26, D4, D29

0x463b38 FCMPE	D23, #0

0x463b3c FCSEL	D29, D24, D29, #4

0x463b40 B	4633ec

0x463b84 UBFM	X25, X9, #61, #60

0x463b88 LDR	D22, [X4, X25]

0x463b8c FMADD	D4, D26, D13, D22

0x463b90 STR	D4, [X4, X25]

0x463b94 CMP	X21, X10

0x463b98 B.NE	46348c

0x463b9c LDR	D23, [X18, X3,LSL #3]

0x463ba0 FMUL	D24, D23, D28

0x463ba4 FMADD	D25, D26, D23, D29

0x463ba8 FCMPE	D24, #0

0x463bac FCSEL	D29, D25, D29, #4

0x463bb0 B	46348c

0x463bb4 LDR	X9, [SP, #144]

0x463bb8 LDR	D13, [X18, X1,LSL #3]

0x463bbc CMP	X9, #1

0x463bc0 B.GT	462c8c

0x463bc4 FCMP	D14, #0

0x463bc8 B.NE	461aec

0x463bcc FADD	D29, D29, D13

0x463bd0 B	461aec

  (810) 0x463bd4 UBFM	X5, X16, #61, #60

  (810) 0x463bd8 LDR	D3, [X4, X5]

  (810) 0x463bdc FMADD	D5, D26, D2, D3

  (810) 0x463be0 STR	D5, [X4, X5]

  (810) 0x463be4 B	463870

0x463be8 FMOV	D31, D14

0x463bec ORR	X9, XZR, X10

0x463bf0 B	462178

0x463de0 LDR	X11, [SP, #280]

0x463de4 LDR	D4, [X11, X3,LSL #3]

0x463de8 FMUL	D23, D4, D28

0x463dec FADD	D24, D31, D4

0x463df0 FCMPE	D23, #0

0x463df4 FCSEL	D31, D24, D31, #4

0x463df8 B	462e2c

0x463e5c LDR	X16, [SP, #280]

0x463e60 LDR	D20, [X16, X3,LSL #3]

0x463e64 FMUL	D21, D20, D28

0x463e68 FADD	D22, D31, D20

0x463e6c FCMPE	D21, #0

0x463e70 FCSEL	D31, D22, D31, #4

0x463e74 B	462e18

0x463e94 LDR	X2, [SP, #280]

0x463e98 LDR	D13, [X2, X25,LSL #3]

0x463e9c FMUL	D31, D13, D28

0x463ea0 FCMPE	D31, #0

0x463ea4 B.GE	463614

0x463ea8 UBFM	X16, X11, #61, #60

0x463eac LDR	D21, [X3, X16]

0x463eb0 FMADD	D22, D26, D13, D21

0x463eb4 STR	D22, [X3, X16]

0x463eb8 B	463614

0x463f30 LDR	D19, [X18, X3,LSL #3]

0x463f34 FMUL	D20, D19, D28

0x463f38 FMADD	D31, D26, D19, D29

0x463f3c FCMPE	D20, #0

0x463f40 FCSEL	D29, D31, D29, #4

0x463f44 B	463468

0x463f50 UBFM	X11, X25, #61, #60

0x463f54 LDR	D27, [X4, X11]

0x463f58 FMADD	D3, D26, D25, D27

0x463f5c STR	D3, [X4, X11]

0x463f60 CMP	X21, X10

0x463f64 B.NE	46342c

0x463f68 LDR	D5, [X18, X3,LSL #3]

0x463f6c ADD	X3, X3, #1

0x463f70 FMUL	D6, D5, D28

0x463f74 FMADD	D30, D26, D5, D29

0x463f78 FCMPE	D6, #0

0x463f7c FCSEL	D29, D30, D29, #4

0x463f80 B	463430

0x463f94 UBFM	X16, X11, #61, #60

0x463f98 ADD	X25, X25, #1

0x463f9c LDR	D30, [X3, X16]

0x463fa0 FMADD	D16, D26, D6, D30

0x463fa4 STR	D16, [X3, X16]

0x463fa8 B	4635cc

0x463fac UBFM	X9, X13, #61, #60

0x463fb0 LDR	D3, [X3, X9]

0x463fb4 FMADD	D5, D26, D2, D3

0x463fb8 STR	D5, [X3, X9]

0x463fbc B	4635a0

0x463fc0 UBFM	X16, X11, #61, #60

0x463fc4 LDR	D24, [X3, X16]

0x463fc8 FMADD	D25, D26, D4, D24

0x463fcc STR	D25, [X3, X16]

0x463fd0 B	463578

0x463fd4 UBFM	X9, X13, #61, #60

0x463fd8 LDR	D21, [X3, X9]

0x463fdc FMADD	D22, D26, D13, D21

0x463fe0 STR	D22, [X3, X9]

0x463fe4 B	463550

0x463ff4 UBFM	X16, X11, #61, #60

0x463ff8 LDR	D19, [X3, X16]

0x463ffc FMADD	D20, D26, D17, D19

0x464000 STR	D20, [X3, X16]

0x464004 B	463528

0x464008 FCMP	D31, #0

0x46400c B.EQ	462328

0x464010 FDIV	D26, D13, D31

0x464014 CMP	X10, X14

0x464018 B.LT	4633c0

0x46401c B	461aec

0x464048 ORR	X5, XZR, X25

0x46404c B	462d34

0x464084 LDR	X10, [SP, #280]

0x464088 LDR	X13, [SP, #312]

0x46408c B	46362c

/home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1609 - 1707

--------------------------------------------------------------------------------

1609:            for (jj = A_diag_i[i]+1; jj < A_diag_i[i+1]; jj++)

1610:            { /* i1 is a c-point and strongly influences i, accumulate

1611:               * a_(i,i1) into interpolation weight */

1612:              i1 = A_diag_j[jj];

1613:              if (P_marker[i1] >= jj_begin_row)

1614:              {

1615:                P_diag_data[P_marker[i1]] += A_diag_data[jj];

1616:              }

1617:              else if(P_marker[i1] == strong_f_marker)

1618:              {

1619:                sum = zero;

1620:                sgn = 1;

1621:                if(A_diag_data[A_diag_i[i1]] < 0) sgn = -1;

1622:                /* Loop over row of A for point i1 and calculate the sum

1623:                 * of the connections to c-points that strongly influence i. */

1624:                for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1625:                {

1626:                  i2 = A_diag_j[jj1];

1627:                  if((P_marker[i2] >= jj_begin_row || i2 == i) && (sgn*A_diag_data[jj1]) < 0)

1628:                    sum += A_diag_data[jj1];

1629:                }

1630:                if(num_procs > 1)

1631:                {

1632:                  for(jj1 = A_offd_i[i1]; jj1< A_offd_i[i1+1]; jj1++)

1633:                  {

1634:                    i2 = A_offd_j[jj1];

1635:                    if(P_marker_offd[i2] >= jj_begin_row_offd &&

1636:                       (sgn*A_offd_data[jj1]) < 0)

1637:                       sum += A_offd_data[jj1];

1638:                  }

1639:                }

1640:                if(sum != 0)

1641:                {

1642:                  distribute = A_diag_data[jj]/sum;

1643:                  /* Loop over row of A for point i1 and do the distribution */

1644:                  for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++)

1645:                  {

1646:                    i2 = A_diag_j[jj1];

1647:                    if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0)

1648:                       P_diag_data[P_marker[i2]] +=

1649:                       distribute*A_diag_data[jj1];

1650:                        if(i2 == i && (sgn*A_diag_data[jj1]) < 0)

1651:                          diagonal += distribute*A_diag_data[jj1];

1652:                  }

1653:                  if(num_procs > 1)

1654:                  {

1655:                    for(jj1 = A_offd_i[i1]; jj1 < A_offd_i[i1+1]; jj1++)

1656:                    {

1657:                      i2 = A_offd_j[jj1];

1658:                      if(P_marker_offd[i2] >= jj_begin_row_offd &&

1659:                                 (sgn*A_offd_data[jj1]) < 0)

1660:                        P_offd_data[P_marker_offd[i2]] +=

[...]

1667:                  diagonal += A_diag_data[jj];

1668:                }

1669:              }

1670:              /* neighbor i1 weakly influences i, accumulate a_(i,i1) into

1671:               * diagonal */

1672:              else if (CF_marker[i1] != -3)

1673:              {

1674:                if(num_functions == 1 || dof_func[i] == dof_func[i1])

1675:                  diagonal += A_diag_data[jj];

[...]

1707:                    for(jj1 = A_ext_i[i1]; jj1 < A_ext_i[i1+1]; jj1++)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:850	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►52.74+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:850	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec
►47.26+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

Coverage (%)	Name	Source Location	Module
►74.32+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►25.68+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:850	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►89.16+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►10.84+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:850	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►93.75+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►6.25+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:850	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►97.85+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.15+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:850	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►97.34+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.66+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:850	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Source Location	Module
►97.74+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.26+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:850	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

Coverage (%)	Name	Source Location	Module
►98.42+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	GOMP_parallel		libgomp.so.1.0.0
○	hypre_BoomerAMGBuildExtPIInter[...]	par_lr_interp.c:1196	exec
○	hypre_BoomerAMGSetup	par_amg_setup.c:850	exec
○	hypre_PCGSetup	pcg.c:234	exec
○	main	amg.c:398	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	amg.c:253	exec

Coverage (%)	Name	Module
►99.47+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.86
CQA speedup if FP arith vectorized	1.10
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1609-1609,par_lr_interp.c:1613-1621,par_lr_interp.c:1624-1632,par_lr_interp.c:1635-1637,par_lr_interp.c:1640-1655,par_lr_interp.c:1658-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675,par_lr_interp.c:1707-1707
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	67.63
CQA cycles if no scalar integer	23.67
CQA cycles if FP arith vectorized	61.72
CQA cycles if fully vectorized	54.00
Front-end cycles	67.63
P0 cycles	54.00
P1 cycles	54.00
P2 cycles	39.75
P3 cycles	39.75
P4 cycles	39.75
P5 cycles	39.75
P6 cycles	33.50
P7 cycles	33.50
P8 cycles	33.50
P9 cycles	33.50
P10 cycles	51.33
P11 cycles	51.33
P12 cycles	51.33
P13 cycles	2.00
P14 cycles	2.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	541.00
Nb uops	541.00
Nb loads	NA
Nb stores	16.00
Nb stack references	40.00
FLOP/cycle	1.27
Nb FLOP add-sub	26.00
Nb FLOP mul	27.00
Nb FLOP fma	15.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	1.56
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	10.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	1.52
Vector-efficiency ratio all	26.58
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	32.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	26.94

Metric	Value
CQA speedup if no scalar integer	2.86
CQA speedup if FP arith vectorized	1.10
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source	par_lr_interp.c:1609-1609,par_lr_interp.c:1613-1621,par_lr_interp.c:1624-1632,par_lr_interp.c:1635-1637,par_lr_interp.c:1640-1655,par_lr_interp.c:1658-1660,par_lr_interp.c:1667-1667,par_lr_interp.c:1672-1675,par_lr_interp.c:1707-1707
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	67.63
CQA cycles if no scalar integer	23.67
CQA cycles if FP arith vectorized	61.72
CQA cycles if fully vectorized	54.00
Front-end cycles	67.63
P0 cycles	54.00
P1 cycles	54.00
P2 cycles	39.75
P3 cycles	39.75
P4 cycles	39.75
P5 cycles	39.75
P6 cycles	33.50
P7 cycles	33.50
P8 cycles	33.50
P9 cycles	33.50
P10 cycles	51.33
P11 cycles	51.33
P12 cycles	51.33
P13 cycles	2.00
P14 cycles	2.00
DIV/SQRT cycles	5.25 - 10.49
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	541.00
Nb uops	541.00
Nb loads	NA
Nb stores	16.00
Nb stack references	40.00
FLOP/cycle	1.27
Nb FLOP add-sub	26.00
Nb FLOP mul	27.00
Nb FLOP fma	15.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	1.56
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	10.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	1.52
Vector-efficiency ratio all	26.58
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	32.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	26.94

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1609-1707
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1609-1660,1667-1675,1707.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c:1609,1613-1621,1624-1632,1635-1637,1640-1655,1658-1660,1667,1672-1675,1707.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 67.63 to 23.67 cycles (2.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 26% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 67.63 to 54.00 cycles (1.25x speedup).

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
10% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
1% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 15 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 86 FP arithmetical operations:

41: addition or subtraction (15 inside FMA instructions)
42: multiply (15 inside FMA instructions)
3: divide

The binary loop does not load or store any data.

General properties

nb instructions	541
nb uops	541
loop length	2164
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	26
used q registers	0
used v registers	0
used z registers	8
nb stack references	40
ADD-SUB / MUL ratio	0.74

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	67.63 cycles
front end	67.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	54.00	54.00	39.75	39.75	39.75	39.75	33.50	33.50	33.50	33.50	51.33	51.33	51.33	2.00	2.00
cycles	54.00	54.00	39.75	39.75	39.75	39.75	33.50	33.50	33.50	33.50	51.33	51.33	51.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	67.63
Dispatch	54.00
DIV/SQRT	5.25-10.49
Overall L1	67.63

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	2%

all	1%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	10%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	10%
fma	0%
div/sqrt	0%
other	1%

Vector efficiency ratios

INT

all	26%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	26%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	32%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	26%
load	25%
store	25%
mul	25%
add-sub	32%
fma	25%
div/sqrt	25%
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 67.63 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 67.63 to 54.00 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 461af8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
UBFM X3, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D26, [X4, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D17, D26, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D17, [X4, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461b50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X19, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 461ad8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4620b0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xfa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X20, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461b3c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X8, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D26, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D29, D29, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461af8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X14, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X18, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D28, D0, D1, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 463bb4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2aa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X25, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X13, X25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X13, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 463be8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2adc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDPL X13, X25, #63	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
DUP Z2.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X5, X18, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z3.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X7, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z5.D, Z28.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
DUP Z31.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
PTRUE P4.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FADDV D17, P4, Z31.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
ADD X9, X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D31, D14, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X16, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462310 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X7, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X11, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X25, X13, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X16, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 4621ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x10a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D18, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D19, D28, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D20, D31, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D20, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 462310 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X25, 462258 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x114c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462224 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4621f8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x10ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X5, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 4621f4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x10e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D21, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D22, D28, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D13, D31, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D22, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D13, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X16, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 462220 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D23, D28, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D24, D31, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D24, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X13, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 46224c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D25, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D26, D28, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D27, D31, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D27, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 462310 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D13, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462c90 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1b84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4633bc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D29, D29, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X9, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X5, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X5, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 464008 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2efc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X3, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X16, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X16, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 464048 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2f3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X17, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X13, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
DUP Z22.D, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z4.D, Z28.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z23.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X5, X5, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADDV D2, P0, Z23.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
ADD X5, X3, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D31, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X9, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46300c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X17, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X13, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X16, X9, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462d6c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1c60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D5, D3, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D30, D31, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D5, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D30, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X3, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46300c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X16, 462ec0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1db4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462e88 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462e5c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462e30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462e1c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462e08 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1cfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462ddc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1cd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462dd8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1ccc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D6, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D7, D6, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D16, D31, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D16, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462e04 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1cf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D17, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D18, D17, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D19, D31, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D19, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X24, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 463e5c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2d50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 463de0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2cd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X24, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462e58 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D25, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D26, D25, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D27, D31, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D27, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462e84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D2, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D3, D2, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D5, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D5, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462eb0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1da4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D30, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D6, D30, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D7, D31, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D7, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X3, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46300c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 462328 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x121c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D13, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
CMP X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4633c0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4634b8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D13, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR X25, [X7, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X11, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X5, X16, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X19, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463b24 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D13, D31, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D13, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463b14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 463498 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x238c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X5, 463860 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2754>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46346c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 463430 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463f60 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2e54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D25, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D2, D25, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463f50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2e44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463460 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D7, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D16, D7, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D16, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 463468 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x235c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X13, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X4, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D18, D26, D7, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D18, [X4, X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 463f30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2e24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463b94 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D13, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D21, D13, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463b84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463860 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2754>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X11, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X11, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X25, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X13, X5, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X10, X13, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDR X3, [X9, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.EQ 464084 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2f78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 463604 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4635cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4635a4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46357c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 463554 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46352c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463528 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x241c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D17, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D18, D17, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463ff4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ee8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463550 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D13, [X10, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D31, D13, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463fd4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ec8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463578 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x246c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D23, D4, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463fc0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2eb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4635a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D2, [X10, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D27, D2, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463fac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ea0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4635c8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D6, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D7, D6, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463f94 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2e88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463600 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D17, [X10, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D18, D17, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 463600 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X3, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D20, D26, D17, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D20, [X3, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 463e94 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2d88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X25, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X13, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X4, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D22, D26, D31, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D22, [X4, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4633ec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D23, D4, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D24, D26, D4, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D29, D24, D29, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 4633ec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X25, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X4, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D4, D26, D13, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D4, [X4, X25]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46348c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D23, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D24, D23, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D25, D26, D23, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D29, D25, D29, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 46348c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D13, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462c8c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1b80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D29, D29, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X9, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 462178 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x106c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D23, D4, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D24, D31, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D24, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 462e2c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D20, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D21, D20, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D22, D31, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D22, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 462e18 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D13, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D31, D13, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 463614 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X16, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X3, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D22, D26, D13, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D22, [X3, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 463614 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D20, D19, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D31, D26, D19, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D29, D31, D29, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 463468 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x235c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X11, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X4, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D3, D26, D25, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D3, [X4, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46342c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL D6, D5, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D30, D26, D5, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D29, D30, D29, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 463430 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X16, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X3, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D16, D26, D6, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D16, [X3, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 4635cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X3, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D5, D26, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D5, [X3, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 4635a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X16, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D24, [X3, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D25, D26, D4, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D25, [X3, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 463578 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x246c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X3, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D22, D26, D13, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D22, [X3, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 463550 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X16, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X3, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D20, D26, D17, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D20, [X3, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 463528 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x241c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 462328 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x121c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D13, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
CMP X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4633c0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X5, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 462d34 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1c28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46362c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	hypre_BoomerAMGBuildExtPIInterp._omp_fn.0
Source file and lines	par_lr_interp.c:1609-1707
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths (too many, greater than internal limit = 100000)
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is very high. Force analysis with --force-loop-streams-analysis: expect potentially high RAM/CPU footprint

Try to simplify control.

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
10% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
1% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 15 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 86 FP arithmetical operations:

41: addition or subtraction (15 inside FMA instructions)
42: multiply (15 inside FMA instructions)
3: divide

The binary loop does not load or store any data.

General properties

nb instructions	541
nb uops	541
loop length	2164
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	1
used d registers	26
used q registers	0
used v registers	0
used z registers	8
nb stack references	40
ADD-SUB / MUL ratio	0.74

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	67.63 cycles
front end	67.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	54.00	54.00	39.75	39.75	39.75	39.75	33.50	33.50	33.50	33.50	51.33	51.33	51.33	2.00	2.00
cycles	54.00	54.00	39.75	39.75	39.75	39.75	33.50	33.50	33.50	33.50	51.33	51.33	51.33	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

5.25-10.49

Cycles summary

Front-end	67.63
Dispatch	54.00
DIV/SQRT	5.25-10.49
Overall L1	67.63

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	2%

all	1%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	10%
fma	0%
div/sqrt	0%
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	10%
fma	0%
div/sqrt	0%
other	1%

Vector efficiency ratios

INT

all	26%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	26%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	32%
fma	25%
div/sqrt	25%
other	25%

INT+FP

all	26%
load	25%
store	25%
mul	25%
add-sub	32%
fma	25%
div/sqrt	25%
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 67.63 cycles.

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 461af8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
UBFM X3, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D28, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D26, [X4, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D17, D26, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D17, [X4, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461b50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X2, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X19, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 461ad8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4620b0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xfa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X20, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMN X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461b3c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0xa30>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X8, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X8, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X25, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D26, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D29, D29, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X1, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 461af8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X14, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X5, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X18, X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D28, D0, D1, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
CMP X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 463bb4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2aa8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X25, X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X13, X25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X16, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X13, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 463be8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2adc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X9, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDPL X13, X25, #63	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
DUP Z2.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X5, X18, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z3.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X13, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X9, X7, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z5.D, Z28.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
DUP Z31.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
PTRUE P4.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FADDV D17, P4, Z31.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
ADD X9, X3, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D31, D14, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X16, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462310 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X7, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X11, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X25, X13, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X3, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X16, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 4621ac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x10a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D18, [X18, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D19, D28, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D20, D31, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D20, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 462310 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X25, 462258 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x114c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462224 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1118>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X25, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4621f8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x10ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X19, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X5, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 4621f4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x10e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D21, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D22, D28, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D13, D31, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D22, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D13, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X16, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 462220 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1114>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D23, D28, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D24, D31, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D24, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X19, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CCMP X21, X13, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
B.NE 46224c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D25, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D26, D28, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D27, D31, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D27, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 462310 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D13, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462c90 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1b84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 4633bc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D29, D29, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X9, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X5, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X5, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X25, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 464008 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2efc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X13, X3, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB X16, X13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X13, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X16, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 464048 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2f3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X17, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ X3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X13, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTB X11, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
DUP Z22.D, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z4.D, Z28.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z23.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
PTRUE P0.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
ADD X5, X5, X25,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADDV D2, P0, Z23.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
ADD X5, X3, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FADD D31, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
CMP X9, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46300c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [X17, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X13, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X9, X13, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X16, X9, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X6, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462d6c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1c60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X13, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D5, D3, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D30, D31, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D5, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D30, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X3, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46300c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X16, 462ec0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1db4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462e88 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462e5c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462e30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462e1c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462e08 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1cfc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X16, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 462ddc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1cd0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462dd8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1ccc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D6, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D7, D6, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D16, D31, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D16, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462e04 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1cf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D17, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D18, D17, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D19, D31, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D19, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X24, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 463e5c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2d50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X24, X13,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 463de0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2cd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X24, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462e58 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X13, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D25, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D26, D25, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D27, D31, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D26, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D27, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462e84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D2, [X9, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D3, D2, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D5, D31, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D5, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X24, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462eb0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1da4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D30, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D6, D30, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D7, D31, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D7, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X11, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X3, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 46300c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1f00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 462328 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x121c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D13, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
CMP X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4633c0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 4634b8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x23ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D13, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
LDR X25, [X7, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORN X11, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X11, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X5, X16, #0x3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X13, [X19, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463b24 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a18>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D31, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D13, D31, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D13, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463b14 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 463498 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x238c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X5, 463860 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2754>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46346c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X5, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 463430 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463f60 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2e54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D25, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D2, D25, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D2, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463f50 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2e44>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X19, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463460 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2354>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D7, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D16, D7, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D16, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 463468 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x235c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X13, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D17, [X4, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D18, D26, D7, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D18, [X4, X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 463f30 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2e24>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X19, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463b94 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D13, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D21, D13, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463b84 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2a78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X14, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463860 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2754>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X11, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X11, X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X5, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X25, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GE 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X13, X5, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ANDS X10, X13, #0x7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDR X3, [X9, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B.EQ 464084 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2f78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 463604 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4635cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 4635a4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46357c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 463554 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2448>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X10, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 46352c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X14, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463528 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x241c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D17, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D18, D17, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463ff4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ee8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463550 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D13, [X10, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D31, D13, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463fd4 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ec8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463578 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x246c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D23, D4, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463fc0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2eb4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4635a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D2, [X10, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D27, D2, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463fac <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2ea0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 4635c8 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D6, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D7, D6, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D7, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.MI 463f94 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2e88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X24, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 463600 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D17, [X10, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D18, D17, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D18, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 463600 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X3, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D20, D26, D17, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D20, [X3, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X14, [X17, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X24, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X6, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 463e94 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2d88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X25, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X13, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X4, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D22, D26, D31, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D22, [X4, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 4633ec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D4, [X18, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D23, D4, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D24, D26, D4, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D29, D24, D29, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 4633ec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X25, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D22, [X4, X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D4, D26, D13, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D4, [X4, X25]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46348c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D23, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D24, D23, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D25, D26, D23, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D29, D25, D29, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 46348c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2380>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D13, [X18, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
CMP X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.GT 462c8c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1b80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D14, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.NE 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D29, D29, D13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D31, D14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X9, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 462178 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x106c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D4, [X11, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D23, D4, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D24, D31, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D23, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D24, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 462e2c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X16, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D20, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D21, D20, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FADD D22, D31, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D31, D22, D31, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 462e18 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1d0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D13, [X2, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D31, D13, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.GE 463614 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X16, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X3, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D22, D26, D13, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D22, [X3, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 463614 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2508>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMUL D20, D19, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D31, D26, D19, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D20, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D29, D31, D29, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 463468 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x235c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X11, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D27, [X4, X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D3, D26, D25, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D3, [X4, X11]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
CMP X21, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 46342c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2320>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X18, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMUL D6, D5, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D30, D26, D5, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D29, D30, D29, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
B 463430 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2324>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X16, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D30, [X3, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D16, D26, D6, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D16, [X3, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 4635cc <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x24c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D3, [X3, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D5, D26, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D5, [X3, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 4635a0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2494>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X16, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D24, [X3, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D25, D26, D4, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D25, [X3, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 463578 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x246c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X9, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D21, [X3, X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D22, D26, D13, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D22, [X3, X9]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 463550 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2444>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X16, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D19, [X3, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FMADD D20, D26, D17, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
STR D20, [X3, X16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B 463528 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x241c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FCMP D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.EQ 462328 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x121c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV D26, D13, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	7-15	1.75-3.50	scal (25.0%)
CMP X10, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 4633c0 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x22b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 461aec <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x9e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X5, XZR, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 462d34 <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x1c28>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
B 46362c <hypre_BoomerAMGBuildExtPIInterp._omp_fn.0+0x2520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: NARun Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Run Command: <executable> -n 400 400 400MPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=64 --rank-by fill --report-bindings Dataset: Run Directory: /home/eoseret/qaas/qaas_runs/178-188-3659/intel/AMG/run/oneview_runs/multicore/gcc_1/oneview_run_1781892409OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)
1	0	1.68	0	3.09	0	4.97	0	8.11	0	12.05	0	15.47	0	20.56	0	21.04	0	26.39	0	30.13	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.63499999046326	0.18347333371639
1x2	2	1.68	1.68	2	0.38499999046326	0.20218716561794
1x4	4	3.09	3.09	4	0.21499998867512	0.20048075914383
1x8	8	4.97	4.97	8	0.13000001013279	0.20669849216938
1x16	16	8.11	8.11	16	0.10000000149012	0.14905667304993
1x24	24	12.05	12.05	24	0.060000002384186	0.1055536866188
1x32	32	15.47	15.47	32	0.044999998062849	0.087827749550343
1x40	40	20.56	20.56	40	0.045000001788139	0.069932781159878
1x48	47	21.04	21.04	48	0.035000000149012	0.068112500011921
1x56	54	26.39	26.39	56	0.03999999910593	0.055188406258821
1x64	61	30.13	30.13	64	0.030000001192093	0.047437824308872

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency