OV - exec - Function calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, double&, int&, double&, double&, int&, int&, int&) [clone .omp

	Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ...	Module: exec	Source: calc_dt.cpp:49-75 [...]	Coverage (incl. loops): 4.54% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 49 - 75

--------------------------------------------------------------------------------

49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42c730 STP	D15, D14, [SP, #864]!

0x42c734 STP	D13, D12, [SP, #16]

0x42c738 STP	D11, D10, [SP, #32]

0x42c73c STP	D9, D8, [SP, #48]

0x42c740 STP	X29, X30, [SP, #64]

0x42c744 STP	X28, X27, [SP, #80]

0x42c748 STP	X26, X25, [SP, #96]

0x42c74c STP	X24, X23, [SP, #112]

0x42c750 STP	X22, X21, [SP, #128]

0x42c754 STP	X20, X19, [SP, #144]

0x42c758 ADD	X29, SP, #64

0x42c75c SUB	SP, SP, #160

0x42c760 ADDVL	SP, SP, #63

0x42c764 LDR	W8, [X2]

0x42c768 LDR	W24, [X4]

0x42c76c LDR	W9, [X5]

0x42c770 ADD	W23, W8, #1

0x42c774 LDR	W8, [X3]

0x42c778 ADD	W27, W24, #1

0x42c77c ADD	W9, W9, #2

0x42c780 ADD	W8, W8, #2

0x42c784 SUBS	W8, W8, W23

0x42c788 CCMP	W9, W27, #4, #12

0x42c78c B.LE	42c960

0x42c790 LDR	W22, [X0]

0x42c794 LDR	X19, [X29, #192]

0x42c798 SUB	W25, W9, W27

0x42c79c MOVN	X9, #0

0x42c7a0 ORR	X20, XZR, X7

0x42c7a4 ORR	X21, XZR, X6

0x42c7a8 MOVZ	W10, #1

0x42c7ac ADRP	X0,

0x42c7b0 ADD	X0, X0, #1016

0x42c7b4 UMADDL	X26, W25, W8, X9

0x42c7b8 MOVN	X8, #32784

0x42c7bc ADD	X3, SP, #132

0x42c7c0 STR	X10, [SP, #136]

0x42c7c4 STR	WZR, [SP, #132]

0x42c7c8 ADD	X4, SP, #152

0x42c7cc ADD	X5, SP, #144

0x42c7d0 ADD	X6, SP, #136

0x42c7d4 MOVZ	W2, #34

0x42c7d8 STR	X8, [SP, #120]

0x42c7dc STR	X10, [SP]

0x42c7e0 MOVZ	W7, #1

0x42c7e4 STP	X26, XZR, [SP, #144]

0x42c7e8 ORR	W1, WZR, W22

0x42c7ec BL	4101a0

0x42c7f0 LDP	X9, X8, [SP, #144]

0x42c7f4 CMP	X9, X26

0x42c7f8 CSEL	X7, X9, X26, #11

0x42c7fc CMP	X8, X7

0x42c800 STR	X7, [SP, #144]

0x42c804 B.LE	42c88c

0x42c808 ADRP	X0,

0x42c80c ADD	X0, X0, #1040

0x42c810 ORR	W1, WZR, W22

0x42c814 BL	410050

0x42c818 ADD	X8, SP, #120

0x42c81c ADRP	X6,

0x42c820 ADRP	X0,

0x42c824 ADD	X0, X0, #1064

0x42c828 ORR	W1, WZR, W22

0x42c82c STR	X8, [SP, #112]

0x42c830 ADRP	X5, 42c830

0x42c834 ADD	X5, X5, #3904

0x42c838 ADD	X4, SP, #112

0x42c83c MOVZ	W2, #1

0x42c840 LDR	X6, [X6, #3936]

0x42c844 MOVZ	W3, #8

0x42c848 BL	410120

0x42c84c CMP	W0, #2

0x42c850 B.EQ	42c930

0x42c854 CMP	W0, #1

0x42c858 B.NE	42c960

0x42c85c LDR	D0, [X19]

0x42c860 LDR	D1, [SP, #120]

0x42c864 ADRP	X2,

0x42c868 ADRP	X0,

0x42c86c ADD	X0, X0, #1064

0x42c870 ORR	W1, WZR, W22

0x42c874 FCMP	D0, D1

0x42c878 FCSEL	D0, D0, D1, #4

0x42c87c STR	D0, [X19]

0x42c880 LDR	X2, [X2, #3936]

0x42c884 BL	4101f0

0x42c888 B	42c960

0x42c88c LDP	X28, X26, [X29, #176]

0x42c890 LDP	X2, X3, [X29, #144]

0x42c894 ADD	X7, X7, #1

0x42c898 LDR	X9, [X21, #8]

0x42c89c MOVN	X21, #32784

0x42c8a0 LDR	X10, [X20, #8]

0x42c8a4 LDR	D1, [X2]

0x42c8a8 LDP	X16, X17, [X29, #112]

0x42c8ac LDP	X5, X30, [X29, #160]

0x42c8b0 LDP	X18, X1, [X29, #128]

0x42c8b4 LDR	D2, [X28]

0x42c8b8 LDP	X12, X14, [X29, #96]

0x42c8bc FADD	D1, D1, D1

0x42c8c0 LDR	D0, [X17]

0x42c8c4 LDR	X2, [X3, #16]

0x42c8c8 LDR	X3, [X3]

0x42c8cc LDR	D3, [X26]

0x42c8d0 LDR	X11, [X12, #16]

0x42c8d4 LDR	X12, [X12]

0x42c8d8 LDR	X13, [X14, #16]

0x42c8dc LDR	X14, [X14]

0x42c8e0 LDR	X15, [X16, #16]

0x42c8e4 LDR	X16, [X16]

0x42c8e8 LDR	X17, [X18, #16]

0x42c8ec LDR	X18, [X18]

0x42c8f0 LDR	X0, [X1, #16]

0x42c8f4 LDR	X1, [X1]

0x42c8f8 LDR	X4, [X5, #16]

0x42c8fc LDR	X5, [X5]

0x42c900 LDR	X6, [X30, #16]

0x42c904 FADD	D2, D2, D2

0x42c908 LDR	X20, [X30]

0x42c90c STP	X7, X3, [SP, #72]

0x42c910 SUB	X7, X7, X8

0x42c914 CMP	X7, #2

0x42c918 STP	X16, X14, [SP, #96]

0x42c91c STR	X1, [SP, #88]

0x42c920 B.CS	42c994

0x42c924 FMOV	D4, X21

0x42c928 ORR	X30, XZR, X12

0x42c92c B	42cd60

0x42c930 LDR	X8, [X19]

0x42c934 LDR	D0, [SP, #120]

0x42c938 ORR	X9, XZR, X8

0x42c93c HINT	#0

(182) 0x42c940 FMOV	D1, X8

(182) 0x42c944 FCMP	D0, D1

(182) 0x42c948 FCSEL	D1, D1, D0, #12

(182) 0x42c94c FMOV	X10, D1

(182) 0x42c950 CAS	X9, X10, [X19]

(182) 0x42c954 CMP	X9, X8

(182) 0x42c958 ORR	X8, XZR, X9

(182) 0x42c95c B.NE	42c940

0x42c960 ADDVL	SP, SP, #1

0x42c964 ADD	SP, SP, #160

0x42c968 LDP	D9, D8, [SP, #48]

0x42c96c LDP	D11, D10, [SP, #32]

0x42c970 LDP	D13, D12, [SP, #16]

0x42c974 LDP	X20, X19, [SP, #144]

0x42c978 LDP	X22, X21, [SP, #128]

0x42c97c LDP	X24, X23, [SP, #112]

0x42c980 LDP	X26, X25, [SP, #96]

0x42c984 LDP	X28, X27, [SP, #80]

0x42c988 LDP	X29, X30, [SP, #64]

0x42c98c LDP	D15, D14, [SP], #160

0x42c990 RET

0x42c994 DUP	V25.2D, X21

0x42c998 MOVZ	X21, #35260

0x42c99c INDEX	Z17.D, #0, #1

0x42c9a0 DUP	V7.2D, X8

0x42c9a4 DUP	V21.2S, W23

0x42c9a8 STR	X19, [SP, #64]

0x42c9ac MOVK	X21, #38872

0x42c9b0 AND	X19, X7, #0xfffffffe

0x42c9b4 STP	X12, X25, [SP, #40]

0x42c9b8 STR	W22, [SP, #60]

0x42c9bc STP	X19, X7, [SP, #24]

0x42c9c0 MOVK	X21, #53938

0x42c9c4 MOVK	X21, #15516

0x42c9c8 DUP	V22.2S, W27

0x42c9cc AND	X27, X7, #0xfffffffe

0x42c9d0 ADD	V23.2D, V7.2D, V17.2D

0x42c9d4 DUP	V27.2D, X21

0x42c9d8 MOVZ	X21, #35260

0x42c9dc MOVK	X21, #38872

0x42c9e0 MOVI	V7.2S, #1

0x42c9e4 DUP	V4.2D, X12

0x42c9e8 SUB	X12, X29, #64

0x42c9ec MOVK	X21, #53938

0x42c9f0 DUP	V5.2D, X14

0x42c9f4 STR	Z4, [X12, #511, MUL VL]

0x42c9f8 MOVK	X21, #48284

0x42c9fc DUP	V6.2D, X16

0x42ca00 ADD	V24.2S, V21.2S, V7.2S

0x42ca04 ADD	V26.2S, V22.2S, V7.2S

0x42ca08 DUP	V28.2D, X18

0x42ca0c DUP	V16.2D, X1

0x42ca10 DUP	V30.2D, X3

0x42ca14 DUP	V31.2D, X5

0x42ca18 DUP	V19.2D, X20

0x42ca1c DUP	V20.2D, X25

0x42ca20 PTRUE	P0.D, VL2

0x42ca24 DUP	V29.2D, X21

0x42ca28 MOVZ	X21, #61264

0x42ca2c MOVK	X21, #55010

0x42ca30 MOVK	X21, #6884

0x42ca34 MOVK	X21, #17483

0x42ca38 DUP	V8.2D, X21

0x42ca3c HINT	#0

(181) 0x42ca40 MOVPRFX	Z7, Z23

(181) 0x42ca44 SDIV	Z7.D, P0/M, Z7.D, Z20.D

(181) 0x42ca48 SUB	X12, X29, #64

(181) 0x42ca4c SUBS	X27, X27, #2

(181) 0x42ca50 LDR	Z4, [X12, #511, MUL VL]

(181) 0x42ca54 XTN	V10.2S, V7.2D

(181) 0x42ca58 MSB	Z7.D, P0/M, Z20.D, Z23.D

(181) 0x42ca5c ADD	V17.2S, V21.2S, V10.2S

(181) 0x42ca60 SSHLL	V11.2D, V17.2S, #32

(181) 0x42ca64 XTN	V9.2S, V7.2D

(181) 0x42ca68 MOVPRFX	Z12, Z4

(181) 0x42ca6c MUL	Z12.D, P0/M, Z12.D, Z11.D

(181) 0x42ca70 MOVPRFX	Z13, Z5

(181) 0x42ca74 MUL	Z13.D, P0/M, Z13.D, Z11.D

(181) 0x42ca78 FMOV	X19, D11

(181) 0x42ca7c MOVPRFX	Z14, Z6

(181) 0x42ca80 MUL	Z14.D, P0/M, Z14.D, Z11.D

(181) 0x42ca84 MOV	X21, V11.D[1]

(181) 0x42ca88 MOVPRFX	Z15, Z16

(181) 0x42ca8c MUL	Z15.D, P0/M, Z15.D, Z11.D

(181) 0x42ca90 MOVPRFX	Z18, Z31

(181) 0x42ca94 MUL	Z18.D, P0/M, Z18.D, Z11.D

(181) 0x42ca98 ADD	V7.2S, V22.2S, V9.2S

(181) 0x42ca9c ADD	V9.2S, V9.2S, V26.2S

(181) 0x42caa0 ADD	X21, X10, X21,LSL #3

(181) 0x42caa4 SSHLL	V17.2D, V7.2S, #32

(181) 0x42caa8 MOVPRFX	Z7, Z28

(181) 0x42caac MUL	Z7.D, P0/M, Z7.D, Z11.D

(181) 0x42cab0 SSHLL	V9.2D, V9.2S, #32

(181) 0x42cab4 FMOV	X30, D17

(181) 0x42cab8 MOV	X14, V12.D[1]

(181) 0x42cabc FMOV	X26, D12

(181) 0x42cac0 MOV	X16, V13.D[1]

(181) 0x42cac4 FMOV	X1, D13

(181) 0x42cac8 LDR	D13, [X10, X19,LSL #3]

(181) 0x42cacc MOV	X28, V17.D[1]

(181) 0x42cad0 MOVPRFX	Z17, Z30

(181) 0x42cad4 MUL	Z17.D, P0/M, Z17.D, Z11.D

(181) 0x42cad8 UBFM	X22, X30, #61, #60

(181) 0x42cadc ADD	X12, X9, X28,LSL #3

(181) 0x42cae0 ADD	X19, X13, X30,LSL #3

(181) 0x42cae4 ADD	X25, X17, X28,LSL #3

(181) 0x42cae8 MUL	Z11.D, P0/M, Z11.D, Z19.D

(181) 0x42caec LDR	D12, [X9, X22]

(181) 0x42caf0 ADD	X22, X13, X28,LSL #3

(181) 0x42caf4 LD1	{V13.D[1]}, [X21]

(181) 0x42caf8 ADD	X21, X11, X30,LSL #3

(181) 0x42cafc LD1	{V12.D[1]}, [X12]

(181) 0x42cb00 ADD	X12, X22, X16,LSL #3

(181) 0x42cb04 MOV	X16, V14.D[1]

(181) 0x42cb08 FMOV	X22, D14

(181) 0x42cb0c LDR	D14, [X19, X1,LSL #3]

(181) 0x42cb10 ADD	X1, X15, X28,LSL #3

(181) 0x42cb14 ADD	X19, X17, X30,LSL #3

(181) 0x42cb18 ADD	X16, X1, X16,LSL #3

(181) 0x42cb1c FMOV	X1, D7

(181) 0x42cb20 LDR	D4, [X19, X1,LSL #3]

(181) 0x42cb24 LD1	{V14.D[1]}, [X12]

(181) 0x42cb28 MOV	X12, V7.D[1]

(181) 0x42cb2c ADD	V7.2S, V10.2S, V24.2S

(181) 0x42cb30 SSHLL	V10.2D, V7.2S, #32

(181) 0x42cb34 FMINNM	V7.2D, V12.2D, V13.2D

(181) 0x42cb38 MOVPRFX	Z12, Z28

(181) 0x42cb3c MUL	Z12.D, P0/M, Z12.D, Z10.D

(181) 0x42cb40 FMUL	V7.2D, V7.2D, V0.D[0]

(181) 0x42cb44 FADD	V13.2D, V14.2D, V14.2D

(181) 0x42cb48 FMOV	X7, D12

(181) 0x42cb4c MOV	X3, V12.D[1]

(181) 0x42cb50 LDR	D12, [X19, X7,LSL #3]

(181) 0x42cb54 ADD	X19, X25, X12,LSL #3

(181) 0x42cb58 ADD	X25, X25, X3,LSL #3

(181) 0x42cb5c LD1	{V4.D[1]}, [X19]

(181) 0x42cb60 ADD	X19, X11, X28,LSL #3

(181) 0x42cb64 ADD	X14, X19, X14,LSL #3

(181) 0x42cb68 LD1	{V12.D[1]}, [X25]

(181) 0x42cb6c ADD	X25, X15, X30,LSL #3

(181) 0x42cb70 FADD	V4.2D, V4.2D, V12.2D

(181) 0x42cb74 LDR	D12, [X25, X22,LSL #3]

(181) 0x42cb78 FMOV	X22, D9

(181) 0x42cb7c ADD	X25, X17, X22,LSL #3

(181) 0x42cb80 LD1	{V12.D[1]}, [X16]

(181) 0x42cb84 MOV	X16, V9.D[1]

(181) 0x42cb88 LDR	D9, [X25, X1,LSL #3]

(181) 0x42cb8c MOV	X1, V15.D[1]

(181) 0x42cb90 FDIV	V13.2D, V13.2D, V12.2D

(181) 0x42cb94 LDR	D12, [X25, X7,LSL #3]

(181) 0x42cb98 FMOV	X7, D15

(181) 0x42cb9c ADD	X25, X0, X30,LSL #3

(181) 0x42cba0 LDR	D14, [X25, X7,LSL #3]

(181) 0x42cba4 ADD	X25, X0, X28,LSL #3

(181) 0x42cba8 ADD	X19, X25, X1,LSL #3

(181) 0x42cbac LD1	{V14.D[1]}, [X19]

(181) 0x42cbb0 ADD	X19, X17, X16,LSL #3

(181) 0x42cbb4 ADD	X12, X19, X12,LSL #3

(181) 0x42cbb8 ADD	X3, X19, X3,LSL #3

(181) 0x42cbbc LD1	{V9.D[1]}, [X12]

(181) 0x42cbc0 LD1	{V12.D[1]}, [X3]

(181) 0x42cbc4 ADD	X12, X0, X22,LSL #3

(181) 0x42cbc8 ADD	X3, X0, X16,LSL #3

(181) 0x42cbcc ADD	X22, X4, X22,LSL #3

(181) 0x42cbd0 ADD	X16, X4, X16,LSL #3

(181) 0x42cbd4 ADD	X1, X3, X1,LSL #3

(181) 0x42cbd8 ADD	X3, X2, X30,LSL #3

(181) 0x42cbdc FMUL	V4.2D, V4.2D, V14.2D

(181) 0x42cbe0 FADD	V9.2D, V9.2D, V12.2D

(181) 0x42cbe4 LDR	D12, [X12, X7,LSL #3]

(181) 0x42cbe8 MOV	X12, V17.D[1]

(181) 0x42cbec ADD	X7, X2, X28,LSL #3

(181) 0x42cbf0 ADD	X12, X7, X12,LSL #3

(181) 0x42cbf4 ADD	X7, X4, X28,LSL #3

(181) 0x42cbf8 LD1	{V12.D[1]}, [X1]

(181) 0x42cbfc FMOV	X1, D17

(181) 0x42cc00 LDR	D17, [X3, X1,LSL #3]

(181) 0x42cc04 FMOV	X1, D18

(181) 0x42cc08 ADD	X3, X4, X30,LSL #3

(181) 0x42cc0c LD1	{V17.D[1]}, [X12]

(181) 0x42cc10 FMUL	V9.2D, V9.2D, V12.2D

(181) 0x42cc14 MOVI	V12.2D, #0

(181) 0x42cc18 MOV	X12, V18.D[1]

(181) 0x42cc1c ADD	X19, X7, X12,LSL #3

(181) 0x42cc20 ADD	X12, X16, X12,LSL #3

(181) 0x42cc24 FADD	V12.2D, V9.2D, V12.2D

(181) 0x42cc28 FABS	V9.2D, V9.2D

(181) 0x42cc2c FSUB	V12.2D, V12.2D, V4.2D

(181) 0x42cc30 FABS	V4.2D, V4.2D

(181) 0x42cc34 FMAXNM	V4.2D, V4.2D, V9.2D

(181) 0x42cc38 FMUL	V9.2D, V17.2D, V27.2D

(181) 0x42cc3c FMUL	V14.2D, V17.2D, V1.D[0]

(181) 0x42cc40 FMAXNM	V4.2D, V4.2D, V9.2D

(181) 0x42cc44 FDIV	V18.2D, V14.2D, V4.2D

(181) 0x42cc48 LDR	D4, [X3, X1,LSL #3]

(181) 0x42cc4c LDR	D14, [X22, X1,LSL #3]

(181) 0x42cc50 ADD	X1, X6, X30,LSL #3

(181) 0x42cc54 LD1	{V4.D[1]}, [X19]

(181) 0x42cc58 LD1	{V14.D[1]}, [X12]

(181) 0x42cc5c MOV	X12, V11.D[1]

(181) 0x42cc60 ADD	X19, X6, X28,LSL #3

(181) 0x42cc64 ADD	X12, X19, X12,LSL #3

(181) 0x42cc68 FADD	V4.2D, V4.2D, V14.2D

(181) 0x42cc6c LDR	D14, [X21, X26,LSL #3]

(181) 0x42cc70 LD1	{V14.D[1]}, [X14]

(181) 0x42cc74 FMOV	X14, D11

(181) 0x42cc78 LDR	D11, [X1, X14,LSL #3]

(181) 0x42cc7c FMUL	V14.2D, V14.2D, V14.2D

(181) 0x42cc80 LD1	{V11.D[1]}, [X12]

(181) 0x42cc84 FADD	V13.2D, V14.2D, V13.2D

(181) 0x42cc88 MOVPRFX	Z14, Z31

(181) 0x42cc8c MUL	Z14.D, P0/M, Z14.D, Z10.D

(181) 0x42cc90 MUL	Z10.D, P0/M, Z10.D, Z19.D

(181) 0x42cc94 FMOV	X14, D14

(181) 0x42cc98 FMUL	V4.2D, V4.2D, V11.2D

(181) 0x42cc9c MOV	X12, V14.D[1]

(181) 0x42cca0 LDR	D11, [X22, X14,LSL #3]

(181) 0x42cca4 LDR	D14, [X3, X14,LSL #3]

(181) 0x42cca8 FMOV	X14, D10

(181) 0x42ccac ADD	X7, X7, X12,LSL #3

(181) 0x42ccb0 ADD	X12, X16, X12,LSL #3

(181) 0x42ccb4 LD1	{V11.D[1]}, [X12]

(181) 0x42ccb8 MOV	X12, V10.D[1]

(181) 0x42ccbc LDR	D10, [X1, X14,LSL #3]

(181) 0x42ccc0 LD1	{V14.D[1]}, [X7]

(181) 0x42ccc4 ADD	X12, X19, X12,LSL #3

(181) 0x42ccc8 FADD	V11.2D, V14.2D, V11.2D

(181) 0x42cccc LD1	{V10.D[1]}, [X12]

(181) 0x42ccd0 FMUL	V10.2D, V11.2D, V10.2D

(181) 0x42ccd4 FADD	V11.2D, V12.2D, V10.2D

(181) 0x42ccd8 FABS	V10.2D, V10.2D

(181) 0x42ccdc FSUB	V11.2D, V11.2D, V4.2D

(181) 0x42cce0 FABS	V4.2D, V4.2D

(181) 0x42cce4 FMAXNM	V4.2D, V4.2D, V10.2D

(181) 0x42cce8 FSQRT	V10.2D, V13.2D

(181) 0x42ccec FMAXNM	V4.2D, V4.2D, V9.2D

(181) 0x42ccf0 FMUL	V9.2D, V17.2D, V2.D[0]

(181) 0x42ccf4 FADD	V17.2D, V17.2D, V17.2D

(181) 0x42ccf8 FDIV	V17.2D, V11.2D, V17.2D

(181) 0x42ccfc FDIV	V4.2D, V9.2D, V4.2D

(181) 0x42cd00 FMOV	V9.2D, #-1.0000000

(181) 0x42cd04 FMAXNM	V10.2D, V10.2D, V27.2D

(181) 0x42cd08 FDIV	V7.2D, V7.2D, V10.2D

(181) 0x42cd0c FDIV	V9.2D, V9.2D, V17.2D

(181) 0x42cd10 FCMGT	V17.2D, V29.2D, V17.2D

(181) 0x42cd14 FMUL	V9.2D, V9.2D, V3.D[0]

(181) 0x42cd18 FMINNM	V9.2D, V9.2D, V8.2D

(181) 0x42cd1c BSL	V17.16B, V9.16B, V8.16B

(181) 0x42cd20 FMINNM	V4.2D, V4.2D, V17.2D

(181) 0x42cd24 FMINNM	V4.2D, V18.2D, V4.2D

(181) 0x42cd28 FMINNM	V4.2D, V7.2D, V4.2D

(181) 0x42cd2c FMINNM	V25.2D, V4.2D, V25.2D

(181) 0x42cd30 DUP	Z4.D, #2

(181) 0x42cd34 ADD	V23.2D, V23.2D, V4.2D

(181) 0x42cd38 B.NE	42ca40

0x42cd3c LDP	X14, X12, [SP, #24]

0x42cd40 LDR	X19, [SP, #64]

0x42cd44 FMINNMP	D4, V25.2D

0x42cd48 CMP	X12, X14

0x42cd4c LDR	W22, [SP, #60]

0x42cd50 LDP	X30, X25, [SP, #40]

0x42cd54 STR	D4, [SP, #120]

0x42cd58 B.EQ	42c808

0x42cd5c ADD	X8, X8, X14

0x42cd60 ADRP	X12,

0x42cd64 MOVI	D6, #0

0x42cd68 FMOV	D17, #-1.0000000

0x42cd6c SUB	W21, WZR, W25

0x42cd70 LDR	D5, [X12, #2744]

0x42cd74 ADRP	X12,

0x42cd78 LDR	D7, [X12, #2840]

0x42cd7c ADRP	X12,

0x42cd80 LDR	D16, [X12, #2848]

0x42cd84 B	42ce38

(183) 0x42cd88 MUL	X12, X30, X27

(183) 0x42cd8c ADD	X14, X11, X26

(183) 0x42cd90 LDR	D24, [X9, X26]

(183) 0x42cd94 LDR	D25, [X10, W28,SXTW #3]

(183) 0x42cd98 FABS	D18, D18

(183) 0x42cd9c FABS	D19, D19

(183) 0x42cda0 FABS	D21, D21

(183) 0x42cda4 FABS	D22, D22

(183) 0x42cda8 ADD	X8, X8, #1

(183) 0x42cdac LDR	D26, [X14, X12,LSL #3]

(183) 0x42cdb0 LDR	X12, [SP, #104]

(183) 0x42cdb4 ADD	X14, X13, X26

(183) 0x42cdb8 FMAXNM	D18, D18, D19

(183) 0x42cdbc FMUL	D19, D20, D5

(183) 0x42cdc0 FMAXNM	D21, D21, D22

(183) 0x42cdc4 FMAXNM	D18, D18, D19

(183) 0x42cdc8 FMAXNM	D19, D21, D19

(183) 0x42cdcc MUL	X12, X12, X27

(183) 0x42cdd0 FMINNM	D24, D24, D25

(183) 0x42cdd4 FMUL	D25, D1, D20

(183) 0x42cdd8 FMUL	D20, D20, D2

(183) 0x42cddc LDR	D27, [X14, X12,LSL #3]

(183) 0x42cde0 LDR	X12, [SP, #96]

(183) 0x42cde4 ADD	X14, X15, X26

(183) 0x42cde8 FMUL	D26, D26, D26

(183) 0x42cdec FMUL	D24, D24, D0

(183) 0x42cdf0 FDIV	D19, D20, D19

(183) 0x42cdf4 FDIV	D18, D25, D18

(183) 0x42cdf8 MUL	X12, X12, X27

(183) 0x42cdfc LDR	D28, [X14, X12,LSL #3]

(183) 0x42ce00 FADD	D27, D27, D27

(183) 0x42ce04 LDR	X12, [SP, #72]

(183) 0x42ce08 CMP	X12, X8

(183) 0x42ce0c FDIV	D27, D27, D28

(183) 0x42ce10 FMINNM	D19, D19, D23

(183) 0x42ce14 FMINNM	D18, D18, D19

(183) 0x42ce18 FADD	D26, D26, D27

(183) 0x42ce1c FSQRT	D26, D26

(183) 0x42ce20 FMAXNM	D26, D26, D5

(183) 0x42ce24 FDIV	D24, D24, D26

(183) 0x42ce28 FMINNM	D18, D24, D18

(183) 0x42ce2c FMINNM	D4, D18, D4

(183) 0x42ce30 STR	D4, [SP, #120]

(183) 0x42ce34 B.EQ	42c808

(183) 0x42ce38 SDIV	X12, X8, X25

(183) 0x42ce3c ADD	W14, W24, W8

(183) 0x42ce40 ADD	W28, W23, W12

(183) 0x42ce44 MADD	W12, W21, W12, W14

(183) 0x42ce48 ADD	W1, W28, #1

(183) 0x42ce4c SBFM	X27, X28, #0, #31

(183) 0x42ce50 ADD	W14, W12, #1

(183) 0x42ce54 SBFM	X1, X1, #0, #31

(183) 0x42ce58 ADD	W12, W12, #2

(183) 0x42ce5c SBFM	X26, X14, #61, #31

(183) 0x42ce60 MUL	X14, X18, X27

(183) 0x42ce64 MUL	X3, X18, X1

(183) 0x42ce68 SBFM	X12, X12, #61, #31

(183) 0x42ce6c ADD	X16, X17, X26

(183) 0x42ce70 ADD	X7, X0, X26

(183) 0x42ce74 LDR	D18, [X16, X14,LSL #3]

(183) 0x42ce78 LDR	D19, [X16, X3,LSL #3]

(183) 0x42ce7c LDR	X16, [SP, #88]

(183) 0x42ce80 MUL	X16, X16, X27

(183) 0x42ce84 FADD	D18, D18, D19

(183) 0x42ce88 LDR	D19, [X7, X16,LSL #3]

(183) 0x42ce8c ADD	X7, X17, X12

(183) 0x42ce90 LDR	D20, [X7, X3,LSL #3]

(183) 0x42ce94 ADD	X3, X6, X26

(183) 0x42ce98 FMUL	D18, D18, D19

(183) 0x42ce9c LDR	D19, [X7, X14,LSL #3]

(183) 0x42cea0 ADD	X14, X0, X12

(183) 0x42cea4 ADD	X12, X4, X12

(183) 0x42cea8 FADD	D19, D19, D20

(183) 0x42ceac LDR	D20, [X14, X16,LSL #3]

(183) 0x42ceb0 LDR	X14, [SP, #80]

(183) 0x42ceb4 ADD	X16, X2, X26

(183) 0x42ceb8 MUL	X14, X14, X27

(183) 0x42cebc FMUL	D19, D19, D20

(183) 0x42cec0 FADD	D20, D19, D6

(183) 0x42cec4 FSUB	D23, D20, S18

(183) 0x42cec8 LDR	D20, [X16, X14,LSL #3]

(183) 0x42cecc MUL	X14, X5, X27

(183) 0x42ced0 ADD	X16, X4, X26

(183) 0x42ced4 LDR	D21, [X16, X14,LSL #3]

(183) 0x42ced8 LDR	D22, [X12, X14,LSL #3]

(183) 0x42cedc MUL	X14, X20, X27

(183) 0x42cee0 FADD	D21, D21, D22

(183) 0x42cee4 LDR	D22, [X3, X14,LSL #3]

(183) 0x42cee8 MUL	X14, X5, X1

(183) 0x42ceec LDR	D24, [X12, X14,LSL #3]

(183) 0x42cef0 MUL	X12, X20, X1

(183) 0x42cef4 FMUL	D21, D21, D22

(183) 0x42cef8 LDR	D22, [X16, X14,LSL #3]

(183) 0x42cefc FADD	D22, D22, D24

(183) 0x42cf00 LDR	D24, [X3, X12,LSL #3]

(183) 0x42cf04 FMUL	D22, D22, D24

(183) 0x42cf08 FADD	D24, D20, D20

(183) 0x42cf0c FADD	D23, D23, D22

(183) 0x42cf10 FSUB	D23, D23, S21

(183) 0x42cf14 FDIV	D24, D23, D24

(183) 0x42cf18 FMOV	D23, D7

(183) 0x42cf1c FCMP	D24, D16

(183) 0x42cf20 B.PL	42cd88

(183) 0x42cf24 FDIV	D23, D17, D24

(183) 0x42cf28 FMUL	D23, D23, D3

(183) 0x42cf2c FMINNM	D23, D23, D7

(183) 0x42cf30 B	42cd88

0x42cf34 HINT	#0

0x42cf38 HINT	#0

0x42cf3c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	calc_dt_kernel(int, int, int, [...]	calc_dt.cpp:82	exec
○	calc_dt(global_variables&, int[...]	calc_dt.cpp:131	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:80	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.50 to 17.00 cycles (1.68x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 28.50 to 17.47 cycles (1.63x speedup).

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

14% of VPU loads are used in vector version.
18% of VPU stores are used in vector version.
20% of VPU addition or subtraction instructions are used in vector version.
5% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 18 bytes. The binary function is storing 38 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	210
nb uops	205
loop length	840
used w registers	15
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	18
used q registers	0
used v registers	20
used z registers	2
nb stack references	42

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.63 cycles
front end	25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.00	7.00	24.75	24.75	24.75	24.75	5.00	5.00	5.00	5.00	28.50	28.17	28.33	10.00	10.00
cycles	7.00	7.00	24.75	24.75	24.75	24.75	5.00	5.00	5.00	5.00	28.50	28.17	28.33	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.63
Dispatch	28.50
Overall L1	28.50

Vectorization ratios

INT

all	13%
load	14%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	12%
load	14%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	29%
load	27%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	28%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

INT+FP

all	29%
load	27%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.50 cycles. At this rate:

0% of peak load performance is reached (0.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42c730

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #63	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W24, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W23, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W27, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W8, W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W9, W27, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 42c960 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W22, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X19, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W9, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <47d7ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UMADDL X26, W25, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVN X8, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #132	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD X4, SP, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X26, XZR, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W1, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4101a0 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X9, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X7, X9, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 42c88c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <47d808>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1040	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X6, <47f81c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d820>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X5, 42c830 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x100>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #3904	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X6, #3936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42c930 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 42c960 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X2, <47f864>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d868>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D0, D0, D1, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR D0, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #3936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42c960 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X28, X26, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X2, X3, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVN X21, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X16, X17, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X5, X30, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X18, X1, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D2, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X12, X14, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FADD D1, D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D0, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X2, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X11, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X30, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADD D2, D2, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X20, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X7, X3, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X7, X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP X16, X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X1, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.CS 42c994 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D4, X21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X30, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42cd60 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X9, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
ADDVL SP, SP, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V25.2D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ X21, #35260	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INDEX Z17.D, #0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
DUP V7.2D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V21.2S, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
STR X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVK X21, #38872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X19, X7, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X12, X25, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W22, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STP X19, X7, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVK X21, #53938	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #15516	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V22.2S, W27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
AND X27, X7, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD V23.2D, V7.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
DUP V27.2D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ X21, #35260	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #38872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V7.2S, #1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
DUP V4.2D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #53938	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V5.2D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z4, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVK X21, #48284	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V6.2D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD V24.2S, V21.2S, V7.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
ADD V26.2S, V22.2S, V7.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
DUP V28.2D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V16.2D, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V30.2D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V31.2D, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V19.2D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V20.2D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, VL2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
DUP V29.2D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ X21, #61264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #55010	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #6884	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #17483	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V8.2D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
HINT #0																			N/A
LDP X14, X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMINNMP D4, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR W22, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP X30, X25, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR D4, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B.EQ 42c808 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X12, <451d60>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D17, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB W21, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X12, #2744]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X12, <451d74>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X12, #2840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X12, <451d7c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X12, #2848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 42ce38 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

14% of VPU loads are used in vector version.
18% of VPU stores are used in vector version.
20% of VPU addition or subtraction instructions are used in vector version.
5% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 18 bytes. The binary function is storing 38 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	210
nb uops	205
loop length	840
used w registers	15
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	18
used q registers	0
used v registers	20
used z registers	2
nb stack references	42

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.63 cycles
front end	25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.00	7.00	24.75	24.75	24.75	24.75	5.00	5.00	5.00	5.00	28.50	28.17	28.33	10.00	10.00
cycles	7.00	7.00	24.75	24.75	24.75	24.75	5.00	5.00	5.00	5.00	28.50	28.17	28.33	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.63
Dispatch	28.50
Overall L1	28.50

Vectorization ratios

INT

all	13%
load	14%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	12%
load	14%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	20%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Vector efficiency ratios

INT

all	29%
load	27%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	28%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

INT+FP

all	29%
load	27%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	21%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.50 cycles. At this rate:

0% of peak load performance is reached (0.63 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42c730

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #63	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W24, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W23, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W27, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W8, W8, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W9, W27, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 42c960 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W22, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR X19, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W9, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <47d7ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UMADDL X26, W25, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVN X8, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, SP, #132	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X10, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD X4, SP, #152	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X26, XZR, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR W1, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4101a0 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X9, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X7, X9, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X8, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X7, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 42c88c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <47d808>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1040	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X6, <47f81c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d820>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X5, 42c830 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x100>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #3904	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X6, #3936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42c930 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 42c960 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X2, <47f864>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d868>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1064	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FCMP D0, D1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
FCSEL D0, D0, D1, #4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (25.0%)
STR D0, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #3936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42c960 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x230>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X28, X26, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X2, X3, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X7, X7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVN X21, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X10, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X16, X17, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X5, X30, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X18, X1, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D2, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X12, X14, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FADD D1, D1, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D0, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X2, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D3, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X11, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X5, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X30, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FADD D2, D2, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X20, [X30]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X7, X3, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X7, X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X7, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STP X16, X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X1, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.CS 42c994 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D4, X21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X30, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42cd60 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x630>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X9, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
ADDVL SP, SP, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V25.2D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ X21, #35260	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INDEX Z17.D, #0, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
DUP V7.2D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V21.2S, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
STR X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVK X21, #38872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
AND X19, X7, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X12, X25, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W22, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STP X19, X7, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVK X21, #53938	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #15516	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V22.2S, W27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	vect (25.0%)
AND X27, X7, #0xfffffffe	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD V23.2D, V7.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
DUP V27.2D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ X21, #35260	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #38872	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI V7.2S, #1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (12.5%)
DUP V4.2D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #53938	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V5.2D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z4, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVK X21, #48284	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V6.2D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD V24.2S, V21.2S, V7.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
ADD V26.2S, V22.2S, V7.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (25.0%)
DUP V28.2D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V16.2D, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V30.2D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V31.2D, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V19.2D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP V20.2D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, VL2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
DUP V29.2D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MOVZ X21, #61264	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #55010	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #6884	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X21, #17483	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP V8.2D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
HINT #0																			N/A
LDP X14, X12, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMINNMP D4, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X12, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR W22, [SP, #60]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP X30, X25, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR D4, [SP, #120]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B.EQ 42c808 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X12, <451d60>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D17, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB W21, WZR, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D5, [X12, #2744]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X12, <451d74>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D7, [X12, #2840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X12, <451d7c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR D16, [X12, #2848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
B 42ce38 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x708>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D–	4.54	6.30
○Loop 181 - calc_dt.cpp:50-75 - exec	4.54	6.16
○Loop 182 - calc_dt.cpp:49-49 - exec	0.00	0.00
○Loop 183 - calc_dt.cpp:50-75 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code