OV - exec - Function field_summary(global_variables&, parallel_&) [clone .omp

	Function: field_summary(global_variables&, parallel_&) [clone .omp_outlined]	Module: exec	Source: field_summary.cpp:75-91 [...]	Coverage (incl. loops): 0.34% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp: 75 - 91

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75: #pragma omp parallel for simd reduction(+ : press) reduction(+ : ke) reduction(+ : ie) reduction(+ : mass) reduction(+ : vol)

76:     for (int idx = (0); idx < ((ymax - ymin + 1) * (xmax - xmin + 1)); idx++) {

77:       const int j = xmin + 1 + idx % (xmax - xmin + 1);

78:       const int k = ymin + 1 + idx / (xmax - xmin + 1);

79:       double vsqrd = 0.0;

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

83:         }

84:       }

85:       double cell_vol = field.volume(j, k);

86:       double cell_mass = cell_vol * field.density0(j, k);

87:       vol += cell_vol;

88:       mass += cell_mass;

89:       ie += cell_mass * field.energy0(j, k);

90:       ke += cell_mass * 0.5 * vsqrd;

91:       press += cell_vol * field.pressure(j, k);

0x42e0c0 STP	D15, D14, [SP, #864]!

0x42e0c4 STP	D13, D12, [SP, #16]

0x42e0c8 STP	D11, D10, [SP, #32]

0x42e0cc STP	D9, D8, [SP, #48]

0x42e0d0 STP	X29, X30, [SP, #64]

0x42e0d4 STP	X28, X27, [SP, #80]

0x42e0d8 STP	X26, X25, [SP, #96]

0x42e0dc STP	X24, X23, [SP, #112]

0x42e0e0 STP	X22, X21, [SP, #128]

0x42e0e4 STP	X20, X19, [SP, #144]

0x42e0e8 ADD	X29, SP, #64

0x42e0ec SUB	SP, SP, #128

0x42e0f0 ADDVL	SP, SP, #63

0x42e0f4 LDR	W8, [X2]

0x42e0f8 LDR	W9, [X3]

0x42e0fc LDR	W10, [X5]

0x42e100 SUB	W8, W8, W9

0x42e104 LDR	W9, [X4]

0x42e108 ADD	W8, W8, #1

0x42e10c SUB	W9, W9, W10

0x42e110 MADD	W8, W8, W9, W8

0x42e114 SUBS	W20, W8, #1

0x42e118 B.LT	42e700

0x42e11c LDR	W1, [X0]

0x42e120 LDP	X27, X28, [X29, #112]

0x42e124 ORR	X19, XZR, X7

0x42e128 ORR	X21, XZR, X6

0x42e12c ORR	X24, XZR, X5

0x42e130 ORR	X23, XZR, X4

0x42e134 ORR	X22, XZR, X3

0x42e138 LDP	X25, X26, [X29, #96]

0x42e13c MOVZ	W8, #1

0x42e140 ADRP	X0,

0x42e144 ADD	X0, X0, #1112

0x42e148 ADD	X3, SP, #112

0x42e14c ADD	X4, SP, #124

0x42e150 ADD	X5, SP, #120

0x42e154 ADD	X6, SP, #116

0x42e158 MOVZ	W2, #34

0x42e15c MOVZ	W7, #1

0x42e160 STP	W20, WZR, [SP, #120]

0x42e164 STP	WZR, W8, [SP, #112]

0x42e168 STP	XZR, XZR, [SP, #96]

0x42e16c STP	XZR, XZR, [SP, #80]

0x42e170 STR	XZR, [SP, #72]

0x42e174 STR	W8, [SP]

0x42e178 STR	W1, [SP, #28]

0x42e17c BL	410560

0x42e180 LDP	W8, W30, [SP, #120]

0x42e184 CMP	W8, W20

0x42e188 CSEL	W1, W8, W20, #11

0x42e18c CMP	W30, W1

0x42e190 STR	W1, [SP, #120]

0x42e194 B.GT	42e534

0x42e198 LDR	W3, [X24]

0x42e19c LDR	W4, [X23]

0x42e1a0 LDR	W5, [X22]

0x42e1a4 ADD	W1, W1, #1

0x42e1a8 MOVI	D20, #0

0x42e1ac MOVI	D1, #0

0x42e1b0 MOVI	D4, #0

0x42e1b4 MOVI	D5, #0

0x42e1b8 LDR	X8, [X21, #184]

0x42e1bc LDR	X9, [X21, #168]

0x42e1c0 LDR	X10, [X21, #232]

0x42e1c4 SUB	W6, W1, W30

0x42e1c8 MOVI	D6, #0

0x42e1cc MOVI	D3, #0

0x42e1d0 SUB	W4, W4, W3

0x42e1d4 LDR	X11, [X21, #216]

0x42e1d8 LDR	X12, [X21, #672]

0x42e1dc LDR	X13, [X21, #656]

0x42e1e0 LDR	X14, [X21, #16]

0x42e1e4 LDR	X15, [X21]

0x42e1e8 LDR	X16, [X21, #64]

0x42e1ec LDR	X17, [X21, #48]

0x42e1f0 LDR	X18, [X21, #112]

0x42e1f4 LDR	X0, [X21, #96]

0x42e1f8 CNTD	X21, ALL

0x42e1fc ADD	W2, W3, #1

0x42e200 ADD	W3, W5, #1

0x42e204 CMP	W6, W21

0x42e208 ORR	W5, WZR, W30

0x42e20c ADD	W4, W4, #1

0x42e210 B.CC	42e438

0x42e214 INDEX	Z16.D, X30, #1

0x42e218 MOVI	D2, #0

0x42e21c DUPM	Z20.D, #0x8000000000000000

0x42e220 SUB	W5, WZR, W21

0x42e224 FDUP	Z30.D, #80

0x42e228 AND	W7, W6, W5

0x42e22c SUB	X20, X29, #64

0x42e230 ADD	W5, W30, W7

0x42e234 PTRUE	P0.D, VL1

0x42e238 SEL	Z2.D, P0, Z2.D, Z20.D

0x42e23c ORR	W22, WZR, W7

0x42e240 ORR	Z21.D, Z2.D, Z2.D

0x42e244 DUP	Z0.D, X2

0x42e248 DUP	Z3.D, X4

0x42e24c ORR	Z22.D, Z2.D, Z2.D

0x42e250 ORR	Z20.D, Z2.D, Z2.D

0x42e254 ORR	Z25.D, Z2.D, Z2.D

0x42e258 STR	Z0, [X20, #511, MUL VL]

0x42e25c DUP	Z4.D, X3

0x42e260 DUP	Z29.D, X9

0x42e264 DUP	Z6.D, X11

0x42e268 DUP	Z7.D, X13

0x42e26c DUP	Z17.D, X15

0x42e270 DUP	Z18.D, X17

0x42e274 DUP	Z19.D, X0

0x42e278 DUP	Z23.D, X21

0x42e27c DUP	Z26.D, X8

0x42e280 DUP	Z28.D, X10

0x42e284 DUP	Z31.D, X12

0x42e288 DUP	Z8.D, X14

0x42e28c DUP	Z9.D, X16

0x42e290 DUP	Z10.D, X18

0x42e294 PTRUE	P0.D, ALL

0x42e298 MOVPRFX	Z24, Z3

0x42e29c SXTW	Z24.D, P0/M, Z3.D

(200) 0x42e2a0 MOVPRFX	Z11, Z16

(200) 0x42e2a4 SXTW	Z11.D, P0/M, Z16.D

(200) 0x42e2a8 SUB	X20, X29, #64

(200) 0x42e2ac DUP	Z5.D, #8

(200) 0x42e2b0 MOVI	V1.2D, #0

(200) 0x42e2b4 SUBS	W22, W22, W21

(200) 0x42e2b8 LDR	Z0, [X20, #511, MUL VL]

(200) 0x42e2bc SDIV	Z11.D, P0/M, Z11.D, Z24.D

(200) 0x42e2c0 MOVPRFX	Z13, Z16

(200) 0x42e2c4 MLS	Z13.D, P0/M, Z11.D, Z3.D

(200) 0x42e2c8 ADD	Z11.D, Z4.D, Z11.D

(200) 0x42e2cc ADD	Z16.D, Z16.D, Z23.D

(200) 0x42e2d0 MOVPRFX	Z12, Z11

(200) 0x42e2d4 SXTW	Z12.D, P0/M, Z11.D

(200) 0x42e2d8 MOVPRFX	Z15, Z6

(200) 0x42e2dc MUL	Z15.D, P0/M, Z15.D, Z12.D

(200) 0x42e2e0 ADD	Z11.D, Z0.D, Z13.D

(200) 0x42e2e4 MOVPRFX	Z13, Z29

(200) 0x42e2e8 MUL	Z13.D, P0/M, Z13.D, Z12.D

(200) 0x42e2ec ADR	Z27.D, [Z5, Z11.D,SXTW #3]

(200) 0x42e2f0 ADR	Z15.D, [Z28, Z15.D,LSL #3]

(200) 0x42e2f4 ADR	Z13.D, [Z26, Z13.D,LSL #3]

(200) 0x42e2f8 ADR	Z0.D, [Z15, Z11.D,SXTW #3]

(200) 0x42e2fc ADD	Z15.D, Z15.D, Z27.D

(200) 0x42e300 ADR	Z14.D, [Z13, Z11.D,SXTW #3]

(200) 0x42e304 ADD	Z13.D, Z13.D, Z27.D

(200) 0x42e308 LD1D	{Z0.D}, P0/Z, [V0.D]

(200) 0x42e30c LD1D	{Z15.D}, P0/Z, [V15.D]

(200) 0x42e310 LD1D	{Z14.D}, P0/Z, [V14.D]

(200) 0x42e314 LD1D	{Z13.D}, P0/Z, [V13.D]

(200) 0x42e318 FMUL	Z0.D, Z0.D, Z0.D

(200) 0x42e31c FMLA	Z0.D, P0/M, Z14.D, Z14.D

(200) 0x42e320 FMUL	Z14.D, Z15.D, Z15.D

(200) 0x42e324 ORR	Z15.D, Z12.D, Z12.D

(200) 0x42e328 ADD	Z15.D, Z15.D, #1

(200) 0x42e32c FMAD	Z0.D, P0/M, Z30.D, Z1.D

(200) 0x42e330 FMAD	Z13.D, P0/M, Z13.D, Z14.D

(200) 0x42e334 MOVPRFX	Z5, Z29

(200) 0x42e338 MUL	Z5.D, P0/M, Z5.D, Z15.D

(200) 0x42e33c MUL	Z15.D, P0/M, Z15.D, Z6.D

(200) 0x42e340 FMLA	Z0.D, P0/M, Z13.D, Z30.D

(200) 0x42e344 ADR	Z13.D, [Z28, Z15.D,LSL #3]

(200) 0x42e348 ADR	Z5.D, [Z26, Z5.D,LSL #3]

(200) 0x42e34c ADR	Z15.D, [Z13, Z11.D,SXTW #3]

(200) 0x42e350 ADR	Z14.D, [Z5, Z11.D,SXTW #3]

(200) 0x42e354 ADD	Z5.D, Z5.D, Z27.D

(200) 0x42e358 ADD	Z27.D, Z13.D, Z27.D

(200) 0x42e35c MOVPRFX	Z13, Z17

(200) 0x42e360 MUL	Z13.D, P0/M, Z13.D, Z12.D

(200) 0x42e364 LD1D	{Z15.D}, P0/Z, [V15.D]

(200) 0x42e368 FMUL	Z15.D, Z15.D, Z15.D

(200) 0x42e36c LD1D	{Z14.D}, P0/Z, [V14.D]

(200) 0x42e370 LD1D	{Z27.D}, P0/Z, [V27.D]

(200) 0x42e374 LD1D	{Z5.D}, P0/Z, [V5.D]

(200) 0x42e378 FMUL	Z27.D, Z27.D, Z27.D

(200) 0x42e37c FMAD	Z14.D, P0/M, Z14.D, Z15.D

(200) 0x42e380 MOVPRFX	Z15, Z7

(200) 0x42e384 MUL	Z15.D, P0/M, Z15.D, Z12.D

(200) 0x42e388 FMAD	Z5.D, P0/M, Z5.D, Z27.D

(200) 0x42e38c ADR	Z27.D, [Z31, Z11.D,SXTW #3]

(200) 0x42e390 FMLA	Z0.D, P0/M, Z14.D, Z30.D

(200) 0x42e394 ADR	Z14.D, [Z8, Z11.D,SXTW #3]

(200) 0x42e398 ADR	Z27.D, [Z27, Z15.D,LSL #3]

(200) 0x42e39c ADR	Z13.D, [Z14, Z13.D,LSL #3]

(200) 0x42e3a0 FMLA	Z0.D, P0/M, Z5.D, Z30.D

(200) 0x42e3a4 LD1D	{Z27.D}, P0/Z, [V27.D]

(200) 0x42e3a8 LD1D	{Z13.D}, P0/Z, [V13.D]

(200) 0x42e3ac FADD	Z2.D, Z27.D, Z2.D

(200) 0x42e3b0 FMUL	Z13.D, Z27.D, Z13.D

(200) 0x42e3b4 MOVPRFX	Z5, Z13

(200) 0x42e3b8 FMUL	Z5.D, P0/M, Z5.D, #0.0000000

(200) 0x42e3bc FADD	Z21.D, Z13.D, Z21.D

(200) 0x42e3c0 FMLA	Z20.D, P0/M, Z5.D, Z0.D

(200) 0x42e3c4 MOVPRFX	Z0, Z18

(200) 0x42e3c8 MUL	Z0.D, P0/M, Z0.D, Z12.D

(200) 0x42e3cc MUL	Z12.D, P0/M, Z12.D, Z19.D

(200) 0x42e3d0 ADR	Z5.D, [Z9, Z11.D,SXTW #3]

(200) 0x42e3d4 ADR	Z0.D, [Z5, Z0.D,LSL #3]

(200) 0x42e3d8 ADR	Z5.D, [Z10, Z11.D,SXTW #3]

(200) 0x42e3dc ADR	Z5.D, [Z5, Z12.D,LSL #3]

(200) 0x42e3e0 LD1D	{Z0.D}, P0/Z, [V0.D]

(200) 0x42e3e4 LD1D	{Z5.D}, P0/Z, [V5.D]

(200) 0x42e3e8 FMLA	Z22.D, P0/M, Z13.D, Z0.D

(200) 0x42e3ec FMLA	Z25.D, P0/M, Z27.D, Z5.D

(200) 0x42e3f0 B.NE	42e2a0

0x42e3f4 MOVZ	X20, #32768

0x42e3f8 CMP	W6, W7

0x42e3fc FMOV	D3, X20

0x42e400 ORR	Z1.D, Z3.D, Z3.D

0x42e404 ORR	Z4.D, Z3.D, Z3.D

0x42e408 ORR	Z5.D, Z3.D, Z3.D

0x42e40c ORR	Z6.D, Z3.D, Z3.D

0x42e410 FADDA	D3, P0, D3, Z25.D

0x42e414 FADDA	D1, P0, D1, Z2.D

0x42e418 STR	D3, [SP, #104]

0x42e41c FADDA	D4, P0, D4, Z21.D

0x42e420 FADDA	D5, P0, D5, Z22.D

0x42e424 STP	D1, D4, [SP, #72]

0x42e428 FADDA	D6, P0, D6, Z20.D

0x42e42c MOVI	D20, #0

0x42e430 STP	D5, D6, [SP, #88]

0x42e434 B.EQ	42e534

0x42e438 FMOV	D2, #0.2500000

0x42e43c FMOV	D7, #0.5000000

(199) 0x42e440 SDIV	W6, W5, W4

(199) 0x42e444 ADD	W7, W2, W5

(199) 0x42e448 ADD	W5, W5, #1

(199) 0x42e44c CMP	W1, W5

(199) 0x42e450 MSUB	W7, W4, W6, W7

(199) 0x42e454 ADD	W6, W3, W6

(199) 0x42e458 SBFM	X6, X6, #0, #31

(199) 0x42e45c MUL	X21, X11, X6

(199) 0x42e460 MUL	X20, X9, X6

(199) 0x42e464 SBFM	X7, X7, #61, #31

(199) 0x42e468 ADD	X22, X7, #8

(199) 0x42e46c ADD	X21, X10, X21,LSL #3

(199) 0x42e470 ADD	X20, X8, X20,LSL #3

(199) 0x42e474 LDR	D16, [X21, X7]

(199) 0x42e478 LDR	D0, [X20, X7]

(199) 0x42e47c LDR	D17, [X21, X22]

(199) 0x42e480 FMUL	D16, D16, D16

(199) 0x42e484 FMUL	D17, D17, D17

(199) 0x42e488 FMADD	D0, D0, D0, D16

(199) 0x42e48c LDR	D16, [X20, X22]

(199) 0x42e490 ADD	X20, X6, #1

(199) 0x42e494 MUL	X21, X9, X20

(199) 0x42e498 MUL	X20, X11, X20

(199) 0x42e49c ADD	X20, X10, X20,LSL #3

(199) 0x42e4a0 ADD	X21, X8, X21,LSL #3

(199) 0x42e4a4 LDR	D18, [X20, X7]

(199) 0x42e4a8 LDR	D19, [X20, X22]

(199) 0x42e4ac FMADD	D0, D0, D2, D20

(199) 0x42e4b0 MUL	X20, X13, X6

(199) 0x42e4b4 FMADD	D16, D16, D16, D17

(199) 0x42e4b8 LDR	D17, [X21, X7]

(199) 0x42e4bc FMUL	D18, D18, D18

(199) 0x42e4c0 FMADD	D0, D16, D2, D0

(199) 0x42e4c4 FMUL	D19, D19, D19

(199) 0x42e4c8 FMADD	D17, D17, D17, D18

(199) 0x42e4cc LDR	D18, [X21, X22]

(199) 0x42e4d0 ADD	X21, X12, X7

(199) 0x42e4d4 LDR	D16, [X21, X20,LSL #3]

(199) 0x42e4d8 MUL	X20, X15, X6

(199) 0x42e4dc ADD	X21, X14, X7

(199) 0x42e4e0 FMADD	D0, D17, D2, D0

(199) 0x42e4e4 FMADD	D18, D18, D18, D19

(199) 0x42e4e8 LDR	D19, [X21, X20,LSL #3]

(199) 0x42e4ec MUL	X20, X17, X6

(199) 0x42e4f0 ADD	X21, X16, X7

(199) 0x42e4f4 MUL	X6, X0, X6

(199) 0x42e4f8 ADD	X7, X18, X7

(199) 0x42e4fc FADD	D1, D16, D1

(199) 0x42e500 FMADD	D0, D18, D2, D0

(199) 0x42e504 FMUL	D19, D16, D19

(199) 0x42e508 FADD	D4, D19, D4

(199) 0x42e50c STP	D1, D4, [SP, #72]

(199) 0x42e510 LDR	D17, [X21, X20,LSL #3]

(199) 0x42e514 FMADD	D5, D19, D17, D5

(199) 0x42e518 FMUL	D17, D19, D7

(199) 0x42e51c FMADD	D6, D17, D0, D6

(199) 0x42e520 STP	D5, D6, [SP, #88]

(199) 0x42e524 LDR	D0, [X7, X6,LSL #3]

(199) 0x42e528 FMADD	D3, D16, D0, D3

(199) 0x42e52c STR	D3, [SP, #104]

(199) 0x42e530 B.NE	42e440

0x42e534 LDR	W20, [SP, #28]

0x42e538 ADRP	X0,

0x42e53c ADD	X0, X0, #1136

0x42e540 ORR	W1, WZR, W20

0x42e544 BL	410050

0x42e548 ADD	X8, SP, #104

0x42e54c ADD	X9, SP, #96

0x42e550 ADD	X10, SP, #88

0x42e554 ADRP	X6,

0x42e558 ORR	W1, WZR, W20

0x42e55c STP	X8, X9, [SP, #32]

0x42e560 ADD	X8, SP, #80

0x42e564 ADRP	X0,

0x42e568 ADD	X0, X0, #1160

0x42e56c ADRP	X5, 42e56c

0x42e570 ADD	X5, X5, #1856

0x42e574 STP	X10, X8, [SP, #48]

0x42e578 ADD	X8, SP, #72

0x42e57c ADD	X4, SP, #32

0x42e580 MOVZ	W2, #5

0x42e584 STR	X8, [SP, #64]

0x42e588 MOVZ	W3, #40

0x42e58c LDR	X6, [X6, #3936]

0x42e590 BL	410120

0x42e594 CMP	W0, #2

0x42e598 B.EQ	42e608

0x42e59c CMP	W0, #1

0x42e5a0 B.NE	42e700

0x42e5a4 LDR	D0, [X28]

0x42e5a8 LDP	D1, D2, [SP, #96]

0x42e5ac ADRP	X2,

0x42e5b0 ADRP	X0,

0x42e5b4 ADD	X0, X0, #1160

0x42e5b8 ORR	W1, WZR, W20

0x42e5bc FADD	D0, D0, D2

0x42e5c0 STR	D0, [X28]

0x42e5c4 LDR	D0, [X27]

0x42e5c8 FADD	D0, D0, D1

0x42e5cc LDP	D1, D2, [SP, #80]

0x42e5d0 STR	D0, [X27]

0x42e5d4 LDR	D0, [X26]

0x42e5d8 FADD	D0, D0, D2

0x42e5dc STR	D0, [X26]

0x42e5e0 LDR	D0, [X25]

0x42e5e4 FADD	D0, D0, D1

0x42e5e8 LDR	D1, [SP, #72]

0x42e5ec STR	D0, [X25]

0x42e5f0 LDR	D0, [X19]

0x42e5f4 FADD	D0, D0, D1

0x42e5f8 STR	D0, [X19]

0x42e5fc LDR	X2, [X2, #3936]

0x42e600 BL	4101f0

0x42e604 B	42e700

0x42e608 LDR	D0, [SP, #104]

0x42e60c LDR	D1, [X28]

0x42e610 HINT	#0

0x42e614 HINT	#0

0x42e618 HINT	#0

0x42e61c HINT	#0

(194) 0x42e620 FADD	D2, D1, D0

(194) 0x42e624 FMOV	X9, D1

(194) 0x42e628 ORR	X10, XZR, X9

(194) 0x42e62c FMOV	X8, D2

(194) 0x42e630 CAS	X10, X8, [X28]

(194) 0x42e634 FMOV	D1, X10

(194) 0x42e638 CMP	X10, X9

(194) 0x42e63c B.NE	42e620

0x42e640 LDR	D0, [SP, #96]

0x42e644 LDR	D1, [X27]

(195) 0x42e648 FADD	D2, D1, D0

(195) 0x42e64c FMOV	X9, D1

(195) 0x42e650 ORR	X10, XZR, X9

(195) 0x42e654 FMOV	X8, D2

(195) 0x42e658 CAS	X10, X8, [X27]

(195) 0x42e65c FMOV	D1, X10

(195) 0x42e660 CMP	X10, X9

(195) 0x42e664 B.NE	42e648

0x42e668 LDR	D0, [SP, #88]

0x42e66c LDR	D1, [X26]

0x42e670 HINT	#0

0x42e674 HINT	#0

0x42e678 HINT	#0

0x42e67c HINT	#0

(196) 0x42e680 FADD	D2, D1, D0

(196) 0x42e684 FMOV	X9, D1

(196) 0x42e688 ORR	X10, XZR, X9

(196) 0x42e68c FMOV	X8, D2

(196) 0x42e690 CAS	X10, X8, [X26]

(196) 0x42e694 FMOV	D1, X10

(196) 0x42e698 CMP	X10, X9

(196) 0x42e69c B.NE	42e680

0x42e6a0 LDR	D0, [SP, #80]

0x42e6a4 LDR	D1, [X25]

(197) 0x42e6a8 FADD	D2, D1, D0

(197) 0x42e6ac FMOV	X9, D1

(197) 0x42e6b0 ORR	X10, XZR, X9

(197) 0x42e6b4 FMOV	X8, D2

(197) 0x42e6b8 CAS	X10, X8, [X25]

(197) 0x42e6bc FMOV	D1, X10

(197) 0x42e6c0 CMP	X10, X9

(197) 0x42e6c4 B.NE	42e6a8

0x42e6c8 LDR	D0, [SP, #72]

0x42e6cc LDR	D1, [X19]

0x42e6d0 HINT	#0

0x42e6d4 HINT	#0

0x42e6d8 HINT	#0

0x42e6dc HINT	#0

(198) 0x42e6e0 FADD	D2, D1, D0

(198) 0x42e6e4 FMOV	X9, D1

(198) 0x42e6e8 ORR	X10, XZR, X9

(198) 0x42e6ec FMOV	X8, D2

(198) 0x42e6f0 CAS	X10, X8, [X19]

(198) 0x42e6f4 FMOV	D1, X10

(198) 0x42e6f8 CMP	X10, X9

(198) 0x42e6fc B.NE	42e6e0

0x42e700 ADDVL	SP, SP, #1

0x42e704 ADD	SP, SP, #128

0x42e708 LDP	D9, D8, [SP, #48]

0x42e70c LDP	D11, D10, [SP, #32]

0x42e710 LDP	D13, D12, [SP, #16]

0x42e714 LDP	X20, X19, [SP, #144]

0x42e718 LDP	X22, X21, [SP, #128]

0x42e71c LDP	X24, X23, [SP, #112]

0x42e720 LDP	X26, X25, [SP, #96]

0x42e724 LDP	X28, X27, [SP, #80]

0x42e728 LDP	X29, X30, [SP, #64]

0x42e72c LDP	D15, D14, [SP], #160

0x42e730 RET

0x42e734 HINT	#0

0x42e738 HINT	#0

0x42e73c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.42+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.27+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	field_summary(global_variables[...]	field_summary.cpp:66	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:105	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	field_summary.cpp:75-91
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75-91

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 28.00 to 20.00 cycles (1.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 36% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 28.00 to 17.41 cycles (1.61x speedup).

Details

20% of VPU instructions are used in vector version (process two or more data elements in vector registers):

15% of VPU loads are used in vector version.
23% of VPU stores are used in vector version.
26% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75

Matching between your function (in the source code) and the binary function

The binary function is composed of 25 FP arithmetical operations:

25: addition or subtraction

The binary function is loading 27 bytes. The binary function is storing 41 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	230
nb uops	215
loop length	920
used w registers	16
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	17
used q registers	0
used v registers	0
used z registers	26
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.88 cycles
front end	26.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	22.50	22.50	22.50	22.50	15.50	15.50	8.50	8.50	28.00	28.00	28.00	8.50	8.50
cycles	6.00	6.00	22.50	22.50	22.50	22.50	15.50	15.50	8.50	8.50	28.00	28.00	28.00	8.50	8.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	26.88
Dispatch	28.00
Overall L1	28.00

Vectorization ratios

INT

all	18%
load	15%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	21%

all	35%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	20%
load	15%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	26%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	35%
load	27%
store	39%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	19%
fma	12%
other	42%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

INT+FP

all	36%
load	27%
store	39%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	42%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.00 cycles. At this rate:

1% of peak load performance is reached (0.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.46 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42e0c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #63	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W9, W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MADD W8, W8, W9, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
SUBS W20, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 42e700 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP X27, X28, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X25, X26, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <47d140>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #124	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #116	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP W20, WZR, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP WZR, W8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP XZR, XZR, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP XZR, XZR, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410560 <@plt_start@+0x540>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W30, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W1, W8, W20, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W30, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR W1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.GT 42e534 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W3, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W4, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W5, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D4, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D5, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X8, [X21, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X21, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [X21, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W6, W1, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D3, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB W4, W4, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X21, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X21, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X21, #656]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X21, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X21, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W2, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W6, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ORR W5, WZR, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.CC 42e438 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z16.D, X30, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUPM Z20.D, #0x8000000000000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
SUB W5, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z30.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
AND W7, W6, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X20, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W30, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SEL Z2.D, P0, Z2.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR W22, WZR, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR Z21.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z3.D, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ORR Z22.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z20.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z25.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X20, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z29.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z7.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z17.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z18.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z19.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z23.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z26.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z28.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z31.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z8.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z9.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z10.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVPRFX Z24, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z24.D, P0/M, Z3.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVZ X20, #32768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W6, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
FMOV D3, X20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR Z1.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z4.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z5.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z6.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDA D3, P0, D3, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	8	1.50	vect (100.0%)
FADDA D1, P0, D1, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	8	1.50	vect (100.0%)
STR D3, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
FADDA D4, P0, D4, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	8	1.50	vect (100.0%)
FADDA D5, P0, D5, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	8	1.50	vect (100.0%)
STP D1, D4, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FADDA D6, P0, D6, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	8	1.50	vect (100.0%)
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D5, D6, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
B.EQ 42e534 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D2, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D7, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR W20, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <47d538>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, SP, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X6, <47f554>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X8, X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <47d564>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X5, 42e56c <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x4ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #1856	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X10, X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W3, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X6, #3936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42e608 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 42e700 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D1, D2, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADRP X2, <47f5ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d5b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
FADD D0, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X28]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP D1, D2, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
STR D0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X26]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D1, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D0, [X25]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #3936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42e700 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADDVL SP, SP, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	field_summary.cpp:75-91
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75-91

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

20% of VPU instructions are used in vector version (process two or more data elements in vector registers):

15% of VPU loads are used in vector version.
23% of VPU stores are used in vector version.
26% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:75

Matching between your function (in the source code) and the binary function

The binary function is composed of 25 FP arithmetical operations:

25: addition or subtraction

The binary function is loading 27 bytes. The binary function is storing 41 bytes.

Arithmetic intensity

Arithmetic intensity is 0.37 FP operations per loaded or stored byte.

General properties

nb instructions	230
nb uops	215
loop length	920
used w registers	16
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	17
used q registers	0
used v registers	0
used z registers	26
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.88 cycles
front end	26.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	22.50	22.50	22.50	22.50	15.50	15.50	8.50	8.50	28.00	28.00	28.00	8.50	8.50
cycles	6.00	6.00	22.50	22.50	22.50	22.50	15.50	15.50	8.50	8.50	28.00	28.00	28.00	8.50	8.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	26.88
Dispatch	28.00
Overall L1	28.00

Vectorization ratios

INT

all	18%
load	15%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	21%

all	35%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	20%
load	15%
store	23%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	26%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Vector efficiency ratios

INT

all	35%
load	27%
store	39%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	19%
fma	12%
other	42%

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	62%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

INT+FP

all	36%
load	27%
store	39%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	42%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 28.00 cycles. At this rate:

1% of peak load performance is reached (0.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.46 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42e0c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #63	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W8, W8, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W9, W9, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MADD W8, W8, W9, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
SUBS W20, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.LT 42e700 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDP X27, X28, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ORR X19, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X24, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X25, X26, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADRP X0, <47d140>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #124	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #120	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #116	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP W20, WZR, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP WZR, W8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP XZR, XZR, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP XZR, XZR, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR XZR, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410560 <@plt_start@+0x540>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W30, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W8, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W1, W8, W20, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W30, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
STR W1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
B.GT 42e534 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W3, [X24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W4, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W5, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D4, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D5, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X8, [X21, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X21, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [X21, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W6, W1, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVI D6, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MOVI D3, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUB W4, W4, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X11, [X21, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X21, #672]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X21, #656]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X21, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X21, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X21, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X21, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W2, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W3, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W6, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ORR W5, WZR, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B.CC 42e438 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x378>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z16.D, X30, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
MOVI D2, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUPM Z20.D, #0x8000000000000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
SUB W5, WZR, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FDUP Z30.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
AND W7, W6, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB X20, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W5, W30, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
PTRUE P0.D, VL1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
SEL Z2.D, P0, Z2.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR W22, WZR, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR Z21.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z3.D, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ORR Z22.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z20.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z25.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X20, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z29.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z7.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z17.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z18.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z19.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z23.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z26.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z28.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z31.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z8.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z9.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z10.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
MOVPRFX Z24, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z24.D, P0/M, Z3.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	2	1	vect (100.0%)
MOVZ X20, #32768	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W6, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
FMOV D3, X20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR Z1.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z4.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z5.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
ORR Z6.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FADDA D3, P0, D3, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	8	1.50	vect (100.0%)
FADDA D1, P0, D1, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	8	1.50	vect (100.0%)
STR D3, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
FADDA D4, P0, D4, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	8	1.50	vect (100.0%)
FADDA D5, P0, D5, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	8	1.50	vect (100.0%)
STP D1, D4, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
FADDA D6, P0, D6, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	8	1.50	vect (100.0%)
MOVI D20, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP D5, D6, [SP, #88]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
B.EQ 42e534 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D2, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMOV D7, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR W20, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <47d538>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1136	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, SP, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X6, <47f554>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X8, X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, SP, #80	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <47d564>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X5, 42e56c <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x4ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #1856	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X10, X8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MOVZ W3, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X6, #3936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410120 <@plt_start@+0x100>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42e608 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x548>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 42e700 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP D1, D2, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
ADRP X2, <47f5ac>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d5b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
FADD D0, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X28]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP D1, D2, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
STR D0, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D0, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X26]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D1, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
STR D0, [X25]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR D0, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
FADD D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #3936]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4101f0 <@plt_start@+0x1d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42e700 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDR D0, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X25]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D0, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADDVL SP, SP, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼field_summary(global_variables&, parallel_&) [clone .omp_outlined]–	0.34	0.47
○Loop 200 - field_summary.cpp:76-91 - exec	0.34	0.45
○Loop 194 - field_summary.cpp:75-75 - exec	0.00	0.00
○Loop 195 - field_summary.cpp:75-75 - exec	0.00	0.00
○Loop 199 - field_summary.cpp:76-91 - exec	0.00	0.00
○Loop 196 - field_summary.cpp:75-75 - exec	0.00	0.00
○Loop 198 - field_summary.cpp:75-75 - exec	0.00	0.00
○Loop 197 - field_summary.cpp:75-75 - exec	0.00	0.00

Report Configuration

Code clean check

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Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code