OV - exec - Function accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D< ...	Module: exec	Source: accelerate.cpp:40-53 [...]	Coverage (incl. loops): 7.15% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp: 40 - 53

--------------------------------------------------------------------------------

40: #pragma omp parallel for simd collapse(2)

41:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

42:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

43:       double stepbymass_s = halfdt / ((density0(i - 1, j - 1) * volume(i - 1, j - 1) + density0(i - 1, j + 0) * volume(i - 1, j + 0) +

44:                                        density0(i, j) * volume(i, j) + density0(i + 0, j - 1) * volume(i + 0, j - 1)) *

45:                                       0.25);

46:       xvel1(i, j) = xvel0(i, j) - stepbymass_s * (xarea(i, j) * (pressure(i, j) - pressure(i - 1, j + 0)) +

47:                                                   xarea(i + 0, j - 1) * (pressure(i + 0, j - 1) - pressure(i - 1, j - 1)));

48:       yvel1(i, j) = yvel0(i, j) - stepbymass_s * (yarea(i, j) * (pressure(i, j) - pressure(i + 0, j - 1)) +

49:                                                   yarea(i - 1, j + 0) * (pressure(i - 1, j + 0) - pressure(i - 1, j - 1)));

50:       xvel1(i, j) = xvel1(i, j) - stepbymass_s * (xarea(i, j) * (viscosity(i, j) - viscosity(i - 1, j + 0)) +

51:                                                   xarea(i + 0, j - 1) * (viscosity(i + 0, j - 1) - viscosity(i - 1, j - 1)));

52:       yvel1(i, j) = yvel1(i, j) - stepbymass_s * (yarea(i, j) * (viscosity(i, j) - viscosity(i + 0, j - 1)) +

53:                                                   yarea(i - 1, j + 0) * (viscosity(i - 1, j + 0) - viscosity(i - 1, j - 1)));

0x4272c0 STP	D15, D14, [SP, #864]!

0x4272c4 STP	D13, D12, [SP, #16]

0x4272c8 STP	D11, D10, [SP, #32]

0x4272cc STP	D9, D8, [SP, #48]

0x4272d0 STP	X29, X30, [SP, #64]

0x4272d4 STP	X28, X27, [SP, #80]

0x4272d8 STP	X26, X25, [SP, #96]

0x4272dc STP	X24, X23, [SP, #112]

0x4272e0 STP	X22, X21, [SP, #128]

0x4272e4 STP	X20, X19, [SP, #144]

0x4272e8 ADD	X29, SP, #64

0x4272ec SUB	SP, SP, #48

0x4272f0 ADDVL	SP, SP, #50

0x4272f4 LDR	W22, [X2]

0x4272f8 LDR	W8, [X3]

0x4272fc LDR	W23, [X4]

0x427300 ADD	W25, W22, #1

0x427304 LDR	W9, [X5]

0x427308 ADD	W8, W8, #3

0x42730c ADD	W24, W23, #1

0x427310 ADD	W9, W9, #3

0x427314 SUBS	W8, W8, W25

0x427318 CCMP	W9, W24, #4, #12

0x42731c B.LE	427750

0x427320 LDR	W20, [X0]

0x427324 SUB	W26, W9, W24

0x427328 MOVN	X9, #0

0x42732c ORR	X21, XZR, X7

0x427330 ORR	X19, XZR, X6

0x427334 ADRP	X0,

0x427338 ADD	X0, X0, #3024

0x42733c ORR	W1, WZR, W20

0x427340 UMADDL	X27, W26, W8, X9

0x427344 MOVZ	W8, #1

0x427348 ADD	X3, SP, #20

0x42734c ADD	X4, SP, #40

0x427350 ADD	X5, SP, #32

0x427354 ADD	X6, SP, #24

0x427358 MOVZ	W2, #34

0x42735c MOVZ	W7, #1

0x427360 STP	X27, XZR, [SP, #32]

0x427364 STR	X8, [SP, #24]

0x427368 STR	WZR, [SP, #20]

0x42736c STR	X8, [SP]

0x427370 BL	4101a0

0x427374 LDP	X8, X11, [SP, #32]

0x427378 CMP	X8, X27

0x42737c CSEL	X9, X8, X27, #11

0x427380 CMP	X11, X9

0x427384 STR	X9, [SP, #32]

0x427388 B.GT	427740

0x42738c CNTD	X8, ALL

0x427390 SUB	X9, X9, X11

0x427394 LDR	X1, [X21, #16]

0x427398 LDP	X16, X15, [X29, #120]

0x42739c LDP	X14, X13, [X29, #136]

0x4273a0 DUP	Z1.D, X25

0x4273a4 ADD	X18, X9, #1

0x4273a8 SUB	X25, X29, #64

0x4273ac LDP	X12, X10, [X29, #152]

0x4273b0 PTRUE	P1.D, ALL

0x4273b4 LDR	X0, [X29, #96]

0x4273b8 SUBS	X9, X18, X8

0x4273bc LD1RD	{Z19.D}, P1/Z, [X21]

0x4273c0 SUB	X21, X29, #64

0x4273c4 CSEL	X9, XZR, X9, #3

0x4273c8 WHILELO	P0.D, XZR, X18

0x4273cc LDP	X18, X17, [X29, #104]

0x4273d0 STR	Z1, [X25, #511, MUL VL]

0x4273d4 LDR	X4, [X16, #16]

0x4273d8 LD1RD	{Z6.D}, P1/Z, [X16]

0x4273dc SUB	X16, X29, #64

0x4273e0 LDR	X5, [X15, #16]

0x4273e4 LD1RD	{Z16.D}, P1/Z, [X15]

0x4273e8 DUP	Z1.D, X24

0x4273ec SUB	X15, X29, #64

0x4273f0 LDR	X7, [X13, #16]

0x4273f4 LDR	X27, [X10, #16]

0x4273f8 LD1RD	{Z22.D}, P1/Z, [X10]

0x4273fc DUP	Z0.D, X26

0x427400 LDR	X26, [X12, #16]

0x427404 SUB	X10, X29, #64

0x427408 LDR	X2, [X0, #16]

0x42740c LDR	X25, [X14, #16]

0x427410 DUP	Z25.D, X1

0x427414 LD1RD	{Z20.D}, P1/Z, [X0]

0x427418 STR	Z1, [X21, #510, MUL VL]

0x42741c LD1RD	{Z1.D}, P1/Z, [X17]

0x427420 INDEX	Z12.D, X11, #1

0x427424 LDR	X3, [X17, #16]

0x427428 SUB	X17, X29, #64

0x42742c LDR	X6, [X18, #16]

0x427430 STR	Z1, [X17, #509, MUL VL]

0x427434 DUP	Z1.D, X23

0x427438 DUP	Z26.D, X2

0x42743c DUP	Z30.D, X5

0x427440 DUP	Z9.D, X26

0x427444 STR	Z1, [X16, #508, MUL VL]

0x427448 LD1RD	{Z1.D}, P1/Z, [X18]

0x42744c DUP	Z10.D, X25

0x427450 DUP	Z11.D, X27

0x427454 STR	Z1, [X15, #507, MUL VL]

0x427458 LD1RD	{Z1.D}, P1/Z, [X13]

0x42745c SUB	X13, X29, #64

0x427460 STR	Z1, [X13, #506, MUL VL]

0x427464 DUP	Z1.D, X22

0x427468 STR	Z1, [X13, #505, MUL VL]

0x42746c LD1RD	{Z1.D}, P1/Z, [X12]

0x427470 SUB	X12, X29, #64

0x427474 STR	Z1, [X12, #504, MUL VL]

0x427478 LD1RD	{Z1.D}, P1/Z, [X14]

0x42747c STR	Z1, [X12, #503, MUL VL]

0x427480 DUP	Z1.D, X8

0x427484 STR	Z1, [X10, #502, MUL VL]

0x427488 DUP	Z1.D, X3

0x42748c SUB	X10, XZR, X8

0x427490 STR	Z1, [X12, #501, MUL VL]

0x427494 DUP	Z1.D, X4

0x427498 STR	Z1, [X12, #500, MUL VL]

0x42749c DUP	Z1.D, X6

0x4274a0 STR	Z1, [X12, #499, MUL VL]

0x4274a4 DUP	Z1.D, X7

0x4274a8 STR	Z1, [X12, #498, MUL VL]

(146) 0x4274ac DUP	Z1.D, #1

(146) 0x4274b0 SUB	X11, X29, #64

(146) 0x4274b4 ADD	X10, X10, X8

(146) 0x4274b8 LDR	Z2, [X11, #511, MUL VL]

(146) 0x4274bc LDR	Z21, [X11, #510, MUL VL]

(146) 0x4274c0 SEL	Z1.D, P0, Z0.D, Z1.D

(146) 0x4274c4 SDIVR	Z1.D, P1/M, Z1.D, Z12.D

(146) 0x4274c8 ADD	Z24.D, Z2.D, Z1.D

(146) 0x4274cc LDR	Z2, [X11, #508, MUL VL]

(146) 0x4274d0 MOVPRFX	Z27, Z12

(146) 0x4274d4 MLS	Z27.D, P1/M, Z1.D, Z0.D

(146) 0x4274d8 ADD	Z14.D, Z2.D, Z27.D

(146) 0x4274dc LDR	Z2, [X11, #505, MUL VL]

(146) 0x4274e0 ADR	Z3.D, [Z25, Z14.D,SXTW #3]

(146) 0x4274e4 ADR	Z17.D, [Z26, Z14.D,SXTW #3]

(146) 0x4274e8 ADD	Z1.D, Z2.D, Z1.D

(146) 0x4274ec MOVPRFX	Z13, Z1

(146) 0x4274f0 SXTW	Z13.D, P1/M, Z1.D

(146) 0x4274f4 MOVPRFX	Z1, Z19

(146) 0x4274f8 MUL	Z1.D, P1/M, Z1.D, Z13.D

(146) 0x4274fc MOVPRFX	Z4, Z20

(146) 0x427500 MUL	Z4.D, P1/M, Z4.D, Z13.D

(146) 0x427504 ADR	Z15.D, [Z3, Z1.D,LSL #3]

(146) 0x427508 LD1D	{Z5.D}, P0/Z, [V15.D]

(146) 0x42750c ADR	Z15.D, [Z17, Z4.D,LSL #3]

(146) 0x427510 LD1D	{Z18.D}, P0/Z, [V15.D]

(146) 0x427514 MOVPRFX	Z15, Z24

(146) 0x427518 SXTW	Z15.D, P1/M, Z24.D

(146) 0x42751c ADD	Z24.D, Z21.D, Z27.D

(146) 0x427520 MOVPRFX	Z2, Z19

(146) 0x427524 MUL	Z2.D, P1/M, Z2.D, Z15.D

(146) 0x427528 ADR	Z27.D, [Z25, Z24.D,SXTW #3]

(146) 0x42752c MOVPRFX	Z7, Z20

(146) 0x427530 MUL	Z7.D, P1/M, Z7.D, Z15.D

(146) 0x427534 ADR	Z21.D, [Z26, Z24.D,SXTW #3]

(146) 0x427538 ADR	Z23.D, [Z30, Z24.D,SXTW #3]

(146) 0x42753c ADR	Z1.D, [Z27, Z1.D,LSL #3]

(146) 0x427540 ADR	Z3.D, [Z3, Z2.D,LSL #3]

(146) 0x427544 ADR	Z2.D, [Z27, Z2.D,LSL #3]

(146) 0x427548 ADR	Z17.D, [Z17, Z7.D,LSL #3]

(146) 0x42754c ADR	Z7.D, [Z21, Z7.D,LSL #3]

(146) 0x427550 LD1D	{Z27.D}, P0/Z, [V1.D]

(146) 0x427554 ADR	Z1.D, [Z21, Z4.D,LSL #3]

(146) 0x427558 LDR	Z21, [X11, #501, MUL VL]

(146) 0x42755c ADR	Z21.D, [Z21, Z24.D,SXTW #3]

(146) 0x427560 LD1D	{Z4.D}, P0/Z, [V1.D]

(146) 0x427564 LDR	Z1, [X11, #509, MUL VL]

(146) 0x427568 MUL	Z1.D, P1/M, Z1.D, Z15.D

(146) 0x42756c ADR	Z1.D, [Z21, Z1.D,LSL #3]

(146) 0x427570 LD1D	{Z3.D}, P0/Z, [V3.D]

(146) 0x427574 LD1D	{Z17.D}, P0/Z, [V17.D]

(146) 0x427578 LD1D	{Z2.D}, P0/Z, [V2.D]

(146) 0x42757c LD1D	{Z7.D}, P0/Z, [V7.D]

(146) 0x427580 FMUL	Z3.D, Z3.D, Z17.D

(146) 0x427584 FMLA	Z3.D, P1/M, Z5.D, Z18.D

(146) 0x427588 ADR	Z5.D, [Z30, Z14.D,SXTW #3]

(146) 0x42758c LD1D	{Z21.D}, P0/Z, [V1.D]

(146) 0x427590 MOVPRFX	Z1, Z16

(146) 0x427594 MUL	Z1.D, P1/M, Z1.D, Z15.D

(146) 0x427598 FMAD	Z2.D, P1/M, Z7.D, Z3.D

(146) 0x42759c MOVPRFX	Z3, Z16

(146) 0x4275a0 MUL	Z3.D, P1/M, Z3.D, Z13.D

(146) 0x4275a4 ADR	Z28.D, [Z23, Z1.D,LSL #3]

(146) 0x4275a8 ADR	Z17.D, [Z5, Z1.D,LSL #3]

(146) 0x4275ac LDR	Z1, [X11, #500, MUL VL]

(146) 0x4275b0 FMLA	Z2.D, P1/M, Z27.D, Z4.D

(146) 0x4275b4 MOVPRFX	Z4, Z6

(146) 0x4275b8 MUL	Z4.D, P1/M, Z4.D, Z15.D

(146) 0x4275bc ADR	Z7.D, [Z23, Z3.D,LSL #3]

(146) 0x4275c0 ADR	Z3.D, [Z5, Z3.D,LSL #3]

(146) 0x4275c4 LD1D	{Z29.D}, P0/Z, [V28.D]

(146) 0x4275c8 ADR	Z31.D, [Z1, Z24.D,SXTW #3]

(146) 0x4275cc MOVPRFX	Z1, Z6

(146) 0x4275d0 MUL	Z1.D, P1/M, Z1.D, Z13.D

(146) 0x4275d4 ADR	Z4.D, [Z31, Z4.D,LSL #3]

(146) 0x4275d8 LD1D	{Z23.D}, P0/Z, [V7.D]

(146) 0x4275dc LD1D	{Z5.D}, P0/Z, [V3.D]

(146) 0x4275e0 LD1D	{Z18.D}, P0/Z, [V17.D]

(146) 0x4275e4 MUL	Z13.D, P1/M, Z13.D, Z22.D

(146) 0x4275e8 ADR	Z1.D, [Z31, Z1.D,LSL #3]

(146) 0x4275ec FSUB	Z18.D, Z29.D, Z18.D

(146) 0x4275f0 LD1D	{Z8.D}, P0/Z, [V1.D]

(146) 0x4275f4 FSUB	Z5.D, Z23.D, Z5.D

(146) 0x4275f8 FMUL	Z5.D, Z8.D, Z5.D

(146) 0x4275fc LD1D	{Z23.D}, P0/Z, [V4.D]

(146) 0x427600 FMLA	Z5.D, P1/M, Z23.D, Z18.D

(146) 0x427604 LDR	D18, [X19]

(146) 0x427608 FDUP	Z23.D, #80

(146) 0x42760c FMUL	Z2.D, Z2.D, Z23.D

(146) 0x427610 FNEG	D18, D18

(146) 0x427614 DUP	Z18.D, Z18.D[0]

(146) 0x427618 MOVPRFX	Z27, Z18

(146) 0x42761c FDIV	Z27.D, P1/M, Z27.D, Z2.D

(146) 0x427620 LDR	Z2, [X11, #507, MUL VL]

(146) 0x427624 LDR	Z18, [X11, #499, MUL VL]

(146) 0x427628 MUL	Z2.D, P1/M, Z2.D, Z15.D

(146) 0x42762c ADR	Z18.D, [Z18, Z24.D,SXTW #3]

(146) 0x427630 ADR	Z2.D, [Z18, Z2.D,LSL #3]

(146) 0x427634 FMAD	Z5.D, P1/M, Z27.D, Z21.D

(146) 0x427638 ADR	Z21.D, [Z9, Z24.D,SXTW #3]

(146) 0x42763c ST1D	{Z5.D}, P0, [V2.D]

(146) 0x427640 LDR	Z5, [X11, #506, MUL VL]

(146) 0x427644 LDR	Z18, [X11, #498, MUL VL]

(146) 0x427648 ADR	Z18.D, [Z18, Z24.D,SXTW #3]

(146) 0x42764c MUL	Z5.D, P1/M, Z5.D, Z15.D

(146) 0x427650 LD1D	{Z23.D}, P0/Z, [V28.D]

(146) 0x427654 ADR	Z5.D, [Z18, Z5.D,LSL #3]

(146) 0x427658 LDR	Z18, [X11, #504, MUL VL]

(146) 0x42765c LD1D	{Z7.D}, P0/Z, [V7.D]

(146) 0x427660 LD1D	{Z17.D}, P0/Z, [V17.D]

(146) 0x427664 LD1D	{Z3.D}, P0/Z, [V3.D]

(146) 0x427668 FSUB	Z7.D, Z23.D, Z7.D

(146) 0x42766c ADR	Z23.D, [Z9, Z14.D,SXTW #3]

(146) 0x427670 FSUB	Z3.D, Z17.D, Z3.D

(146) 0x427674 LD1D	{Z5.D}, P0/Z, [V5.D]

(146) 0x427678 MUL	Z18.D, P1/M, Z18.D, Z15.D

(146) 0x42767c ADR	Z21.D, [Z21, Z18.D,LSL #3]

(146) 0x427680 ADR	Z18.D, [Z23, Z18.D,LSL #3]

(146) 0x427684 LD1D	{Z17.D}, P0/Z, [V18.D]

(146) 0x427688 LD1D	{Z23.D}, P0/Z, [V21.D]

(146) 0x42768c FMUL	Z3.D, Z17.D, Z3.D

(146) 0x427690 FMLA	Z3.D, P1/M, Z23.D, Z7.D

(146) 0x427694 ADR	Z7.D, [Z10, Z24.D,SXTW #3]

(146) 0x427698 ADR	Z23.D, [Z11, Z14.D,SXTW #3]

(146) 0x42769c FMAD	Z3.D, P1/M, Z27.D, Z5.D

(146) 0x4276a0 LDR	Z5, [X11, #503, MUL VL]

(146) 0x4276a4 MUL	Z5.D, P1/M, Z5.D, Z15.D

(146) 0x4276a8 MUL	Z15.D, P1/M, Z15.D, Z22.D

(146) 0x4276ac ADR	Z5.D, [Z7, Z5.D,LSL #3]

(146) 0x4276b0 ST1D	{Z3.D}, P0, [V5.D]

(146) 0x4276b4 ADR	Z3.D, [Z11, Z24.D,SXTW #3]

(146) 0x4276b8 ADR	Z24.D, [Z23, Z15.D,LSL #3]

(146) 0x4276bc ADR	Z23.D, [Z23, Z13.D,LSL #3]

(146) 0x4276c0 LD1D	{Z1.D}, P0/Z, [V1.D]

(146) 0x4276c4 LD1D	{Z4.D}, P0/Z, [V4.D]

(146) 0x4276c8 ADR	Z7.D, [Z3, Z15.D,LSL #3]

(146) 0x4276cc ADR	Z3.D, [Z3, Z13.D,LSL #3]

(146) 0x4276d0 LD1D	{Z28.D}, P0/Z, [V24.D]

(146) 0x4276d4 LD1D	{Z31.D}, P0/Z, [V23.D]

(146) 0x4276d8 LD1D	{Z17.D}, P0/Z, [V7.D]

(146) 0x4276dc LD1D	{Z29.D}, P0/Z, [V3.D]

(146) 0x4276e0 FSUB	Z17.D, Z17.D, Z28.D

(146) 0x4276e4 FSUB	Z28.D, Z29.D, Z31.D

(146) 0x4276e8 FMUL	Z1.D, Z1.D, Z28.D

(146) 0x4276ec FMLA	Z1.D, P1/M, Z4.D, Z17.D

(146) 0x4276f0 LD1D	{Z4.D}, P0/Z, [V2.D]

(146) 0x4276f4 FMAD	Z1.D, P1/M, Z27.D, Z4.D

(146) 0x4276f8 ST1D	{Z1.D}, P0, [V2.D]

(146) 0x4276fc LD1D	{Z1.D}, P0/Z, [V7.D]

(146) 0x427700 LD1D	{Z2.D}, P0/Z, [V3.D]

(146) 0x427704 LD1D	{Z3.D}, P0/Z, [V24.D]

(146) 0x427708 LD1D	{Z4.D}, P0/Z, [V23.D]

(146) 0x42770c FSUB	Z1.D, Z1.D, Z2.D

(146) 0x427710 FSUB	Z2.D, Z3.D, Z4.D

(146) 0x427714 LD1D	{Z3.D}, P0/Z, [V18.D]

(146) 0x427718 FMUL	Z2.D, Z3.D, Z2.D

(146) 0x42771c LD1D	{Z4.D}, P0/Z, [V21.D]

(146) 0x427720 LD1D	{Z3.D}, P0/Z, [V5.D]

(146) 0x427724 FMAD	Z1.D, P1/M, Z4.D, Z2.D

(146) 0x427728 FMAD	Z1.D, P1/M, Z27.D, Z3.D

(146) 0x42772c ST1D	{Z1.D}, P0, [V5.D]

(146) 0x427730 WHILELO	P0.D, X10, X9

(146) 0x427734 LDR	Z1, [X11, #502, MUL VL]

(146) 0x427738 ADD	Z12.D, Z12.D, Z1.D

(146) 0x42773c B.MI	4274ac

0x427740 ADRP	X0,

0x427744 ADD	X0, X0, #3048

0x427748 ORR	W1, WZR, W20

0x42774c BL	410050

0x427750 ADDVL	SP, SP, #14

0x427754 ADD	SP, SP, #48

0x427758 LDP	D9, D8, [SP, #48]

0x42775c LDP	D11, D10, [SP, #32]

0x427760 LDP	D13, D12, [SP, #16]

0x427764 LDP	X20, X19, [SP, #144]

0x427768 LDP	X22, X21, [SP, #128]

0x42776c LDP	X24, X23, [SP, #112]

0x427770 LDP	X26, X25, [SP, #96]

0x427774 LDP	X28, X27, [SP, #80]

0x427778 LDP	X29, X30, [SP, #64]

0x42777c LDP	D15, D14, [SP], #160

0x427780 RET

0x427784 HINT	#0

0x427788 HINT	#0

0x42778c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.42+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	accelerate(global_variables&)	accelerate.cpp:66	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.50 to 19.00 cycles (1.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 39% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 23.50 to 13.94 cycles (1.69x speedup).

Details

23% of VPU instructions are used in vector version (process two or more data elements in vector registers):

14% of VPU loads are used in vector version.
62% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 451 bytes.

General properties

nb instructions	143
nb uops	140
loop length	572
used w registers	12
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	14
nb stack references	26

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.50 cycles
front end	17.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	15.50	15.25	22.00	15.25	4.75	4.75	4.75	4.75	23.50	23.17	23.33	5.50	5.50
cycles	2.50	2.50	15.50	15.25	22.00	15.25	4.75	4.75	4.75	4.75	23.50	23.17	23.33	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.50
Dispatch	23.50
Overall L1	23.50

Vectorization ratios

all	23%
load	14%
store	62%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	39%
load	29%
store	70%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	17%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (19.19 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4272c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #50	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W25, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W8, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W9, W24, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 427750 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W26, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <47c334>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3024	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UMADDL X27, W26, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X27, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101a0 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 427740 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X16, X15, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X14, X13, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
DUP Z1.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X18, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X25, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X12, X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X0, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X9, X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LD1RD {Z19.D}, P1/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X21, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X9, XZR, X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P0.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LDP X18, X17, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR Z1, [X25, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X4, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LD1RD {Z6.D}, P1/Z, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X16, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LD1RD {Z16.D}, P1/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z1.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X15, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X27, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LD1RD {Z22.D}, P1/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z0.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDR X26, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X10, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z25.D, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LD1RD {Z20.D}, P1/Z, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
STR Z1, [X21, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z1.D}, P1/Z, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
INDEX Z12.D, X11, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
LDR X3, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X17, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR Z1, [X17, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z26.D, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z30.D, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z9.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X16, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z1.D}, P1/Z, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z10.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z11.D, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X15, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z1.D}, P1/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X13, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z1, [X13, #506, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X13, #505, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z1.D}, P1/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z1, [X12, #504, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z1.D}, P1/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
STR Z1, [X12, #503, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X10, #502, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X10, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z1, [X12, #501, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X12, #500, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X12, #499, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X12, #498, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADRP X0, <47c740>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3048	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

23% of VPU instructions are used in vector version (process two or more data elements in vector registers):

14% of VPU loads are used in vector version.
62% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 451 bytes.

General properties

nb instructions	143
nb uops	140
loop length	572
used w registers	12
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	14
nb stack references	26

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.50 cycles
front end	17.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	15.50	15.25	22.00	15.25	4.75	4.75	4.75	4.75	23.50	23.17	23.33	5.50	5.50
cycles	2.50	2.50	15.50	15.25	22.00	15.25	4.75	4.75	4.75	4.75	23.50	23.17	23.33	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.50
Dispatch	23.50
Overall L1	23.50

Vectorization ratios

all	23%
load	14%
store	62%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	39%
load	29%
store	70%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	17%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.50 cycles. At this rate:

0% of peak load performance is reached (0.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (19.19 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4272c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #50	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W25, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W8, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W9, W24, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 427750 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x490>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W26, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X19, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADRP X0, <47c334>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3024	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UMADDL X27, W26, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X27, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 4101a0 <@plt_start@+0x180>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 427740 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X1, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X16, X15, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X14, X13, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
DUP Z1.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X18, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X25, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X12, X10, [X29, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X0, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X9, X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LD1RD {Z19.D}, P1/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X21, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X9, XZR, X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P0.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LDP X18, X17, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR Z1, [X25, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X4, [X16, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LD1RD {Z6.D}, P1/Z, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X16, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X5, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LD1RD {Z16.D}, P1/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z1.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X15, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X7, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X27, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LD1RD {Z22.D}, P1/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z0.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDR X26, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X10, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X2, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X25, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z25.D, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LD1RD {Z20.D}, P1/Z, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
STR Z1, [X21, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z1.D}, P1/Z, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
INDEX Z12.D, X11, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
LDR X3, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X17, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X18, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR Z1, [X17, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z26.D, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z30.D, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z9.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X16, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z1.D}, P1/Z, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z10.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z11.D, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X15, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z1.D}, P1/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X13, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z1, [X13, #506, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X13, #505, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z1.D}, P1/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z1, [X12, #504, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z1.D}, P1/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
STR Z1, [X12, #503, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X10, #502, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X10, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z1, [X12, #501, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X12, #500, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X12, #499, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z1.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z1, [X12, #498, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADRP X0, <47c740>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3048	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410050 <@plt_start@+0x30>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	7.15	9.93
○Loop 146 - accelerate.cpp:41-53 - exec	7.15	9.70

Report Configuration

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Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code