| Loop Id: 149 | Module: exec | Source: advec_cell.cpp:55-58 [...] | Coverage: 1.04% |
|---|
| Loop Id: 149 | Module: exec | Source: advec_cell.cpp:55-58 [...] | Coverage: 1.04% |
|---|
0x427ea0 SEL Z23.D, P1, Z4.D, Z17.D |
0x427ea4 ADD X10, X10, X8 |
0x427ea8 SDIVR Z23.D, P0/M, Z23.D, Z22.D |
0x427eac ADD Z24.D, Z5.D, Z23.D |
0x427eb0 MSB Z23.D, P0/M, Z4.D, Z22.D |
0x427eb4 ADD Z22.D, Z22.D, Z16.D |
0x427eb8 SXTW Z24.D, P0/M, Z24.D |
0x427ebc MOVPRFX Z26, Z0 |
0x427ec0 MUL Z26.D, P0/M, Z26.D, Z24.D |
0x427ec4 ADD Z25.D, Z6.D, Z23.D |
0x427ec8 ADD Z23.D, Z7.D, Z23.D |
0x427ecc ADR Z27.D, [Z18, Z25.D,SXTW #3] [11] |
0x427ed0 ADR Z23.D, [Z19, Z23.D,SXTW #3] [14] |
0x427ed4 ADR Z28.D, [Z19, Z25.D,SXTW #3] [14] |
0x427ed8 ADR Z26.D, [Z27, Z26.D,LSL #3] [10] |
0x427edc MOVPRFX Z27, Z1 |
0x427ee0 MUL Z27.D, P0/M, Z27.D, Z24.D |
0x427ee4 ADR Z23.D, [Z23, Z27.D,LSL #3] [4] |
0x427ee8 ADR Z27.D, [Z28, Z27.D,LSL #3] [13] |
0x427eec LD1D {Z28.D}, P1/Z, [V26.D] [7] |
0x427ef0 LD1D {Z23.D}, P1/Z, [V23.D] [3] |
0x427ef4 LD1D {Z27.D}, P1/Z, [V27.D] [9] |
0x427ef8 FADD Z23.D, Z28.D, Z23.D |
0x427efc ADR Z28.D, [Z20, Z25.D,SXTW #3] [1] |
0x427f00 ADR Z25.D, [Z21, Z25.D,SXTW #3] [2] |
0x427f04 FSUB Z23.D, Z23.D, Z27.D |
0x427f08 MOVPRFX Z27, Z2 |
0x427f0c MUL Z27.D, P0/M, Z27.D, Z24.D |
0x427f10 MUL Z24.D, P0/M, Z24.D, Z3.D |
0x427f14 ADR Z27.D, [Z28, Z27.D,LSL #3] [12] |
0x427f18 ADR Z24.D, [Z25, Z24.D,LSL #3] [6] |
0x427f1c ST1D {Z23.D}, P1, [V27.D] [8] |
0x427f20 LD1D {Z23.D}, P1/Z, [V26.D] [7] |
0x427f24 ST1D {Z23.D}, P1, [V24.D] [5] |
0x427f28 WHILELO P1.D, X10, X9 |
0x427f2c B.MI 427ea0 |
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 55 - 58 |
-------------------------------------------------------------------------------- |
55: for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) { |
56: for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) { |
57: pre_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j); |
58: post_vol(i, j) = volume(i, j); |
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.42+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_launch_thread | libomp.so | |
| ○ | __kmp_launch_worker(void*) | libomp.so | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 | |
| ►1.58+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_fork_call | libomp.so | |
| ○ | __kmpc_fork_call | libomp.so | |
| ○ | advec_cell_kernel(int, int, in[...] | advec_cell.cpp:54 | exec |
| ○ | advec_cell_driver(global_varia[...] | advec_cell.cpp:232 | exec |
| ○ | advection(global_variables&) | advection.cpp:81 | exec |
| ○ | hydro(global_variables&, paral[...] | basic_string.h:1077 | exec |
| ○ | main | clover_leaf.cpp:209 | exec |
| ○ | __libc_start_call_main | libc.so.6 | |
| ○ | __libc_start_main | libc.so.6 | |
| ○ | _start | ostream:93 | exec |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.38 - 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 3.00 - 1.48 |
| Bottlenecks | P6, P8, |
| Function | advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D |
| Source | advec_cell.cpp:55-58,context.h:69-69 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 13.50 - 20.00 |
| CQA cycles if no scalar integer | 13.50 - 20.00 |
| CQA cycles if FP arith vectorized | 13.50 - 20.00 |
| CQA cycles if fully vectorized | 9.75 - 20.00 |
| Front-end cycles | 4.50 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 0.50 |
| P3 cycles | 0.25 |
| P4 cycles | 1.00 |
| P5 cycles | 0.25 |
| P6 cycles | 13.50 |
| P7 cycles | 13.50 |
| P8 cycles | 3.00 |
| P9 cycles | 3.00 |
| P10 cycles | 2.00 |
| P11 cycles | 2.00 |
| P12 cycles | 2.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.87 - 20.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 36.00 |
| Nb uops | 36.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.59 - 0.40 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 9.66 - 14.31 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 129.25 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 10.00 |
| Stride indirect | 4.00 |
| Vectorization ratio all | 60.61 |
| Vectorization ratio load | 28.57 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 37.50 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 40.00 |
| Vector-efficiency ratio all | 77.27 |
| Vector-efficiency ratio load | 46.43 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 53.13 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 100.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.38 - 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 3.00 - 1.48 |
| Bottlenecks | P6, P8, |
| Function | advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D |
| Source | advec_cell.cpp:55-58,context.h:69-69 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 13.50 - 20.00 |
| CQA cycles if no scalar integer | 13.50 - 20.00 |
| CQA cycles if FP arith vectorized | 13.50 - 20.00 |
| CQA cycles if fully vectorized | 9.75 - 20.00 |
| Front-end cycles | 4.50 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 0.50 |
| P3 cycles | 0.25 |
| P4 cycles | 1.00 |
| P5 cycles | 0.25 |
| P6 cycles | 13.50 |
| P7 cycles | 13.50 |
| P8 cycles | 3.00 |
| P9 cycles | 3.00 |
| P10 cycles | 2.00 |
| P11 cycles | 2.00 |
| P12 cycles | 2.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 0.87 - 20.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 36.00 |
| Nb uops | 36.00 |
| Nb loads | NA |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.59 - 0.40 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 9.66 - 14.31 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 129.25 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 10.00 |
| Stride indirect | 4.00 |
| Vectorization ratio all | 60.61 |
| Vectorization ratio load | 28.57 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 37.50 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 40.00 |
| Vector-efficiency ratio all | 77.27 |
| Vector-efficiency ratio load | 46.43 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 53.13 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 100.00 |
| Path / |
| nb instructions | 36 |
| nb uops | 36 |
| loop length | 144 |
| used w registers | 0 |
| used x registers | 3 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 4 |
| used z registers | 21 |
| nb stack references | 0 |
| micro-operation queue | 4.50 cycles |
| front end | 4.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 13.50 | 13.50 | 3.00 | 3.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 13.50 | 13.50 | 3.00 | 3.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 0.87-20.00 |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 4.50 |
| Dispatch | 13.50 |
| DIV/SQRT | 0.87-20.00 |
| Data deps. | 2.00 |
| Overall L1 | 13.50-20.00 |
| all | 58% |
| load | 28% |
| store | 100% |
| mul | 100% |
| add-sub | 28% |
| fma | 100% |
| other | 50% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 60% |
| load | 28% |
| store | 100% |
| mul | 100% |
| add-sub | 37% |
| fma | 100% |
| div/sqrt | 100% |
| other | 40% |
| all | 75% |
| load | 46% |
| store | 100% |
| mul | 100% |
| add-sub | 46% |
| fma | 100% |
| other | 100% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 77% |
| load | 46% |
| store | 100% |
| mul | 100% |
| add-sub | 53% |
| fma | 100% |
| div/sqrt | 100% |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SEL Z23.D, P1, Z4.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADD X10, X10, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SDIVR Z23.D, P0/M, Z23.D, Z22.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-20 | 0.87-20 | vect (100.0%) |
| ADD Z24.D, Z5.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| MSB Z23.D, P0/M, Z4.D, Z22.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADD Z22.D, Z22.D, Z16.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| SXTW Z24.D, P0/M, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | vect (100.0%) |
| MOVPRFX Z26, Z0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z26.D, P0/M, Z26.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADD Z25.D, Z6.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADD Z23.D, Z7.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADR Z27.D, [Z18, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z23.D, [Z19, Z23.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z28.D, [Z19, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z26.D, [Z27, Z26.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| MOVPRFX Z27, Z1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z27.D, P0/M, Z27.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADR Z23.D, [Z23, Z27.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z27.D, [Z28, Z27.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LD1D {Z28.D}, P1/Z, [V26.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| LD1D {Z23.D}, P1/Z, [V23.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| LD1D {Z27.D}, P1/Z, [V27.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| FADD Z23.D, Z28.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADR Z28.D, [Z20, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z25.D, [Z21, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| FSUB Z23.D, Z23.D, Z27.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| MOVPRFX Z27, Z2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z27.D, P0/M, Z27.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| MUL Z24.D, P0/M, Z24.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADR Z27.D, [Z28, Z27.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z24.D, [Z25, Z24.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ST1D {Z23.D}, P1, [V27.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 | vect (100.0%) |
| LD1D {Z23.D}, P1/Z, [V26.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| ST1D {Z23.D}, P1, [V24.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 | vect (100.0%) |
| WHILELO P1.D, X10, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 427ea0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.1+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| nb instructions | 36 |
| nb uops | 36 |
| loop length | 144 |
| used w registers | 0 |
| used x registers | 3 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 4 |
| used z registers | 21 |
| nb stack references | 0 |
| micro-operation queue | 4.50 cycles |
| front end | 4.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 13.50 | 13.50 | 3.00 | 3.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 13.50 | 13.50 | 3.00 | 3.00 | 2.00 | 2.00 | 2.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 0.87-20.00 |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 4.50 |
| Dispatch | 13.50 |
| DIV/SQRT | 0.87-20.00 |
| Data deps. | 2.00 |
| Overall L1 | 13.50-20.00 |
| all | 58% |
| load | 28% |
| store | 100% |
| mul | 100% |
| add-sub | 28% |
| fma | 100% |
| other | 50% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 60% |
| load | 28% |
| store | 100% |
| mul | 100% |
| add-sub | 37% |
| fma | 100% |
| div/sqrt | 100% |
| other | 40% |
| all | 75% |
| load | 46% |
| store | 100% |
| mul | 100% |
| add-sub | 46% |
| fma | 100% |
| other | 100% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 77% |
| load | 46% |
| store | 100% |
| mul | 100% |
| add-sub | 53% |
| fma | 100% |
| div/sqrt | 100% |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SEL Z23.D, P1, Z4.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADD X10, X10, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SDIVR Z23.D, P0/M, Z23.D, Z22.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-20 | 0.87-20 | vect (100.0%) |
| ADD Z24.D, Z5.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| MSB Z23.D, P0/M, Z4.D, Z22.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADD Z22.D, Z22.D, Z16.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| SXTW Z24.D, P0/M, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | vect (100.0%) |
| MOVPRFX Z26, Z0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z26.D, P0/M, Z26.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADD Z25.D, Z6.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADD Z23.D, Z7.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADR Z27.D, [Z18, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z23.D, [Z19, Z23.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z28.D, [Z19, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z26.D, [Z27, Z26.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| MOVPRFX Z27, Z1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z27.D, P0/M, Z27.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADR Z23.D, [Z23, Z27.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z27.D, [Z28, Z27.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LD1D {Z28.D}, P1/Z, [V26.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| LD1D {Z23.D}, P1/Z, [V23.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| LD1D {Z27.D}, P1/Z, [V27.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| FADD Z23.D, Z28.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADR Z28.D, [Z20, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z25.D, [Z21, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| FSUB Z23.D, Z23.D, Z27.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| MOVPRFX Z27, Z2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z27.D, P0/M, Z27.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| MUL Z24.D, P0/M, Z24.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADR Z27.D, [Z28, Z27.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z24.D, [Z25, Z24.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ST1D {Z23.D}, P1, [V27.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 | vect (100.0%) |
| LD1D {Z23.D}, P1/Z, [V26.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| ST1D {Z23.D}, P1, [V24.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 | vect (100.0%) |
| WHILELO P1.D, X10, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 427ea0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.1+0x130> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |