OV - exec - Loop 162

	Loop Id: 162	Module: exec	Source: advec_mom.cpp:109-139 [...]	Coverage: 3.60%

0x42a260 SEL	Z26.D, P1, Z4.D, Z16.D

0x42a264 ADD	X11, X11, X8

0x42a268 SDIVR	Z26.D, P0/M, Z26.D, Z25.D

0x42a26c ADD	Z27.D, Z5.D, Z26.D

0x42a270 MSB	Z26.D, P0/M, Z4.D, Z25.D

0x42a274 ADD	Z25.D, Z25.D, Z7.D

0x42a278 SXTW	Z27.D, P0/M, Z27.D

0x42a27c MOVPRFX	Z29, Z0

0x42a280 MUL	Z29.D, P0/M, Z29.D, Z27.D

0x42a284 ADD	Z26.D, Z6.D, Z26.D

0x42a288 ADR	Z30.D, [Z17, Z26.D,SXTW #3]    [14]

0x42a28c ORR	Z9.D, Z26.D, Z26.D

0x42a290 MOVPRFX	Z28, Z26

0x42a294 SXTW	Z28.D, P0/M, Z26.D

0x42a298 ADD	Z8.D, Z26.D, Z19.D

0x42a29c ADR	Z29.D, [Z30, Z29.D,LSL #3]    [3]

0x42a2a0 ORR	Z30.D, Z26.D, Z26.D

0x42a2a4 ADD	Z9.D, Z9.D, #2

0x42a2a8 LD1D	{Z29.D}, P1/Z, [V29.D]    [17]

0x42a2ac ADD	Z30.D, Z30.D, #1

0x42a2b0 MOVPRFX	Z31, Z30

0x42a2b4 SXTW	Z31.D, P0/M, Z30.D

0x42a2b8 FCMLT	P2.D, P0/Z, Z29.D, #0.0000000

0x42a2bc MOVPRFX	Z11, Z29

0x42a2c0 FABS	Z11.D, P0/M, Z29.D

0x42a2c4 SEL	Z10.D, P2, Z28.D, Z31.D

0x42a2c8 SEL	Z28.D, P2, Z31.D, Z28.D

0x42a2cc SEL	Z30.D, P2, Z30.D, Z8.D

0x42a2d0 SEL	Z31.D, P2, Z9.D, Z8.D

0x42a2d4 MOVPRFX	Z8, Z1

0x42a2d8 MUL	Z8.D, P0/M, Z8.D, Z27.D

0x42a2dc ADR	Z9.D, [Z20, Z28.D,LSL #3]    [2]

0x42a2e0 ADR	Z28.D, [Z21, Z28.D,LSL #3]    [4]

0x42a2e4 ADR	Z31.D, [Z21, Z31.D,SXTW #3]    [4]

0x42a2e8 ADR	Z10.D, [Z21, Z10.D,LSL #3]    [4]

0x42a2ec ADR	Z8.D, [Z9, Z8.D,LSL #3]    [10]

0x42a2f0 MOVPRFX	Z9, Z2

0x42a2f4 MUL	Z9.D, P0/M, Z9.D, Z27.D

0x42a2f8 MUL	Z27.D, P0/M, Z27.D, Z3.D

0x42a2fc ADR	Z28.D, [Z28, Z9.D,LSL #3]    [16]

0x42a300 ADR	Z31.D, [Z31, Z9.D,LSL #3]    [6]

0x42a304 LD1D	{Z8.D}, P1/Z, [V8.D]    [7]

0x42a308 ADR	Z9.D, [Z10, Z9.D,LSL #3]    [1]

0x42a30c FDIVR	Z8.D, P0/M, Z8.D, Z11.D

0x42a310 MOVPRFX	Z12, Z8

0x42a314 FADD	Z12.D, P0/M, Z12.D, #0.0000000

0x42a318 LD1D	{Z28.D}, P1/Z, [V28.D]    [15]

0x42a31c LD1D	{Z31.D}, P1/Z, [V31.D]    [5]

0x42a320 LD1D	{Z9.D}, P1/Z, [V9.D]    [9]

0x42a324 FSUB	Z31.D, Z28.D, Z31.D

0x42a328 FSUB	Z9.D, Z9.D, Z28.D

0x42a32c FMUL	Z10.D, Z31.D, Z9.D

0x42a330 FCMGT	P3.D, P0/Z, Z10.D, #0.0000000

0x42a334 AND	P4.B, P1/Z, P1.B, P3.B

0x42a338 LD1D	{Z10.D}, P4/Z, [X9, Z26.D,SXTW #3]    [8]

0x42a33c FABS	Z31.D, P0/M, Z31.D

0x42a340 MOVPRFX	Z11, Z9

0x42a344 FABS	Z11.D, P0/M, Z9.D

0x42a348 FCMLE	P2.D, P0/Z, Z9.D, #0.0000000

0x42a34c LD1D	{Z30.D}, P4/Z, [X9, Z30.D,SXTW #3]    [8]

0x42a350 FSUB	Z9.D, Z22.D, Z8.D

0x42a354 FSUBR	Z8.D, P0/M, Z8.D, #0.0000000

0x42a358 ADR	Z26.D, [Z24, Z26.D,SXTW #3]    [11]

0x42a35c ADR	Z26.D, [Z26, Z27.D,LSL #3]    [13]

0x42a360 FMUL	Z9.D, Z9.D, Z11.D

0x42a364 FMUL	Z12.D, Z12.D, Z31.D

0x42a368 FDIV	Z9.D, P0/M, Z9.D, Z10.D

0x42a36c FDIVR	Z30.D, P0/M, Z30.D, Z12.D

0x42a370 FADD	Z30.D, Z9.D, Z30.D

0x42a374 FMUL	Z30.D, Z10.D, Z30.D

0x42a378 FDIV	Z30.D, P0/M, Z30.D, Z23.D

0x42a37c FMINNM	Z30.D, P0/M, Z30.D, Z31.D

0x42a380 FMINNM	Z30.D, P0/M, Z30.D, Z11.D

0x42a384 FNEG	Z30.D, P2/M, Z30.D

0x42a388 SEL	Z30.D, P3, Z30.D, Z18.D

0x42a38c FMLA	Z28.D, P0/M, Z8.D, Z30.D

0x42a390 FMUL	Z28.D, Z29.D, Z28.D

0x42a394 ST1D	{Z28.D}, P1, [V26.D]    [12]

0x42a398 WHILELO	P1.D, X11, X10

0x42a39c B.MI	42a260

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 109 - 139

--------------------------------------------------------------------------------

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

Coverage (%)	Name	Module
►98.41+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.15 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.25
Bottlenecks	P6, P8,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.11]
Source	context.h:69-69,advec_mom.cpp:109-139
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	34.00 - 76.34
CQA cycles if no scalar integer	34.00 - 76.34
CQA cycles if FP arith vectorized	34.00 - 76.34
CQA cycles if fully vectorized	29.50 - 76.34
Front-end cycles	10.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	2.00
P5 cycles	0.25
P6 cycles	34.00
P7 cycles	34.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	2.83
P11 cycles	2.50
P12 cycles	2.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	28.85 - 76.34
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	80.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.00 - 0.89
Nb FLOP add-sub	24.00
Nb FLOP mul	20.00
Nb FLOP fma	4.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.37 - 7.57
Bytes prefetched	0.00
Bytes loaded	225.50
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	5.00
Vectorization ratio all	74.03
Vectorization ratio load	36.84
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	72.41
Vector-efficiency ratio all	87.18
Vector-efficiency ratio load	52.63
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	96.98

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.15 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.25
Bottlenecks	P6, P8,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.11]
Source	context.h:69-69,advec_mom.cpp:109-139
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	34.00 - 76.34
CQA cycles if no scalar integer	34.00 - 76.34
CQA cycles if FP arith vectorized	34.00 - 76.34
CQA cycles if fully vectorized	29.50 - 76.34
Front-end cycles	10.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	2.00
P5 cycles	0.25
P6 cycles	34.00
P7 cycles	34.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	2.83
P11 cycles	2.50
P12 cycles	2.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	28.85 - 76.34
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	80.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.00 - 0.89
Nb FLOP add-sub	24.00
Nb FLOP mul	20.00
Nb FLOP fma	4.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.37 - 7.57
Bytes prefetched	0.00
Bytes loaded	225.50
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	12.00
Stride indirect	5.00
Vectorization ratio all	74.03
Vectorization ratio load	36.84
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	50.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	72.41
Vector-efficiency ratio all	87.18
Vector-efficiency ratio load	52.63
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	96.98

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.11]
Source file and lines	advec_mom.cpp:109-139
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-139

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 87% of vector register length is used (average across all VPU instructions).

Details

74% of VPU instructions are used in vector version (process two or more data elements in vector registers):

36% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
72% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 76.34 to 31.50 cycles (2.42x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 12 occurrence(s)
Irregular (variable stride) or indirect: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (4 inside FMA instructions)
24: multiply (4 inside FMA instructions)
16: divide

The binary loop is loading 225 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	80
nb uops	80
loop length	320
used w registers	0
used x registers	4
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	6
used z registers	29
nb stack references	0
ADD-SUB / MUL ratio	1.20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.00 cycles
front end	10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	34.00	34.00	3.00	3.00	2.83	2.50	2.67	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	34.00	34.00	6.00	6.00	2.83	2.50	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	28.85-76.34
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	10.00
Dispatch	34.00
DIV/SQRT	28.85-76.34
Data deps.	2.00
Overall L1	34.00-76.34

Vectorization ratios

INT

all	61%
load	36%
store	100%
mul	100%
add-sub	33%
fma	100%
other	61%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	74%
load	36%
store	100%
mul	100%
add-sub	50%
fma	100%
div/sqrt	100%
other	72%

Vector efficiency ratios

INT

all	81%
load	52%
store	100%
mul	100%
add-sub	50%
fma	100%
other	95%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	87%
load	52%
store	100%
mul	100%
add-sub	62%
fma	100%
div/sqrt	100%
other	96%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 76.34 cycles. At this rate:

3% of peak load performance is reached (2.95 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.42 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42a260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z26.D, P1, Z4.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X11, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z26.D, P0/M, Z26.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z27.D, Z5.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MSB Z26.D, P0/M, Z4.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z25.D, Z25.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z27.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z29, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z29.D, P0/M, Z29.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z26.D, Z6.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z30.D, [Z17, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ORR Z9.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z28, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z28.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADD Z8.D, Z26.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z29.D, [Z30, Z29.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ORR Z30.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z9.D, Z9.D, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z29.D}, P1/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z30.D, Z30.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z31, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z31.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P2.D, P0/Z, Z29.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z11, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z11.D, P0/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z10.D, P2, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z28.D, P2, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z30.D, P2, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z31.D, P2, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z8, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z8.D, P0/M, Z8.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z9.D, [Z20, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z28.D, [Z21, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z21, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z21, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z9, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z9, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z9.D, P0/M, Z9.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z27.D, P0/M, Z27.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z28.D, [Z28, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z31, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z8.D}, P1/Z, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z9.D, [Z10, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FDIVR Z8.D, P0/M, Z8.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z12, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FADD Z12.D, P0/M, Z12.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z28.D}, P1/Z, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z31.D}, P1/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z9.D}, P1/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z31.D, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z9.D, Z9.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z10.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMGT P3.D, P0/Z, Z10.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
AND P4.B, P1/Z, P1.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z10.D}, P4/Z, [X9, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FABS Z31.D, P0/M, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z11, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z11.D, P0/M, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCMLE P2.D, P0/Z, Z9.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z30.D}, P4/Z, [X9, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z9.D, Z22.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z8.D, P0/M, Z8.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z26.D, [Z24, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z26, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z9.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z12.D, Z12.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z9.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z30.D, P0/M, Z30.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z30.D, Z9.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z30.D, Z10.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z30.D, P0/M, Z30.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMINNM Z30.D, P0/M, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z30.D, P0/M, Z30.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FNEG Z30.D, P2/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z30.D, P3, Z30.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z28.D, P0/M, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z28.D, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z28.D}, P1, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 42a260 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.11+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.11]
Source file and lines	advec_mom.cpp:109-139
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-139

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 87% of vector register length is used (average across all VPU instructions).

Details

74% of VPU instructions are used in vector version (process two or more data elements in vector registers):

36% of VPU loads are used in vector version.
50% of VPU addition or subtraction instructions are used in vector version.
72% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 76.34 to 31.50 cycles (2.42x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 12 occurrence(s)
Irregular (variable stride) or indirect: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (4 inside FMA instructions)
24: multiply (4 inside FMA instructions)
16: divide

The binary loop is loading 225 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	80
nb uops	80
loop length	320
used w registers	0
used x registers	4
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	6
used z registers	29
nb stack references	0
ADD-SUB / MUL ratio	1.20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.00 cycles
front end	10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	34.00	34.00	3.00	3.00	2.83	2.50	2.67	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	34.00	34.00	6.00	6.00	2.83	2.50	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	28.85-76.34
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	10.00
Dispatch	34.00
DIV/SQRT	28.85-76.34
Data deps.	2.00
Overall L1	34.00-76.34

Vectorization ratios

INT

all	61%
load	36%
store	100%
mul	100%
add-sub	33%
fma	100%
other	61%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	74%
load	36%
store	100%
mul	100%
add-sub	50%
fma	100%
div/sqrt	100%
other	72%

Vector efficiency ratios

INT

all	81%
load	52%
store	100%
mul	100%
add-sub	50%
fma	100%
other	95%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	87%
load	52%
store	100%
mul	100%
add-sub	62%
fma	100%
div/sqrt	100%
other	96%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 76.34 cycles. At this rate:

3% of peak load performance is reached (2.95 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.42 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42a260

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z26.D, P1, Z4.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X11, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z26.D, P0/M, Z26.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z27.D, Z5.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MSB Z26.D, P0/M, Z4.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z25.D, Z25.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z27.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z29, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z29.D, P0/M, Z29.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z26.D, Z6.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z30.D, [Z17, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ORR Z9.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z28, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z28.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADD Z8.D, Z26.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z29.D, [Z30, Z29.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ORR Z30.D, Z26.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z9.D, Z9.D, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z29.D}, P1/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z30.D, Z30.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z31, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z31.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P2.D, P0/Z, Z29.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z11, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z11.D, P0/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z10.D, P2, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z28.D, P2, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z30.D, P2, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z31.D, P2, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z8, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z8.D, P0/M, Z8.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z9.D, [Z20, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z28.D, [Z21, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z21, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z21, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z9, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z9, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z9.D, P0/M, Z9.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z27.D, P0/M, Z27.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z28.D, [Z28, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z31, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z8.D}, P1/Z, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z9.D, [Z10, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FDIVR Z8.D, P0/M, Z8.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z12, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FADD Z12.D, P0/M, Z12.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z28.D}, P1/Z, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z31.D}, P1/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z9.D}, P1/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z31.D, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z9.D, Z9.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z10.D, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMGT P3.D, P0/Z, Z10.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
AND P4.B, P1/Z, P1.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z10.D}, P4/Z, [X9, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FABS Z31.D, P0/M, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z11, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z11.D, P0/M, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCMLE P2.D, P0/Z, Z9.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z30.D}, P4/Z, [X9, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z9.D, Z22.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z8.D, P0/M, Z8.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z26.D, [Z24, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z26, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z9.D, Z9.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z12.D, Z12.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z9.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z30.D, P0/M, Z30.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z30.D, Z9.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z30.D, Z10.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z30.D, P0/M, Z30.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMINNM Z30.D, P0/M, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z30.D, P0/M, Z30.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FNEG Z30.D, P2/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z30.D, P3, Z30.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z28.D, P0/M, Z8.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z28.D, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z28.D}, P1, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 42a260 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.11+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code