| Loop Id: 163 | Module: exec | Source: advec_mom.cpp:147-149 [...] | Coverage: 4.45% |
|---|
| Loop Id: 163 | Module: exec | Source: advec_mom.cpp:147-149 [...] | Coverage: 4.45% |
|---|
0x42a504 SEL Z23.D, P1, Z4.D, Z17.D |
0x42a508 ADD X10, X10, X8 |
0x42a50c SDIVR Z23.D, P0/M, Z23.D, Z22.D |
0x42a510 ADD Z24.D, Z5.D, Z23.D |
0x42a514 MSB Z23.D, P0/M, Z4.D, Z22.D |
0x42a518 ADD Z22.D, Z22.D, Z16.D |
0x42a51c SXTW Z24.D, P0/M, Z24.D |
0x42a520 MOVPRFX Z28, Z1 |
0x42a524 MUL Z28.D, P0/M, Z28.D, Z24.D |
0x42a528 MOVPRFX Z26, Z0 |
0x42a52c MUL Z26.D, P0/M, Z26.D, Z24.D |
0x42a530 ADD Z25.D, Z6.D, Z23.D |
0x42a534 ADD Z23.D, Z7.D, Z23.D |
0x42a538 ADR Z29.D, [Z19, Z25.D,SXTW #3] [13] |
0x42a53c ADR Z27.D, [Z18, Z25.D,SXTW #3] [11] |
0x42a540 ADR Z23.D, [Z20, Z23.D,SXTW #3] [1] |
0x42a544 ADR Z28.D, [Z29, Z28.D,LSL #3] [14] |
0x42a548 MOVPRFX Z29, Z2 |
0x42a54c MUL Z29.D, P0/M, Z29.D, Z24.D |
0x42a550 ADR Z26.D, [Z27, Z26.D,LSL #3] [10] |
0x42a554 MUL Z24.D, P0/M, Z24.D, Z3.D |
0x42a558 LD1D {Z27.D}, P1/Z, [V26.D] [7] |
0x42a55c LD1D {Z28.D}, P1/Z, [V28.D] [12] |
0x42a560 ADR Z23.D, [Z23, Z29.D,LSL #3] [4] |
0x42a564 LD1D {Z23.D}, P1/Z, [V23.D] [3] |
0x42a568 FMLA Z23.D, P0/M, Z27.D, Z28.D |
0x42a56c ADR Z27.D, [Z20, Z25.D,SXTW #3] [1] |
0x42a570 ADR Z25.D, [Z21, Z25.D,SXTW #3] [2] |
0x42a574 ADR Z27.D, [Z27, Z29.D,LSL #3] [9] |
0x42a578 ADR Z24.D, [Z25, Z24.D,LSL #3] [6] |
0x42a57c LD1D {Z27.D}, P1/Z, [V27.D] [8] |
0x42a580 FSUB Z23.D, Z23.D, Z27.D |
0x42a584 LD1D {Z24.D}, P1/Z, [V24.D] [5] |
0x42a588 FDIV Z23.D, P0/M, Z23.D, Z24.D |
0x42a58c ST1D {Z23.D}, P1, [V26.D] [7] |
0x42a590 WHILELO P1.D, X10, X9 |
0x42a594 B.MI 42a504 |
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69 |
-------------------------------------------------------------------------------- |
69: T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; } |
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 147 - 149 |
-------------------------------------------------------------------------------- |
147: for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) { |
148: for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) { |
149: vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j); |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►98.43+ | __kmp_invoke_microtask | libomp.so | |
| ○ | __kmp_invoke_task_func | libomp.so | |
| ○ | __kmp_launch_thread | libomp.so | |
| ○ | __kmp_launch_worker(void*) | libomp.so | |
| ○ | start_thread | libc.so.6 | |
| ○ | thread_start | libc.so.6 |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.37 - 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.43 |
| Bottlenecks | P6, P8, |
| Function | advec_mom_kernel(int, int, int, int, clover::Buffer2D |
| Source | context.h:69-69,advec_mom.cpp:147-149 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 14.00 - 34.08 |
| CQA cycles if no scalar integer | 14.00 - 34.08 |
| CQA cycles if FP arith vectorized | 14.00 - 34.08 |
| CQA cycles if fully vectorized | 10.25 - 34.08 |
| Front-end cycles | 4.63 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 0.50 |
| P3 cycles | 0.25 |
| P4 cycles | 1.00 |
| P5 cycles | 0.25 |
| P6 cycles | 14.00 |
| P7 cycles | 14.00 |
| P8 cycles | 3.00 |
| P9 cycles | 3.00 |
| P10 cycles | 2.17 |
| P11 cycles | 1.83 |
| P12 cycles | 2.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 7.87 - 34.08 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 37.00 |
| Nb uops | 37.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.14 - 0.47 |
| Nb FLOP add-sub | 4.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 4.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 5.67 - 13.80 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 161.25 |
| Bytes stored | 32.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 10.00 |
| Stride indirect | 4.00 |
| Vectorization ratio all | 61.76 |
| Vectorization ratio load | 33.33 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 33.33 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 40.00 |
| Vector-efficiency ratio all | 77.94 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 100.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.37 - 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.43 |
| Bottlenecks | P6, P8, |
| Function | advec_mom_kernel(int, int, int, int, clover::Buffer2D |
| Source | context.h:69-69,advec_mom.cpp:147-149 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 14.00 - 34.08 |
| CQA cycles if no scalar integer | 14.00 - 34.08 |
| CQA cycles if FP arith vectorized | 14.00 - 34.08 |
| CQA cycles if fully vectorized | 10.25 - 34.08 |
| Front-end cycles | 4.63 |
| P0 cycles | 0.50 |
| P1 cycles | 0.50 |
| P2 cycles | 0.50 |
| P3 cycles | 0.25 |
| P4 cycles | 1.00 |
| P5 cycles | 0.25 |
| P6 cycles | 14.00 |
| P7 cycles | 14.00 |
| P8 cycles | 3.00 |
| P9 cycles | 3.00 |
| P10 cycles | 2.17 |
| P11 cycles | 1.83 |
| P12 cycles | 2.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| DIV/SQRT cycles | 7.87 - 34.08 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 37.00 |
| Nb uops | 37.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.14 - 0.47 |
| Nb FLOP add-sub | 4.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 4.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 5.67 - 13.80 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 161.25 |
| Bytes stored | 32.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 10.00 |
| Stride indirect | 4.00 |
| Vectorization ratio all | 61.76 |
| Vectorization ratio load | 33.33 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 33.33 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 40.00 |
| Vector-efficiency ratio all | 77.94 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 100.00 |
| Path / |
| nb instructions | 37 |
| nb uops | 37 |
| loop length | 148 |
| used w registers | 0 |
| used x registers | 3 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 5 |
| used z registers | 22 |
| nb stack references | 0 |
| micro-operation queue | 4.63 cycles |
| front end | 4.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 14.00 | 14.00 | 3.00 | 3.00 | 2.17 | 1.83 | 2.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 14.00 | 14.00 | 3.00 | 3.00 | 2.17 | 1.83 | 2.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 7.87-34.08 |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 4.63 |
| Dispatch | 14.00 |
| DIV/SQRT | 7.87-34.08 |
| Data deps. | 2.00 |
| Overall L1 | 14.00-34.08 |
| all | 58% |
| load | 33% |
| store | 100% |
| mul | 100% |
| add-sub | 28% |
| fma | 100% |
| other | 50% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 61% |
| load | 33% |
| store | 100% |
| mul | 100% |
| add-sub | 33% |
| fma | 100% |
| div/sqrt | 100% |
| other | 40% |
| all | 75% |
| load | 50% |
| store | 100% |
| mul | 100% |
| add-sub | 46% |
| fma | 100% |
| other | 100% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 77% |
| load | 50% |
| store | 100% |
| mul | 100% |
| add-sub | 50% |
| fma | 100% |
| div/sqrt | 100% |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SEL Z23.D, P1, Z4.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADD X10, X10, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SDIVR Z23.D, P0/M, Z23.D, Z22.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-20 | 0.87-20 | vect (100.0%) |
| ADD Z24.D, Z5.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| MSB Z23.D, P0/M, Z4.D, Z22.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADD Z22.D, Z22.D, Z16.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| SXTW Z24.D, P0/M, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | vect (100.0%) |
| MOVPRFX Z28, Z1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z28.D, P0/M, Z28.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| MOVPRFX Z26, Z0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z26.D, P0/M, Z26.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADD Z25.D, Z6.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADD Z23.D, Z7.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADR Z29.D, [Z19, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z27.D, [Z18, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z23.D, [Z20, Z23.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z28.D, [Z29, Z28.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| MOVPRFX Z29, Z2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z29.D, P0/M, Z29.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADR Z26.D, [Z27, Z26.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| MUL Z24.D, P0/M, Z24.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| LD1D {Z27.D}, P1/Z, [V26.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| LD1D {Z28.D}, P1/Z, [V28.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| ADR Z23.D, [Z23, Z29.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LD1D {Z23.D}, P1/Z, [V23.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| FMLA Z23.D, P0/M, Z27.D, Z28.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| ADR Z27.D, [Z20, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z25.D, [Z21, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z27.D, [Z27, Z29.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z24.D, [Z25, Z24.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LD1D {Z27.D}, P1/Z, [V27.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| FSUB Z23.D, Z23.D, Z27.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z24.D}, P1/Z, [V24.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| FDIV Z23.D, P0/M, Z23.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 6.99-14.08 | vect (100.0%) |
| ST1D {Z23.D}, P1, [V26.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 | vect (100.0%) |
| WHILELO P1.D, X10, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 42a504 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.13+0x124> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| nb instructions | 37 |
| nb uops | 37 |
| loop length | 148 |
| used w registers | 0 |
| used x registers | 3 |
| used b registers | 0 |
| used h registers | 0 |
| used s registers | 0 |
| used d registers | 0 |
| used q registers | 0 |
| used v registers | 5 |
| used z registers | 22 |
| nb stack references | 0 |
| micro-operation queue | 4.63 cycles |
| front end | 4.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 14.00 | 14.00 | 3.00 | 3.00 | 2.17 | 1.83 | 2.00 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 0.50 | 0.25 | 1.00 | 0.25 | 14.00 | 14.00 | 3.00 | 3.00 | 2.17 | 1.83 | 2.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 7.87-34.08 |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 4.63 |
| Dispatch | 14.00 |
| DIV/SQRT | 7.87-34.08 |
| Data deps. | 2.00 |
| Overall L1 | 14.00-34.08 |
| all | 58% |
| load | 33% |
| store | 100% |
| mul | 100% |
| add-sub | 28% |
| fma | 100% |
| other | 50% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 61% |
| load | 33% |
| store | 100% |
| mul | 100% |
| add-sub | 33% |
| fma | 100% |
| div/sqrt | 100% |
| other | 40% |
| all | 75% |
| load | 50% |
| store | 100% |
| mul | 100% |
| add-sub | 46% |
| fma | 100% |
| other | 100% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 77% |
| load | 50% |
| store | 100% |
| mul | 100% |
| add-sub | 50% |
| fma | 100% |
| div/sqrt | 100% |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| SEL Z23.D, P1, Z4.D, Z17.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADD X10, X10, X8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 | N/A |
| SDIVR Z23.D, P0/M, Z23.D, Z22.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-20 | 0.87-20 | vect (100.0%) |
| ADD Z24.D, Z5.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| MSB Z23.D, P0/M, Z4.D, Z22.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADD Z22.D, Z22.D, Z16.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| SXTW Z24.D, P0/M, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 | vect (100.0%) |
| MOVPRFX Z28, Z1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z28.D, P0/M, Z28.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| MOVPRFX Z26, Z0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z26.D, P0/M, Z26.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADD Z25.D, Z6.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADD Z23.D, Z7.D, Z23.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| ADR Z29.D, [Z19, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z27.D, [Z18, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z23.D, [Z20, Z23.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z28.D, [Z29, Z28.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| MOVPRFX Z29, Z2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (100.0%) |
| MUL Z29.D, P0/M, Z29.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| ADR Z26.D, [Z27, Z26.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| MUL Z24.D, P0/M, Z24.D, Z3.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 2 | vect (100.0%) |
| LD1D {Z27.D}, P1/Z, [V26.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| LD1D {Z28.D}, P1/Z, [V28.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| ADR Z23.D, [Z23, Z29.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LD1D {Z23.D}, P1/Z, [V23.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| FMLA Z23.D, P0/M, Z27.D, Z28.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | vect (100.0%) |
| ADR Z27.D, [Z20, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z25.D, [Z21, Z25.D,SXTW #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z27.D, [Z27, Z29.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| ADR Z24.D, [Z25, Z24.D,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | scal (25.0%) |
| LD1D {Z27.D}, P1/Z, [V27.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| FSUB Z23.D, Z23.D, Z27.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0.50 | vect (100.0%) |
| LD1D {Z24.D}, P1/Z, [V24.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.33 | 0.33 | 0.33 | 0 | 0 | 9 | 2 | vect (100.0%) |
| FDIV Z23.D, P0/M, Z23.D, Z24.D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 6.99-14.08 | vect (100.0%) |
| ST1D {Z23.D}, P1, [V26.D] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0 | 0 | 6 | 2 | vect (100.0%) |
| WHILELO P1.D, X10, X9 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 2 | N/A |
| B.MI 42a504 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.13+0x124> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
