OV - exec - Loop 169

	Loop Id: 169	Module: exec	Source: build_field.cpp:101-113 [...]	Coverage: 0.02%

0x42b300 DUP	Z1.D, #1

0x42b304 SUB	X11, X29, #64

0x42b308 ADD	X10, X10, X8

0x42b30c SEL	Z11.D, P0, Z3.D, Z1.D

0x42b310 LDR	Z1, [X11, #511, MUL VL]    [27]

0x42b314 MOVPRFX	Z12, Z10

0x42b318 SDIV	Z12.D, P1/M, Z12.D, Z11.D

0x42b31c MOVPRFX	Z11, Z10

0x42b320 MLS	Z11.D, P1/M, Z12.D, Z3.D

0x42b324 SXTW	Z12.D, P1/M, Z12.D

0x42b328 ADD	Z10.D, Z10.D, Z7.D

0x42b32c MOVPRFX	Z13, Z1

0x42b330 MUL	Z13.D, P1/M, Z13.D, Z12.D

0x42b334 LDR	Z1, [X11, #510, MUL VL]    [27]

0x42b338 MOVPRFX	Z17, Z2

0x42b33c MUL	Z17.D, P1/M, Z17.D, Z12.D

0x42b340 MOVPRFX	Z18, Z16

0x42b344 MUL	Z18.D, P1/M, Z18.D, Z12.D

0x42b348 MOVPRFX	Z19, Z0

0x42b34c MUL	Z19.D, P1/M, Z19.D, Z12.D

0x42b350 MOVPRFX	Z14, Z1

0x42b354 MUL	Z14.D, P1/M, Z14.D, Z12.D

0x42b358 LDR	Z1, [X11, #509, MUL VL]    [27]

0x42b35c MOVPRFX	Z15, Z1

0x42b360 MUL	Z15.D, P1/M, Z15.D, Z12.D

0x42b364 LDR	Z1, [X11, #508, MUL VL]    [27]

0x42b368 MOVPRFX	Z4, Z1

0x42b36c MUL	Z4.D, P1/M, Z4.D, Z12.D

0x42b370 LDR	Z1, [X11, #507, MUL VL]    [27]

0x42b374 MOVPRFX	Z5, Z1

0x42b378 MUL	Z5.D, P1/M, Z5.D, Z12.D

0x42b37c LDR	Z1, [X11, #506, MUL VL]    [27]

0x42b380 MOVPRFX	Z6, Z1

0x42b384 MUL	Z6.D, P1/M, Z6.D, Z12.D

0x42b388 ADR	Z1.D, [Z20, Z11.D,SXTW #3]    [5]

0x42b38c ADR	Z1.D, [Z1, Z13.D,LSL #3]    [34]

0x42b390 ADR	Z13.D, [Z24, Z11.D,SXTW #3]    [15]

0x42b394 ADR	Z13.D, [Z13, Z14.D,LSL #3]    [10]

0x42b398 ADR	Z14.D, [Z25, Z11.D,SXTW #3]    [24]

0x42b39c ST1D	{Z21.D}, P0, [V1.D]    [33]

0x42b3a0 MOVPRFX	Z1, Z22

0x42b3a4 MUL	Z1.D, P1/M, Z1.D, Z12.D

0x42b3a8 ADR	Z14.D, [Z14, Z15.D,LSL #3]    [13]

0x42b3ac ADR	Z15.D, [Z26, Z11.D,SXTW #3]    [25]

0x42b3b0 ST1D	{Z21.D}, P0, [V13.D]    [9]

0x42b3b4 MUL	Z12.D, P1/M, Z12.D, Z23.D

0x42b3b8 ADR	Z4.D, [Z15, Z4.D,LSL #3]    [23]

0x42b3bc ADR	Z15.D, [Z27, Z11.D,SXTW #3]    [28]

0x42b3c0 ADR	Z5.D, [Z15, Z5.D,LSL #3]    [22]

0x42b3c4 ADR	Z15.D, [Z28, Z11.D,SXTW #3]    [30]

0x42b3c8 ST1D	{Z21.D}, P0, [V14.D]    [12]

0x42b3cc ST1D	{Z21.D}, P0, [V4.D]    [2]

0x42b3d0 ADR	Z4.D, [Z8, Z11.D,SXTW #3]    [8]

0x42b3d4 ADR	Z6.D, [Z15, Z6.D,LSL #3]    [21]

0x42b3d8 ADR	Z15.D, [Z29, Z11.D,SXTW #3]    [32]

0x42b3dc ADR	Z1.D, [Z4, Z1.D,LSL #3]    [1]

0x42b3e0 ST1D	{Z21.D}, P0, [V5.D]    [3]

0x42b3e4 ADR	Z17.D, [Z15, Z17.D,LSL #3]    [20]

0x42b3e8 ADR	Z15.D, [Z30, Z11.D,SXTW #3]    [6]

0x42b3ec ST1D	{Z21.D}, P0, [V6.D]    [4]

0x42b3f0 ADR	Z18.D, [Z15, Z18.D,LSL #3]    [19]

0x42b3f4 ADR	Z15.D, [Z31, Z11.D,SXTW #3]    [7]

0x42b3f8 ST1D	{Z21.D}, P0, [V17.D]    [26]

0x42b3fc ADR	Z19.D, [Z15, Z19.D,LSL #3]    [18]

0x42b400 ST1D	{Z21.D}, P0, [V18.D]    [29]

0x42b404 ST1D	{Z21.D}, P0, [V19.D]    [31]

0x42b408 ST1D	{Z21.D}, P0, [V1.D]    [17]

0x42b40c ADR	Z1.D, [Z9, Z11.D,SXTW #3]    [11]

0x42b410 ADR	Z1.D, [Z1, Z12.D,LSL #3]    [16]

0x42b414 ST1D	{Z21.D}, P0, [V1.D]    [14]

0x42b418 WHILELO	P0.D, X10, X9

0x42b41c B.MI	42b300

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp: 101 - 113

--------------------------------------------------------------------------------

101:     for (int j = (0); j < (yrange + 1); j++) {

102:       for (int i = (0); i < (xrange + 1); i++) {

103:         field.work_array1(i, j) = 0.0;

104:         field.work_array2(i, j) = 0.0;

105:         field.work_array3(i, j) = 0.0;

106:         field.work_array4(i, j) = 0.0;

107:         field.work_array5(i, j) = 0.0;

108:         field.work_array6(i, j) = 0.0;

109:         field.work_array7(i, j) = 0.0;

110:         field.xvel0(i, j) = 0.0;

111:         field.xvel1(i, j) = 0.0;

112:         field.yvel0(i, j) = 0.0;

113:         field.yvel1(i, j) = 0.0;

Coverage (%)	Name	Source Location	Module
►98.67+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.33+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	build_field(global_variables&)	build_field.cpp:118	exec
○	start(parallel_&, global_confi[...]	start.cpp:71	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	stl_vector.h:735	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.52 - 1.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	build_field(global_variables&) [clone .omp_outlined]
Source	context.h:69-69,build_field.cpp:101-113
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.50
CQA cycles if no scalar integer	25.50
CQA cycles if FP arith vectorized	25.50
CQA cycles if fully vectorized	16.78 - 20.00
Front-end cycles	9.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	25.50
P7 cycles	25.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	8.50
P11 cycles	8.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	72.00
Nb uops	72.00
Nb loads	NA
Nb stores	11.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.44
Bytes prefetched	0.00
Bytes loaded	194.75
Bytes stored	352.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	23.00
Stride indirect	11.00
Vectorization ratio all	48.53
Vectorization ratio load	21.43
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	8.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	13.33
Vector-efficiency ratio all	74.31
Vector-efficiency ratio load	41.07
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	31.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	93.54

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.52 - 1.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	build_field(global_variables&) [clone .omp_outlined]
Source	context.h:69-69,build_field.cpp:101-113
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.50
CQA cycles if no scalar integer	25.50
CQA cycles if FP arith vectorized	25.50
CQA cycles if fully vectorized	16.78 - 20.00
Front-end cycles	9.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	25.50
P7 cycles	25.50
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	8.50
P11 cycles	8.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	72.00
Nb uops	72.00
Nb loads	NA
Nb stores	11.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.44
Bytes prefetched	0.00
Bytes loaded	194.75
Bytes stored	352.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	23.00
Stride indirect	11.00
Vectorization ratio all	48.53
Vectorization ratio load	21.43
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	8.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	13.33
Vector-efficiency ratio all	74.31
Vector-efficiency ratio load	41.07
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	31.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	93.54

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	build_field(global_variables&) [clone .omp_outlined]
Source file and lines	build_field.cpp:101-113
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:101-113

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 74% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 25.50 to 20.00 cycles (1.27x speedup).

Details

48% of VPU instructions are used in vector version (process two or more data elements in vector registers):

21% of VPU loads are used in vector version.
8% of VPU addition or subtraction instructions are used in vector version.
13% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 23 occurrence(s)
Irregular (variable stride) or indirect: 11 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 194 bytes. The binary loop is storing 352 bytes.

General properties

nb instructions	72
nb uops	72
loop length	288
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	9
used z registers	32
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	25.50	25.50	5.50	5.50	8.50	8.50	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	25.50	25.50	5.50	5.50	8.50	8.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.00
Dispatch	25.50
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	25.50

Vectorization ratios

all	48%
load	21%
store	100%
mul	100%
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	13%

Vector efficiency ratios

all	74%
load	41%
store	100%
mul	100%
add-sub	31%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	93%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.50 cycles. At this rate:

7% of peak load performance is reached (7.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (13.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42b300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
DUP Z1.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
SUB X11, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SEL Z11.D, P0, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LDR Z1, [X11, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z12, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SDIV Z12.D, P1/M, Z12.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MLS Z11.D, P1/M, Z12.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
SXTW Z12.D, P1/M, Z12.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1	vect (100.0%)
ADD Z10.D, Z10.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P1/M, Z13.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X11, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z17, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z17.D, P1/M, Z17.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z18.D, P1/M, Z18.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z19, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z19.D, P1/M, Z19.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z14, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z14.D, P1/M, Z14.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X11, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z15, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P1/M, Z15.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X11, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z4, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P1/M, Z4.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X11, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z5, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P1/M, Z5.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X11, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z6, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z6.D, P1/M, Z6.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
ADR Z1.D, [Z20, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z1, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z24, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z13, Z14.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z25, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
MOVPRFX Z1, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z1.D, P1/M, Z1.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
ADR Z14.D, [Z14, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z26, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
MUL Z12.D, P1/M, Z12.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
ADR Z4.D, [Z15, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z27, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z15, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z28, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z21.D}, P0, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z4.D, [Z8, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z15, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z29, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z4, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z17.D, [Z15, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z30, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z18.D, [Z15, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z31, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z19.D, [Z15, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z21.D}, P0, [V19.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z21.D}, P0, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z1.D, [Z9, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z1, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
WHILELO P0.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 42b300 <_Z11build_fieldR16global_variables.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	build_field(global_variables&) [clone .omp_outlined]
Source file and lines	build_field.cpp:101-113
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:101-113

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

48% of VPU instructions are used in vector version (process two or more data elements in vector registers):

21% of VPU loads are used in vector version.
8% of VPU addition or subtraction instructions are used in vector version.
13% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 23 occurrence(s)
Irregular (variable stride) or indirect: 11 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 194 bytes. The binary loop is storing 352 bytes.

General properties

nb instructions	72
nb uops	72
loop length	288
used w registers	0
used x registers	5
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	9
used z registers	32
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	25.50	25.50	5.50	5.50	8.50	8.50	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	25.50	25.50	5.50	5.50	8.50	8.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.00
Dispatch	25.50
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	25.50

Vectorization ratios

all	48%
load	21%
store	100%
mul	100%
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	13%

Vector efficiency ratios

all	74%
load	41%
store	100%
mul	100%
add-sub	31%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	93%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.50 cycles. At this rate:

7% of peak load performance is reached (7.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
28% of peak store performance is reached (13.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42b300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
DUP Z1.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
SUB X11, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SEL Z11.D, P0, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LDR Z1, [X11, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z12, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SDIV Z12.D, P1/M, Z12.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z11, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MLS Z11.D, P1/M, Z12.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
SXTW Z12.D, P1/M, Z12.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1	vect (100.0%)
ADD Z10.D, Z10.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P1/M, Z13.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X11, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z17, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z17.D, P1/M, Z17.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z18, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z18.D, P1/M, Z18.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z19, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z19.D, P1/M, Z19.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z14, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z14.D, P1/M, Z14.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X11, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z15, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P1/M, Z15.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X11, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z4, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P1/M, Z4.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X11, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z5, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P1/M, Z5.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X11, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z6, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z6.D, P1/M, Z6.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
ADR Z1.D, [Z20, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z1, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z24, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z13, Z14.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z25, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
MOVPRFX Z1, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z1.D, P1/M, Z1.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
ADR Z14.D, [Z14, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z26, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
MUL Z12.D, P1/M, Z12.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
ADR Z4.D, [Z15, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z27, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z15, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z28, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z21.D}, P0, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z4.D, [Z8, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z15, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z29, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z4, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z17.D, [Z15, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z30, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z18.D, [Z15, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z31, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z19.D, [Z15, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z21.D}, P0, [V19.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z21.D}, P0, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z1.D, [Z9, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z1, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z21.D}, P0, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
WHILELO P0.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 42b300 <_Z11build_fieldR16global_variables.omp_outlined+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code