OV - exec - Loop 170

	Loop Id: 170	Module: exec	Source: build_field.cpp:119-128 [...]	Coverage: 0.01%

0x42b5a0 SEL	Z29.D, P1, Z6.D, Z18.D

0x42b5a4 ADD	X10, X10, X8

0x42b5a8 SDIVR	Z29.D, P0/M, Z29.D, Z28.D

0x42b5ac MOVPRFX	Z30, Z28

0x42b5b0 MLS	Z30.D, P0/M, Z29.D, Z6.D

0x42b5b4 SXTW	Z29.D, P0/M, Z29.D

0x42b5b8 ADD	Z28.D, Z28.D, Z17.D

0x42b5bc MOVPRFX	Z31, Z0

0x42b5c0 MUL	Z31.D, P0/M, Z31.D, Z29.D

0x42b5c4 MOVPRFX	Z8, Z1

0x42b5c8 MUL	Z8.D, P0/M, Z8.D, Z29.D

0x42b5cc MOVPRFX	Z9, Z2

0x42b5d0 MUL	Z9.D, P0/M, Z9.D, Z29.D

0x42b5d4 MOVPRFX	Z10, Z3

0x42b5d8 MUL	Z10.D, P0/M, Z10.D, Z29.D

0x42b5dc MOVPRFX	Z11, Z4

0x42b5e0 MUL	Z11.D, P0/M, Z11.D, Z29.D

0x42b5e4 MOVPRFX	Z12, Z5

0x42b5e8 MUL	Z12.D, P0/M, Z12.D, Z29.D

0x42b5ec ADR	Z13.D, [Z19, Z30.D,SXTW #3]    [23]

0x42b5f0 ADR	Z31.D, [Z13, Z31.D,LSL #3]    [17]

0x42b5f4 ADR	Z13.D, [Z21, Z30.D,SXTW #3]    [4]

0x42b5f8 ADR	Z8.D, [Z13, Z8.D,LSL #3]    [16]

0x42b5fc ADR	Z13.D, [Z22, Z30.D,SXTW #3]    [10]

0x42b600 ST1D	{Z20.D}, P1, [V31.D]    [6]

0x42b604 MOVPRFX	Z31, Z7

0x42b608 MUL	Z31.D, P0/M, Z31.D, Z29.D

0x42b60c MUL	Z29.D, P0/M, Z29.D, Z16.D

0x42b610 ADR	Z9.D, [Z13, Z9.D,LSL #3]    [15]

0x42b614 ADR	Z13.D, [Z23, Z30.D,SXTW #3]    [18]

0x42b618 ST1D	{Z20.D}, P1, [V8.D]    [8]

0x42b61c ADR	Z8.D, [Z26, Z30.D,SXTW #3]    [21]

0x42b620 ADR	Z10.D, [Z13, Z10.D,LSL #3]    [14]

0x42b624 ADR	Z13.D, [Z24, Z30.D,SXTW #3]    [19]

0x42b628 ST1D	{Z20.D}, P1, [V9.D]    [12]

0x42b62c ADR	Z31.D, [Z8, Z31.D,LSL #3]    [7]

0x42b630 ADR	Z11.D, [Z13, Z11.D,LSL #3]    [13]

0x42b634 ADR	Z13.D, [Z25, Z30.D,SXTW #3]    [20]

0x42b638 ADR	Z30.D, [Z27, Z30.D,SXTW #3]    [22]

0x42b63c ST1D	{Z20.D}, P1, [V10.D]    [1]

0x42b640 ADR	Z12.D, [Z13, Z12.D,LSL #3]    [11]

0x42b644 ADR	Z29.D, [Z30, Z29.D,LSL #3]    [2]

0x42b648 ST1D	{Z20.D}, P1, [V11.D]    [3]

0x42b64c ST1D	{Z20.D}, P1, [V12.D]    [9]

0x42b650 ST1D	{Z20.D}, P1, [V31.D]    [5]

0x42b654 ST1D	{Z20.D}, P1, [V29.D]    [24]

0x42b658 WHILELO	P1.D, X10, X9

0x42b65c B.MI	42b5a0

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp: 119 - 128

--------------------------------------------------------------------------------

119:     for (int j = (0); j < (yrange); j++) {

120:       for (int i = (0); i < (xrange); i++) {

121:         field.density0(i, j) = 0.0;

122:         field.density1(i, j) = 0.0;

123:         field.energy0(i, j) = 0.0;

124:         field.energy1(i, j) = 0.0;

125:         field.pressure(i, j) = 0.0;

126:         field.viscosity(i, j) = 0.0;

127:         field.soundspeed(i, j) = 0.0;

128:         field.volume(i, j) = 0.0;

Coverage (%)	Name	Source Location	Module
►97.86+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.14+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	build_field(global_variables&)	build_field.cpp:133	exec
○	start(parallel_&, global_confi[...]	start.cpp:71	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	stl_vector.h:735	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.48 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.08 - 1.08
Bottlenecks	P6, P8,
Function	build_field(global_variables&) [clone .omp_outlined.1]
Source	context.h:69-69,build_field.cpp:119-128
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.50 - 20.00
CQA cycles if no scalar integer	18.50 - 20.00
CQA cycles if FP arith vectorized	18.50 - 20.00
CQA cycles if fully vectorized	12.50 - 20.00
Front-end cycles	6.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	18.50
P7 cycles	18.50
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	48.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.90 - 13.95
Bytes prefetched	0.00
Bytes loaded	2.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	8.00
Vectorization ratio all	46.67
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	11.11
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	20.00
Vector-efficiency ratio all	73.33
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	33.33
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.48 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.08 - 1.08
Bottlenecks	P6, P8,
Function	build_field(global_variables&) [clone .omp_outlined.1]
Source	context.h:69-69,build_field.cpp:119-128
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	18.50 - 20.00
CQA cycles if no scalar integer	18.50 - 20.00
CQA cycles if FP arith vectorized	18.50 - 20.00
CQA cycles if fully vectorized	12.50 - 20.00
Front-end cycles	6.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	18.50
P7 cycles	18.50
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	48.00
Nb uops	48.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00 - 0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.90 - 13.95
Bytes prefetched	0.00
Bytes loaded	2.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	16.00
Stride indirect	8.00
Vectorization ratio all	46.67
Vectorization ratio load	0.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	11.11
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	20.00
Vector-efficiency ratio all	73.33
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	33.33
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	build_field(global_variables&) [clone .omp_outlined.1]
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119-128

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 73% of vector register length is used (average across all VPU instructions).

Details

46% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
11% of VPU addition or subtraction instructions are used in vector version.
20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 18.00 cycles (1.11x speedup).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)
Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 2 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	48
nb uops	48
loop length	192
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	7
used z registers	30
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	18.50	18.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	18.50	18.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.00
Dispatch	18.50
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	18.50-20.00

Vectorization ratios

all	46%
load	0%
store	100%
mul	100%
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	20%

Vector efficiency ratios

all	73%
load	25%
store	100%
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42b5a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SEL Z29.D, P1, Z6.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z29.D, P0/M, Z29.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z30, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MLS Z30.D, P0/M, Z29.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1	vect (100.0%)
ADD Z28.D, Z28.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z31.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z8, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z8.D, P0/M, Z8.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z9, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z9.D, P0/M, Z9.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z10, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z10.D, P0/M, Z10.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z11, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z11.D, P0/M, Z11.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z12, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
ADR Z13.D, [Z19, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z13, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z21, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z13, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z22, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z20.D}, P1, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
MOVPRFX Z31, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z31.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MUL Z29.D, P0/M, Z29.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
ADR Z9.D, [Z13, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z23, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z20.D}, P1, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z8.D, [Z26, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z13, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z24, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z20.D}, P1, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z31.D, [Z8, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z11.D, [Z13, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z25, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z27, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z20.D}, P1, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z12.D, [Z13, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z30, Z29.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z20.D}, P1, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z20.D}, P1, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z20.D}, P1, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z20.D}, P1, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
WHILELO P1.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 42b5a0 <_Z11build_fieldR16global_variables.omp_outlined.1+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	build_field(global_variables&) [clone .omp_outlined.1]
Source file and lines	build_field.cpp:119-128
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/build_field.cpp:119-128

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 73% of vector register length is used (average across all VPU instructions).

Details

46% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
11% of VPU addition or subtraction instructions are used in vector version.
20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 18.00 cycles (1.11x speedup).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 16 occurrence(s)
Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 2 bytes. The binary loop is storing 256 bytes.

General properties

nb instructions	48
nb uops	48
loop length	192
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	7
used z registers	30
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	18.50	18.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	18.50	18.50	4.00	4.00	4.00	4.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	6.00
Dispatch	18.50
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	18.50-20.00

Vectorization ratios

all	46%
load	0%
store	100%
mul	100%
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	20%

Vector efficiency ratios

all	73%
load	25%
store	100%
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

0% of peak load performance is reached (0.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42b5a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SEL Z29.D, P1, Z6.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z29.D, P0/M, Z29.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z30, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MLS Z30.D, P0/M, Z29.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
SXTW Z29.D, P0/M, Z29.D	1	0	0	0	0	0	0	0	1	0	0	0	0	2	1	vect (100.0%)
ADD Z28.D, Z28.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z31.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z8, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z8.D, P0/M, Z8.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z9, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z9.D, P0/M, Z9.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z10, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z10.D, P0/M, Z10.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z11, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z11.D, P0/M, Z11.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z12, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
ADR Z13.D, [Z19, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z13, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z21, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z13, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z22, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z20.D}, P1, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
MOVPRFX Z31, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MUL Z31.D, P0/M, Z31.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MUL Z29.D, P0/M, Z29.D, Z16.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
ADR Z9.D, [Z13, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z23, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z20.D}, P1, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z8.D, [Z26, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z13, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z24, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z20.D}, P1, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z31.D, [Z8, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z11.D, [Z13, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z25, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z27, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z20.D}, P1, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ADR Z12.D, [Z13, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z30, Z29.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z20.D}, P1, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z20.D}, P1, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z20.D}, P1, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
ST1D {Z20.D}, P1, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	2	vect (100.0%)
WHILELO P1.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.MI 42b5a0 <_Z11build_fieldR16global_variables.omp_outlined.1+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code