OV - exec - Loop 181

	Loop Id: 181	Module: exec	Source: calc_dt.cpp:50-75 [...]	Coverage: 4.54%

0x42ca40 MOVPRFX	Z7, Z23

0x42ca44 SDIV	Z7.D, P0/M, Z7.D, Z20.D

0x42ca48 SUB	X12, X29, #64

0x42ca4c SUBS	X27, X27, #2

0x42ca50 LDR	Z4, [X12, #511, MUL VL]    [1]

0x42ca54 XTN	V10.2S, V7.2D

0x42ca58 MSB	Z7.D, P0/M, Z20.D, Z23.D

0x42ca5c ADD	V17.2S, V21.2S, V10.2S

0x42ca60 SSHLL	V11.2D, V17.2S, #32

0x42ca64 XTN	V9.2S, V7.2D

0x42ca68 MOVPRFX	Z12, Z4

0x42ca6c MUL	Z12.D, P0/M, Z12.D, Z11.D

0x42ca70 MOVPRFX	Z13, Z5

0x42ca74 MUL	Z13.D, P0/M, Z13.D, Z11.D

0x42ca78 FMOV	X19, D11

0x42ca7c MOVPRFX	Z14, Z6

0x42ca80 MUL	Z14.D, P0/M, Z14.D, Z11.D

0x42ca84 MOV	X21, V11.D[1]

0x42ca88 MOVPRFX	Z15, Z16

0x42ca8c MUL	Z15.D, P0/M, Z15.D, Z11.D

0x42ca90 MOVPRFX	Z18, Z31

0x42ca94 MUL	Z18.D, P0/M, Z18.D, Z11.D

0x42ca98 ADD	V7.2S, V22.2S, V9.2S

0x42ca9c ADD	V9.2S, V9.2S, V26.2S

0x42caa0 ADD	X21, X10, X21,LSL #3

0x42caa4 SSHLL	V17.2D, V7.2S, #32

0x42caa8 MOVPRFX	Z7, Z28

0x42caac MUL	Z7.D, P0/M, Z7.D, Z11.D

0x42cab0 SSHLL	V9.2D, V9.2S, #32

0x42cab4 FMOV	X30, D17

0x42cab8 MOV	X14, V12.D[1]

0x42cabc FMOV	X26, D12

0x42cac0 MOV	X16, V13.D[1]

0x42cac4 FMOV	X1, D13

0x42cac8 LDR	D13, [X10, X19,LSL #3]    [10]

0x42cacc MOV	X28, V17.D[1]

0x42cad0 MOVPRFX	Z17, Z30

0x42cad4 MUL	Z17.D, P0/M, Z17.D, Z11.D

0x42cad8 UBFM	X22, X30, #61, #60

0x42cadc ADD	X12, X9, X28,LSL #3

0x42cae0 ADD	X19, X13, X30,LSL #3

0x42cae4 ADD	X25, X17, X28,LSL #3

0x42cae8 MUL	Z11.D, P0/M, Z11.D, Z19.D

0x42caec LDR	D12, [X9, X22]    [4]

0x42caf0 ADD	X22, X13, X28,LSL #3

0x42caf4 LD1	{V13.D[1]}, [X21]    [32]

0x42caf8 ADD	X21, X11, X30,LSL #3

0x42cafc LD1	{V12.D[1]}, [X12]    [25]

0x42cb00 ADD	X12, X22, X16,LSL #3

0x42cb04 MOV	X16, V14.D[1]

0x42cb08 FMOV	X22, D14

0x42cb0c LDR	D14, [X19, X1,LSL #3]    [30]

0x42cb10 ADD	X1, X15, X28,LSL #3

0x42cb14 ADD	X19, X17, X30,LSL #3

0x42cb18 ADD	X16, X1, X16,LSL #3

0x42cb1c FMOV	X1, D7

0x42cb20 LDR	D4, [X19, X1,LSL #3]    [29]

0x42cb24 LD1	{V14.D[1]}, [X12]    [24]

0x42cb28 MOV	X12, V7.D[1]

0x42cb2c ADD	V7.2S, V10.2S, V24.2S

0x42cb30 SSHLL	V10.2D, V7.2S, #32

0x42cb34 FMINNM	V7.2D, V12.2D, V13.2D

0x42cb38 MOVPRFX	Z12, Z28

0x42cb3c MUL	Z12.D, P0/M, Z12.D, Z10.D

0x42cb40 FMUL	V7.2D, V7.2D, V0.D[0]

0x42cb44 FADD	V13.2D, V14.2D, V14.2D

0x42cb48 FMOV	X7, D12

0x42cb4c MOV	X3, V12.D[1]

0x42cb50 LDR	D12, [X19, X7,LSL #3]    [29]

0x42cb54 ADD	X19, X25, X12,LSL #3

0x42cb58 ADD	X25, X25, X3,LSL #3

0x42cb5c LD1	{V4.D[1]}, [X19]    [28]

0x42cb60 ADD	X19, X11, X28,LSL #3

0x42cb64 ADD	X14, X19, X14,LSL #3

0x42cb68 LD1	{V12.D[1]}, [X25]    [19]

0x42cb6c ADD	X25, X15, X30,LSL #3

0x42cb70 FADD	V4.2D, V4.2D, V12.2D

0x42cb74 LDR	D12, [X25, X22,LSL #3]    [17]

0x42cb78 FMOV	X22, D9

0x42cb7c ADD	X25, X17, X22,LSL #3

0x42cb80 LD1	{V12.D[1]}, [X16]    [3]

0x42cb84 MOV	X16, V9.D[1]

0x42cb88 LDR	D9, [X25, X1,LSL #3]    [15]

0x42cb8c MOV	X1, V15.D[1]

0x42cb90 FDIV	V13.2D, V13.2D, V12.2D

0x42cb94 LDR	D12, [X25, X7,LSL #3]    [15]

0x42cb98 FMOV	X7, D15

0x42cb9c ADD	X25, X0, X30,LSL #3

0x42cba0 LDR	D14, [X25, X7,LSL #3]    [14]

0x42cba4 ADD	X25, X0, X28,LSL #3

0x42cba8 ADD	X19, X25, X1,LSL #3

0x42cbac LD1	{V14.D[1]}, [X19]    [6]

0x42cbb0 ADD	X19, X17, X16,LSL #3

0x42cbb4 ADD	X12, X19, X12,LSL #3

0x42cbb8 ADD	X3, X19, X3,LSL #3

0x42cbbc LD1	{V9.D[1]}, [X12]    [23]

0x42cbc0 LD1	{V12.D[1]}, [X3]    [27]

0x42cbc4 ADD	X12, X0, X22,LSL #3

0x42cbc8 ADD	X3, X0, X16,LSL #3

0x42cbcc ADD	X22, X4, X22,LSL #3

0x42cbd0 ADD	X16, X4, X16,LSL #3

0x42cbd4 ADD	X1, X3, X1,LSL #3

0x42cbd8 ADD	X3, X2, X30,LSL #3

0x42cbdc FMUL	V4.2D, V4.2D, V14.2D

0x42cbe0 FADD	V9.2D, V9.2D, V12.2D

0x42cbe4 LDR	D12, [X12, X7,LSL #3]    [22]

0x42cbe8 MOV	X12, V17.D[1]

0x42cbec ADD	X7, X2, X28,LSL #3

0x42cbf0 ADD	X12, X7, X12,LSL #3

0x42cbf4 ADD	X7, X4, X28,LSL #3

0x42cbf8 LD1	{V12.D[1]}, [X1]    [13]

0x42cbfc FMOV	X1, D17

0x42cc00 LDR	D17, [X3, X1,LSL #3]    [18]

0x42cc04 FMOV	X1, D18

0x42cc08 ADD	X3, X4, X30,LSL #3

0x42cc0c LD1	{V17.D[1]}, [X12]    [21]

0x42cc10 FMUL	V9.2D, V9.2D, V12.2D

0x42cc14 MOVI	V12.2D, #0

0x42cc18 MOV	X12, V18.D[1]

0x42cc1c ADD	X19, X7, X12,LSL #3

0x42cc20 ADD	X12, X16, X12,LSL #3

0x42cc24 FADD	V12.2D, V9.2D, V12.2D

0x42cc28 FABS	V9.2D, V9.2D

0x42cc2c FSUB	V12.2D, V12.2D, V4.2D

0x42cc30 FABS	V4.2D, V4.2D

0x42cc34 FMAXNM	V4.2D, V4.2D, V9.2D

0x42cc38 FMUL	V9.2D, V17.2D, V27.2D

0x42cc3c FMUL	V14.2D, V17.2D, V1.D[0]

0x42cc40 FMAXNM	V4.2D, V4.2D, V9.2D

0x42cc44 FDIV	V18.2D, V14.2D, V4.2D

0x42cc48 LDR	D4, [X3, X1,LSL #3]    [16]

0x42cc4c LDR	D14, [X22, X1,LSL #3]    [11]

0x42cc50 ADD	X1, X6, X30,LSL #3

0x42cc54 LD1	{V4.D[1]}, [X19]    [5]

0x42cc58 LD1	{V14.D[1]}, [X12]    [20]

0x42cc5c MOV	X12, V11.D[1]

0x42cc60 ADD	X19, X6, X28,LSL #3

0x42cc64 ADD	X12, X19, X12,LSL #3

0x42cc68 FADD	V4.2D, V4.2D, V14.2D

0x42cc6c LDR	D14, [X21, X26,LSL #3]    [31]

0x42cc70 LD1	{V14.D[1]}, [X14]    [2]

0x42cc74 FMOV	X14, D11

0x42cc78 LDR	D11, [X1, X14,LSL #3]    [12]

0x42cc7c FMUL	V14.2D, V14.2D, V14.2D

0x42cc80 LD1	{V11.D[1]}, [X12]    [9]

0x42cc84 FADD	V13.2D, V14.2D, V13.2D

0x42cc88 MOVPRFX	Z14, Z31

0x42cc8c MUL	Z14.D, P0/M, Z14.D, Z10.D

0x42cc90 MUL	Z10.D, P0/M, Z10.D, Z19.D

0x42cc94 FMOV	X14, D14

0x42cc98 FMUL	V4.2D, V4.2D, V11.2D

0x42cc9c MOV	X12, V14.D[1]

0x42cca0 LDR	D11, [X22, X14,LSL #3]    [11]

0x42cca4 LDR	D14, [X3, X14,LSL #3]    [16]

0x42cca8 FMOV	X14, D10

0x42ccac ADD	X7, X7, X12,LSL #3

0x42ccb0 ADD	X12, X16, X12,LSL #3

0x42ccb4 LD1	{V11.D[1]}, [X12]    [8]

0x42ccb8 MOV	X12, V10.D[1]

0x42ccbc LDR	D10, [X1, X14,LSL #3]    [12]

0x42ccc0 LD1	{V14.D[1]}, [X7]    [26]

0x42ccc4 ADD	X12, X19, X12,LSL #3

0x42ccc8 FADD	V11.2D, V14.2D, V11.2D

0x42cccc LD1	{V10.D[1]}, [X12]    [7]

0x42ccd0 FMUL	V10.2D, V11.2D, V10.2D

0x42ccd4 FADD	V11.2D, V12.2D, V10.2D

0x42ccd8 FABS	V10.2D, V10.2D

0x42ccdc FSUB	V11.2D, V11.2D, V4.2D

0x42cce0 FABS	V4.2D, V4.2D

0x42cce4 FMAXNM	V4.2D, V4.2D, V10.2D

0x42cce8 FSQRT	V10.2D, V13.2D

0x42ccec FMAXNM	V4.2D, V4.2D, V9.2D

0x42ccf0 FMUL	V9.2D, V17.2D, V2.D[0]

0x42ccf4 FADD	V17.2D, V17.2D, V17.2D

0x42ccf8 FDIV	V17.2D, V11.2D, V17.2D

0x42ccfc FDIV	V4.2D, V9.2D, V4.2D

0x42cd00 FMOV	V9.2D, #-1.0000000

0x42cd04 FMAXNM	V10.2D, V10.2D, V27.2D

0x42cd08 FDIV	V7.2D, V7.2D, V10.2D

0x42cd0c FDIV	V9.2D, V9.2D, V17.2D

0x42cd10 FCMGT	V17.2D, V29.2D, V17.2D

0x42cd14 FMUL	V9.2D, V9.2D, V3.D[0]

0x42cd18 FMINNM	V9.2D, V9.2D, V8.2D

0x42cd1c BSL	V17.16B, V9.16B, V8.16B

0x42cd20 FMINNM	V4.2D, V4.2D, V17.2D

0x42cd24 FMINNM	V4.2D, V18.2D, V4.2D

0x42cd28 FMINNM	V4.2D, V7.2D, V4.2D

0x42cd2c FMINNM	V25.2D, V4.2D, V25.2D

0x42cd30 DUP	Z4.D, #2

0x42cd34 ADD	V23.2D, V23.2D, V4.2D

0x42cd38 B.NE	42ca40

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 50 - 75

--------------------------------------------------------------------------------

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	calc_dt_kernel(int, int, int, [...]	calc_dt.cpp:82	exec
○	calc_dt(global_variables&, int[...]	calc_dt.cpp:131	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:80	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.12 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.26 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.17
Bottlenecks	P6, P8,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .omp_outlined]
Source	calc_dt.cpp:50-75,context.h:46-46,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	32.00 - 69.48
CQA cycles if no scalar integer	28.50 - 69.48
CQA cycles if FP arith vectorized	25.35 - 69.48
CQA cycles if fully vectorized	25.35 - 69.48
Front-end cycles	23.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	10.75
P3 cycles	10.75
P4 cycles	10.75
P5 cycles	10.75
P6 cycles	32.00
P7 cycles	32.00
P8 cycles	32.00
P9 cycles	32.00
P10 cycles	12.50
P11 cycles	12.17
P12 cycles	12.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	25.35 - 69.48
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	191.00
Nb uops	191.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.75 - 0.81
Nb FLOP add-sub	22.00
Nb FLOP mul	20.00
Nb FLOP fma	0.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.53 - 5.50
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	19.00
Stride indirect	13.00
Vectorization ratio all	47.97
Vectorization ratio load	2.70
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	94.12
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	37.50
Vector-efficiency ratio all	45.29
Vector-efficiency ratio load	27.03
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	76.19
Vector-efficiency ratio add_sub	42.65
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	56.25
Vector-efficiency ratio other	44.19

Metric	Value
CQA speedup if no scalar integer	1.12 - 1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.26 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.17
Bottlenecks	P6, P8,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .omp_outlined]
Source	calc_dt.cpp:50-75,context.h:46-46,context.h:69-69
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	32.00 - 69.48
CQA cycles if no scalar integer	28.50 - 69.48
CQA cycles if FP arith vectorized	25.35 - 69.48
CQA cycles if fully vectorized	25.35 - 69.48
Front-end cycles	23.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	10.75
P3 cycles	10.75
P4 cycles	10.75
P5 cycles	10.75
P6 cycles	32.00
P7 cycles	32.00
P8 cycles	32.00
P9 cycles	32.00
P10 cycles	12.50
P11 cycles	12.17
P12 cycles	12.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	25.35 - 69.48
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	191.00
Nb uops	191.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.75 - 0.81
Nb FLOP add-sub	22.00
Nb FLOP mul	20.00
Nb FLOP fma	0.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.53 - 5.50
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	19.00
Stride indirect	13.00
Vectorization ratio all	47.97
Vectorization ratio load	2.70
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	94.12
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	37.50
Vector-efficiency ratio all	45.29
Vector-efficiency ratio load	27.03
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	76.19
Vector-efficiency ratio add_sub	42.65
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	56.25
Vector-efficiency ratio other	44.19

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Average path: Display a virtual path defined by average values of all real paths

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .omp_outlined]
Source file and lines	calc_dt.cpp:50-75
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50-75
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 45% of vector register length is used (average across all VPU instructions).

Details

47% of VPU instructions are used in vector version (process two or more data elements in vector registers):

2% of VPU loads are used in vector version.
94% of VPU addition or subtraction instructions are used in vector version.
37% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 69.48 to 30.00 cycles (2.32x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 19 occurrence(s)
Irregular (variable stride) or indirect: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 56 FP arithmetical operations:

22: addition or subtraction
20: multiply
12: divide
2: square root

The binary loop is loading 176 bytes.

Arithmetic intensity

Arithmetic intensity is 0.32 FP operations per loaded or stored byte.

General properties

nb instructions	191
nb uops	191
loop length	764
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	0
used d registers	11
used q registers	0
used v registers	24
used z registers	19
nb stack references	0
ADD-SUB / MUL ratio	1.10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.88 cycles
front end	23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	10.75	10.75	10.75	10.75	32.00	32.00	32.00	32.00	12.50	12.17	12.33	0.00	0.00
cycles	0.50	0.50	10.75	10.75	10.75	10.75	32.00	32.00	32.00	32.00	12.50	12.17	12.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	25.35-69.48
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	23.88
Dispatch	32.00
DIV/SQRT	25.35-69.48
Data deps.	2.00
Overall L1	32.00-69.48

Vectorization ratios

INT

all	29%
load	2%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	83%
fma	100%
other	23%

all	76%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	54%

INT+FP

all	47%
load	2%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	37%

Vector efficiency ratios

INT

all	46%
load	27%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	29%
fma	100%
other	50%

all	44%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	38%

INT+FP

all	45%
load	27%
store	NA (no store vectorizable/vectorized instructions)
mul	76%
add-sub	42%
fma	100%
div/sqrt	56%
other	44%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 69.48 cycles. At this rate:

2% of peak load performance is reached (2.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ca40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MOVPRFX Z7, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SDIV Z7.D, P0/M, Z7.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUBS X27, X27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR Z4, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
XTN V10.2S, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MSB Z7.D, P0/M, Z20.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD V17.2S, V21.2S, V10.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (25.0%)
SSHLL V11.2D, V17.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
XTN V9.2S, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOVPRFX Z12, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z13, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P0/M, Z13.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMOV X19, D11	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOVPRFX Z14, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z14.D, P0/M, Z14.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOV X21, V11.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
MOVPRFX Z15, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P0/M, Z15.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z18, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z18.D, P0/M, Z18.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD V7.2S, V22.2S, V9.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (25.0%)
ADD V9.2S, V9.2S, V26.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (25.0%)
ADD X21, X10, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SSHLL V17.2D, V7.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
MOVPRFX Z7, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z7.D, P0/M, Z7.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SSHLL V9.2D, V9.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
FMOV X30, D17	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV X14, V12.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
FMOV X26, D12	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV X16, V13.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
FMOV X1, D13	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D13, [X10, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV X28, V17.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
MOVPRFX Z17, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z17.D, P0/M, Z17.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
UBFM X22, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X9, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X13, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X17, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL Z11.D, P0/M, Z11.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LDR D12, [X9, X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X22, X13, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V13.D[1]}, [X21]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X21, X11, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V12.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X12, X22, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV X16, V14.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
FMOV X22, D14	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D14, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X1, X15, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X17, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X1, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X1, D7	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D4, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1 {V14.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV X12, V7.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
ADD V7.2S, V10.2S, V24.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (25.0%)
SSHLL V10.2D, V7.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
FMINNM V7.2D, V12.2D, V13.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOVPRFX Z12, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMUL V7.2D, V7.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FADD V13.2D, V14.2D, V14.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMOV X7, D12	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV X3, V12.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
LDR D12, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X19, X25, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X25, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V4.D[1]}, [X19]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X19, X11, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X19, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V12.D[1]}, [X25]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X25, X15, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V4.2D, V4.2D, V12.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D12, [X25, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X22, D9	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
ADD X25, X17, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V12.D[1]}, [X16]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV X16, V9.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
LDR D9, [X25, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV X1, V15.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
FDIV V13.2D, V13.2D, V12.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
LDR D12, [X25, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X7, D15	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
ADD X25, X0, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D14, [X25, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X25, X0, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X25, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V14.D[1]}, [X19]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X19, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X19, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X19, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V9.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
LD1 {V12.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X12, X0, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X0, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X22, X4, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X4, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X3, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X2, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V4.2D, V4.2D, V14.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FADD V9.2D, V9.2D, V12.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D12, [X12, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV X12, V17.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
ADD X7, X2, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X7, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X4, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V12.D[1]}, [X1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
FMOV X1, D17	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D17, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X1, D18	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
ADD X3, X4, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V17.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
FMUL V9.2D, V9.2D, V12.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
MOVI V12.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOV X12, V18.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
ADD X19, X7, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X16, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V12.2D, V9.2D, V12.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V9.2D, V9.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V12.2D, V12.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V4.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMAXNM V4.2D, V4.2D, V9.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V9.2D, V17.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V14.2D, V17.2D, V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMAXNM V4.2D, V4.2D, V9.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FDIV V18.2D, V14.2D, V4.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
LDR D4, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D14, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X1, X6, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V4.D[1]}, [X19]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
LD1 {V14.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV X12, V11.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
ADD X19, X6, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X19, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V4.2D, V4.2D, V14.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D14, [X21, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1 {V14.D[1]}, [X14]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
FMOV X14, D11	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D11, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL V14.2D, V14.2D, V14.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
LD1 {V11.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
FADD V13.2D, V14.2D, V13.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOVPRFX Z14, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z14.D, P0/M, Z14.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z10.D, P0/M, Z10.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMOV X14, D14	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
FMUL V4.2D, V4.2D, V11.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
MOV X12, V14.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
LDR D11, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D14, [X3, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X14, D10	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
ADD X7, X7, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X16, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V11.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV X12, V10.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
LDR D10, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1 {V14.D[1]}, [X7]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X12, X19, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V11.2D, V14.2D, V11.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V10.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
FMUL V10.2D, V11.2D, V10.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FADD V11.2D, V12.2D, V10.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V10.2D, V10.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V11.2D, V11.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V4.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMAXNM V4.2D, V4.2D, V10.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSQRT V10.2D, V13.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
FMAXNM V4.2D, V4.2D, V9.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V9.2D, V17.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FADD V17.2D, V17.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FDIV V17.2D, V11.2D, V17.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FDIV V4.2D, V9.2D, V4.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMOV V9.2D, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMAXNM V10.2D, V10.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FDIV V7.2D, V7.2D, V10.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FDIV V9.2D, V9.2D, V17.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FCMGT V17.2D, V29.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V9.2D, V9.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMINNM V9.2D, V9.2D, V8.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V17.16B, V9.16B, V8.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V4.2D, V4.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V4.2D, V18.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V4.2D, V7.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V25.2D, V4.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
DUP Z4.D, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
ADD V23.2D, V23.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
B.NE 42ca40 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .omp_outlined]
Source file and lines	calc_dt.cpp:50-75
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50-75
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 45% of vector register length is used (average across all VPU instructions).

Details

47% of VPU instructions are used in vector version (process two or more data elements in vector registers):

2% of VPU loads are used in vector version.
94% of VPU addition or subtraction instructions are used in vector version.
37% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 69.48 to 30.00 cycles (2.32x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 19 occurrence(s)
Irregular (variable stride) or indirect: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 56 FP arithmetical operations:

22: addition or subtraction
20: multiply
12: divide
2: square root

The binary loop is loading 176 bytes.

Arithmetic intensity

Arithmetic intensity is 0.32 FP operations per loaded or stored byte.

General properties

nb instructions	191
nb uops	191
loop length	764
used w registers	0
used x registers	25
used b registers	0
used h registers	0
used s registers	0
used d registers	11
used q registers	0
used v registers	24
used z registers	19
nb stack references	0
ADD-SUB / MUL ratio	1.10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.88 cycles
front end	23.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	10.75	10.75	10.75	10.75	32.00	32.00	32.00	32.00	12.50	12.17	12.33	0.00	0.00
cycles	0.50	0.50	10.75	10.75	10.75	10.75	32.00	32.00	32.00	32.00	12.50	12.17	12.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	25.35-69.48
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	23.88
Dispatch	32.00
DIV/SQRT	25.35-69.48
Data deps.	2.00
Overall L1	32.00-69.48

Vectorization ratios

INT

all	29%
load	2%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	83%
fma	100%
other	23%

all	76%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	54%

INT+FP

all	47%
load	2%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	94%
fma	100%
div/sqrt	100%
other	37%

Vector efficiency ratios

INT

all	46%
load	27%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	29%
fma	100%
other	50%

all	44%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	50%
other	38%

INT+FP

all	45%
load	27%
store	NA (no store vectorizable/vectorized instructions)
mul	76%
add-sub	42%
fma	100%
div/sqrt	56%
other	44%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 69.48 cycles. At this rate:

2% of peak load performance is reached (2.53 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ca40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MOVPRFX Z7, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SDIV Z7.D, P0/M, Z7.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SUBS X27, X27, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR Z4, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
XTN V10.2S, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MSB Z7.D, P0/M, Z20.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD V17.2S, V21.2S, V10.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (25.0%)
SSHLL V11.2D, V17.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
XTN V9.2S, V7.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOVPRFX Z12, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z13, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P0/M, Z13.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMOV X19, D11	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOVPRFX Z14, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z14.D, P0/M, Z14.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOV X21, V11.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
MOVPRFX Z15, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P0/M, Z15.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z18, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z18.D, P0/M, Z18.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD V7.2S, V22.2S, V9.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (25.0%)
ADD V9.2S, V9.2S, V26.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (25.0%)
ADD X21, X10, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SSHLL V17.2D, V7.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
MOVPRFX Z7, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z7.D, P0/M, Z7.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SSHLL V9.2D, V9.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
FMOV X30, D17	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV X14, V12.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
FMOV X26, D12	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV X16, V13.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
FMOV X1, D13	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D13, [X10, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV X28, V17.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
MOVPRFX Z17, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z17.D, P0/M, Z17.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
UBFM X22, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X9, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X13, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X17, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL Z11.D, P0/M, Z11.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LDR D12, [X9, X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X22, X13, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V13.D[1]}, [X21]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X21, X11, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V12.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X12, X22, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOV X16, V14.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
FMOV X22, D14	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D14, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X1, X15, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X17, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X1, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMOV X1, D7	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D4, [X19, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1 {V14.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV X12, V7.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
ADD V7.2S, V10.2S, V24.2S	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (25.0%)
SSHLL V10.2D, V7.2S, #32	1	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (25.0%)
FMINNM V7.2D, V12.2D, V13.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOVPRFX Z12, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMUL V7.2D, V7.2D, V0.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FADD V13.2D, V14.2D, V14.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMOV X7, D12	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
MOV X3, V12.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
LDR D12, [X19, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X19, X25, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X25, X25, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V4.D[1]}, [X19]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X19, X11, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X19, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V12.D[1]}, [X25]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X25, X15, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V4.2D, V4.2D, V12.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D12, [X25, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X22, D9	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
ADD X25, X17, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V12.D[1]}, [X16]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV X16, V9.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
LDR D9, [X25, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV X1, V15.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
FDIV V13.2D, V13.2D, V12.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
LDR D12, [X25, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X7, D15	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
ADD X25, X0, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D14, [X25, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X25, X0, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X19, X25, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V14.D[1]}, [X19]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X19, X17, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X19, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X19, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V9.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
LD1 {V12.D[1]}, [X3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X12, X0, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X0, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X22, X4, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X4, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X3, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, X2, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMUL V4.2D, V4.2D, V14.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FADD V9.2D, V9.2D, V12.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D12, [X12, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
MOV X12, V17.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
ADD X7, X2, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X7, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X7, X4, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V12.D[1]}, [X1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
FMOV X1, D17	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D17, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X1, D18	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
ADD X3, X4, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V17.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
FMUL V9.2D, V9.2D, V12.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
MOVI V12.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOV X12, V18.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
ADD X19, X7, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X16, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V12.2D, V9.2D, V12.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V9.2D, V9.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V12.2D, V12.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V4.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMAXNM V4.2D, V4.2D, V9.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V9.2D, V17.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMUL V14.2D, V17.2D, V1.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMAXNM V4.2D, V4.2D, V9.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FDIV V18.2D, V14.2D, V4.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
LDR D4, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D14, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X1, X6, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V4.D[1]}, [X19]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
LD1 {V14.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV X12, V11.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
ADD X19, X6, X28,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X19, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V4.2D, V4.2D, V14.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LDR D14, [X21, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1 {V14.D[1]}, [X14]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
FMOV X14, D11	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
LDR D11, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMUL V14.2D, V14.2D, V14.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
LD1 {V11.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
FADD V13.2D, V14.2D, V13.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
MOVPRFX Z14, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z14.D, P0/M, Z14.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z10.D, P0/M, Z10.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMOV X14, D14	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
FMUL V4.2D, V4.2D, V11.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
MOV X12, V14.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
LDR D11, [X22, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LDR D14, [X3, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMOV X14, D10	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (25.0%)
ADD X7, X7, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X16, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1 {V11.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
MOV X12, V10.D[1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (25.0%)
LDR D10, [X1, X14,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1 {V14.D[1]}, [X7]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
ADD X12, X19, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FADD V11.2D, V14.2D, V11.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
LD1 {V10.D[1]}, [X12]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (25.0%)
FMUL V10.2D, V11.2D, V10.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FADD V11.2D, V12.2D, V10.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V10.2D, V10.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSUB V11.2D, V11.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FABS V4.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMAXNM V4.2D, V4.2D, V10.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FSQRT V10.2D, V13.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (50.0%)
FMAXNM V4.2D, V4.2D, V9.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V9.2D, V17.2D, V2.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FADD V17.2D, V17.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FDIV V17.2D, V11.2D, V17.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FDIV V4.2D, V9.2D, V4.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FMOV V9.2D, #-1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMAXNM V10.2D, V10.2D, V27.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FDIV V7.2D, V7.2D, V10.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FDIV V9.2D, V9.2D, V17.2D	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (50.0%)
FCMGT V17.2D, V29.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMUL V9.2D, V9.2D, V3.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (50.0%)
FMINNM V9.2D, V9.2D, V8.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
BSL V17.16B, V9.16B, V8.16B	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V4.2D, V4.2D, V17.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V4.2D, V18.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V4.2D, V7.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
FMINNM V25.2D, V4.2D, V25.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
DUP Z4.D, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
ADD V23.2D, V23.2D, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (50.0%)
B.NE 42ca40 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code