OV - exec - Loop 200

	Loop Id: 200	Module: exec	Source: field_summary.cpp:76-91 [...]	Coverage: 0.34%

0x42e2a0 MOVPRFX	Z11, Z16

0x42e2a4 SXTW	Z11.D, P0/M, Z16.D

0x42e2a8 SUB	X20, X29, #64

0x42e2ac DUP	Z5.D, #8

0x42e2b0 MOVI	V1.2D, #0

0x42e2b4 SUBS	W22, W22, W21

0x42e2b8 LDR	Z0, [X20, #511, MUL VL]    [21]

0x42e2bc SDIV	Z11.D, P0/M, Z11.D, Z24.D

0x42e2c0 MOVPRFX	Z13, Z16

0x42e2c4 MLS	Z13.D, P0/M, Z11.D, Z3.D

0x42e2c8 ADD	Z11.D, Z4.D, Z11.D

0x42e2cc ADD	Z16.D, Z16.D, Z23.D

0x42e2d0 MOVPRFX	Z12, Z11

0x42e2d4 SXTW	Z12.D, P0/M, Z11.D

0x42e2d8 MOVPRFX	Z15, Z6

0x42e2dc MUL	Z15.D, P0/M, Z15.D, Z12.D

0x42e2e0 ADD	Z11.D, Z0.D, Z13.D

0x42e2e4 MOVPRFX	Z13, Z29

0x42e2e8 MUL	Z13.D, P0/M, Z13.D, Z12.D

0x42e2ec ADR	Z27.D, [Z5, Z11.D,SXTW #3]    [3]

0x42e2f0 ADR	Z15.D, [Z28, Z15.D,LSL #3]    [26]

0x42e2f4 ADR	Z13.D, [Z26, Z13.D,LSL #3]    [22]

0x42e2f8 ADR	Z0.D, [Z15, Z11.D,SXTW #3]    [17]

0x42e2fc ADD	Z15.D, Z15.D, Z27.D

0x42e300 ADR	Z14.D, [Z13, Z11.D,SXTW #3]    [9]

0x42e304 ADD	Z13.D, Z13.D, Z27.D

0x42e308 LD1D	{Z0.D}, P0/Z, [V0.D]    [27]

0x42e30c LD1D	{Z15.D}, P0/Z, [V15.D]    [16]

0x42e310 LD1D	{Z14.D}, P0/Z, [V14.D]    [14]

0x42e314 LD1D	{Z13.D}, P0/Z, [V13.D]    [8]

0x42e318 FMUL	Z0.D, Z0.D, Z0.D

0x42e31c FMLA	Z0.D, P0/M, Z14.D, Z14.D

0x42e320 FMUL	Z14.D, Z15.D, Z15.D

0x42e324 ORR	Z15.D, Z12.D, Z12.D

0x42e328 ADD	Z15.D, Z15.D, #1

0x42e32c FMAD	Z0.D, P0/M, Z30.D, Z1.D

0x42e330 FMAD	Z13.D, P0/M, Z13.D, Z14.D

0x42e334 MOVPRFX	Z5, Z29

0x42e338 MUL	Z5.D, P0/M, Z5.D, Z15.D

0x42e33c MUL	Z15.D, P0/M, Z15.D, Z6.D

0x42e340 FMLA	Z0.D, P0/M, Z13.D, Z30.D

0x42e344 ADR	Z13.D, [Z28, Z15.D,LSL #3]    [26]

0x42e348 ADR	Z5.D, [Z26, Z5.D,LSL #3]    [22]

0x42e34c ADR	Z15.D, [Z13, Z11.D,SXTW #3]    [7]

0x42e350 ADR	Z14.D, [Z5, Z11.D,SXTW #3]    [2]

0x42e354 ADD	Z5.D, Z5.D, Z27.D

0x42e358 ADD	Z27.D, Z13.D, Z27.D

0x42e35c MOVPRFX	Z13, Z17

0x42e360 MUL	Z13.D, P0/M, Z13.D, Z12.D

0x42e364 LD1D	{Z15.D}, P0/Z, [V15.D]    [15]

0x42e368 FMUL	Z15.D, Z15.D, Z15.D

0x42e36c LD1D	{Z14.D}, P0/Z, [V14.D]    [12]

0x42e370 LD1D	{Z27.D}, P0/Z, [V27.D]    [25]

0x42e374 LD1D	{Z5.D}, P0/Z, [V5.D]    [1]

0x42e378 FMUL	Z27.D, Z27.D, Z27.D

0x42e37c FMAD	Z14.D, P0/M, Z14.D, Z15.D

0x42e380 MOVPRFX	Z15, Z7

0x42e384 MUL	Z15.D, P0/M, Z15.D, Z12.D

0x42e388 FMAD	Z5.D, P0/M, Z5.D, Z27.D

0x42e38c ADR	Z27.D, [Z31, Z11.D,SXTW #3]    [5]

0x42e390 FMLA	Z0.D, P0/M, Z14.D, Z30.D

0x42e394 ADR	Z14.D, [Z8, Z11.D,SXTW #3]    [6]

0x42e398 ADR	Z27.D, [Z27, Z15.D,LSL #3]    [24]

0x42e39c ADR	Z13.D, [Z14, Z13.D,LSL #3]    [11]

0x42e3a0 FMLA	Z0.D, P0/M, Z5.D, Z30.D

0x42e3a4 LD1D	{Z27.D}, P0/Z, [V27.D]    [23]

0x42e3a8 LD1D	{Z13.D}, P0/Z, [V13.D]    [28]

0x42e3ac FADD	Z2.D, Z27.D, Z2.D

0x42e3b0 FMUL	Z13.D, Z27.D, Z13.D

0x42e3b4 MOVPRFX	Z5, Z13

0x42e3b8 FMUL	Z5.D, P0/M, Z5.D, #0.0000000

0x42e3bc FADD	Z21.D, Z13.D, Z21.D

0x42e3c0 FMLA	Z20.D, P0/M, Z5.D, Z0.D

0x42e3c4 MOVPRFX	Z0, Z18

0x42e3c8 MUL	Z0.D, P0/M, Z0.D, Z12.D

0x42e3cc MUL	Z12.D, P0/M, Z12.D, Z19.D

0x42e3d0 ADR	Z5.D, [Z9, Z11.D,SXTW #3]    [10]

0x42e3d4 ADR	Z0.D, [Z5, Z0.D,LSL #3]    [20]

0x42e3d8 ADR	Z5.D, [Z10, Z11.D,SXTW #3]    [4]

0x42e3dc ADR	Z5.D, [Z5, Z12.D,LSL #3]    [19]

0x42e3e0 LD1D	{Z0.D}, P0/Z, [V0.D]    [13]

0x42e3e4 LD1D	{Z5.D}, P0/Z, [V5.D]    [18]

0x42e3e8 FMLA	Z22.D, P0/M, Z13.D, Z0.D

0x42e3ec FMLA	Z25.D, P0/M, Z27.D, Z5.D

0x42e3f0 B.NE	42e2a0

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp: 76 - 91

--------------------------------------------------------------------------------

76:     for (int idx = (0); idx < ((ymax - ymin + 1) * (xmax - xmin + 1)); idx++) {

77:       const int j = xmin + 1 + idx % (xmax - xmin + 1);

78:       const int k = ymin + 1 + idx / (xmax - xmin + 1);

79:       double vsqrd = 0.0;

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

83:         }

84:       }

85:       double cell_vol = field.volume(j, k);

86:       double cell_mass = cell_vol * field.density0(j, k);

87:       vol += cell_vol;

88:       mass += cell_mass;

89:       ie += cell_mass * field.energy0(j, k);

90:       ke += cell_mass * 0.5 * vsqrd;

91:       press += cell_vol * field.pressure(j, k);

Coverage (%)	Name	Source Location	Module
►98.42+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.27+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	field_summary(global_variables[...]	field_summary.cpp:66	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:105	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source	context.h:69-69,field_summary.cpp:76-91
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	34.00
CQA cycles if no scalar integer	34.00
CQA cycles if FP arith vectorized	34.00
CQA cycles if fully vectorized	27.16
Front-end cycles	10.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	34.00
P7 cycles	34.00
P8 cycles	9.50
P9 cycles	9.50
P10 cycles	4.50
P11 cycles	4.17
P12 cycles	4.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	85.00
Nb uops	85.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.53
Nb FLOP add-sub	8.00
Nb FLOP mul	24.00
Nb FLOP fma	44.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.30
Bytes prefetched	0.00
Bytes loaded	418.13
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	19.00
Stride indirect	9.00
Vectorization ratio all	63.86
Vectorization ratio load	43.33
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	37.93
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	20.00
Vector-efficiency ratio all	81.51
Vector-efficiency ratio load	57.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	53.02
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	88.54

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source	context.h:69-69,field_summary.cpp:76-91
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	34.00
CQA cycles if no scalar integer	34.00
CQA cycles if FP arith vectorized	34.00
CQA cycles if fully vectorized	27.16
Front-end cycles	10.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	34.00
P7 cycles	34.00
P8 cycles	9.50
P9 cycles	9.50
P10 cycles	4.50
P11 cycles	4.17
P12 cycles	4.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	85.00
Nb uops	85.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.53
Nb FLOP add-sub	8.00
Nb FLOP mul	24.00
Nb FLOP fma	44.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.30
Bytes prefetched	0.00
Bytes loaded	418.13
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	19.00
Stride indirect	9.00
Vectorization ratio all	63.86
Vectorization ratio load	43.33
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	37.93
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	20.00
Vector-efficiency ratio all	81.51
Vector-efficiency ratio load	57.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	53.02
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	88.54

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source file and lines	field_summary.cpp:76-91
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76-91

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 81% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 34.00 to 27.16 cycles (1.25x speedup).

Details

63% of VPU instructions are used in vector version (process two or more data elements in vector registers):

43% of VPU loads are used in vector version.
37% of VPU addition or subtraction instructions are used in vector version.
20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 19 occurrence(s)
Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

52: addition or subtraction (44 inside FMA instructions)
68: multiply (44 inside FMA instructions)

The binary loop is loading 418 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	85
nb uops	85
loop length	340
used w registers	2
used x registers	2
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	7
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	0.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	34.00	34.00	6.50	6.50	4.50	4.17	4.33	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	34.00	34.00	9.50	9.50	4.50	4.17	4.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	10.63
Dispatch	34.00
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	34.00

Vectorization ratios

INT

all	53%
load	43%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	63%
load	43%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	37%
fma	100%
div/sqrt	100%
other	20%

Vector efficiency ratios

INT

all	76%
load	57%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	49%
fma	NA (no fma vectorizable/vectorized instructions)
other	89%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	81%
load	57%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	53%
fma	100%
div/sqrt	100%
other	88%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 34.00 cycles. At this rate:

12% of peak load performance is reached (12.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42e2a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MOVPRFX Z11, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z11.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SUB X20, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z5.D, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SUBS W22, W22, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LDR Z0, [X20, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SDIV Z11.D, P0/M, Z11.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z13, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z13.D, P0/M, Z11.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z11.D, Z4.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z16.D, Z16.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z12, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z12.D, P0/M, Z11.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z15, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P0/M, Z15.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z11.D, Z0.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P0/M, Z13.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z27.D, [Z5, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z28, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z26, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z15, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z15.D, Z15.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z14.D, [Z13, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z13.D, Z13.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z15.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z0.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z0.D, P0/M, Z14.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z14.D, Z15.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ORR Z15.D, Z12.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z15.D, Z15.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z0.D, P0/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z13.D, P0/M, Z13.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z5, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P0/M, Z5.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z15.D, P0/M, Z15.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMLA Z0.D, P0/M, Z13.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z13.D, [Z28, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z26, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z13, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z5, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z5.D, Z5.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z27.D, Z13.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P0/M, Z13.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z15.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z15.D, Z15.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z27.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z14.D, P0/M, Z14.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z15, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P0/M, Z15.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMAD Z5.D, P0/M, Z5.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z27.D, [Z31, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMLA Z0.D, P0/M, Z14.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z14.D, [Z8, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z27, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z14, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMLA Z0.D, P0/M, Z5.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z2.D, Z27.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z13.D, Z27.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z5, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z5.D, P0/M, Z5.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z21.D, Z13.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z20.D, P0/M, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z0, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z0.D, P0/M, Z0.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z12.D, P0/M, Z12.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z9, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z5, Z0.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z10, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z5, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z22.D, P0/M, Z13.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z25.D, P0/M, Z27.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
B.NE 42e2a0 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source file and lines	field_summary.cpp:76-91
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76-91

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

63% of VPU instructions are used in vector version (process two or more data elements in vector registers):

43% of VPU loads are used in vector version.
37% of VPU addition or subtraction instructions are used in vector version.
20% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 19 occurrence(s)
Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

52: addition or subtraction (44 inside FMA instructions)
68: multiply (44 inside FMA instructions)

The binary loop is loading 418 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	85
nb uops	85
loop length	340
used w registers	2
used x registers	2
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	7
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	0.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.50	0.50	0.50	34.00	34.00	6.50	6.50	4.50	4.17	4.33	0.00	0.00
cycles	0.50	0.50	0.50	0.50	0.50	0.50	34.00	34.00	9.50	9.50	4.50	4.17	4.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	10.63
Dispatch	34.00
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	34.00

Vectorization ratios

INT

all	53%
load	43%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	63%
load	43%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	37%
fma	100%
div/sqrt	100%
other	20%

Vector efficiency ratios

INT

all	76%
load	57%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	49%
fma	NA (no fma vectorizable/vectorized instructions)
other	89%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	81%
load	57%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	53%
fma	100%
div/sqrt	100%
other	88%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 34.00 cycles. At this rate:

12% of peak load performance is reached (12.30 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42e2a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MOVPRFX Z11, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z11.D, P0/M, Z16.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SUB X20, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z5.D, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V1.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
SUBS W22, W22, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LDR Z0, [X20, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SDIV Z11.D, P0/M, Z11.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z13, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z13.D, P0/M, Z11.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z11.D, Z4.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z16.D, Z16.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z12, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z12.D, P0/M, Z11.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z15, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P0/M, Z15.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z11.D, Z0.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P0/M, Z13.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z27.D, [Z5, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z28, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z26, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z15, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z15.D, Z15.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z14.D, [Z13, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z13.D, Z13.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z15.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z0.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z0.D, P0/M, Z14.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z14.D, Z15.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ORR Z15.D, Z12.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z15.D, Z15.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z0.D, P0/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z13.D, P0/M, Z13.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z5, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P0/M, Z5.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z15.D, P0/M, Z15.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMLA Z0.D, P0/M, Z13.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z13.D, [Z28, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z26, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z13, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z5, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z5.D, Z5.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z27.D, Z13.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P0/M, Z13.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z15.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z15.D, Z15.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z27.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z14.D, P0/M, Z14.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z15, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P0/M, Z15.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMAD Z5.D, P0/M, Z5.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z27.D, [Z31, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMLA Z0.D, P0/M, Z14.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z14.D, [Z8, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z27, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z14, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMLA Z0.D, P0/M, Z5.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z2.D, Z27.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z13.D, Z27.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z5, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z5.D, P0/M, Z5.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z21.D, Z13.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z20.D, P0/M, Z5.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z0, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z0.D, P0/M, Z0.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z12.D, P0/M, Z12.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z9, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z5, Z0.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z10, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z5, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z22.D, P0/M, Z13.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z25.D, P0/M, Z27.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
B.NE 42e2a0 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code