OV - exec - Loop 206

	Loop Id: 206	Module: exec	Source: generate_chunk.cpp:86-98 [...]	Coverage: 0.03%

0x42f680 SEL	Z24.D, P1, Z1.D, Z6.D

0x42f684 LDR	D26, [X9, X8,LSL #3]    [12]

0x42f688 ADD	X2, X2, X18

0x42f68c SDIVR	Z24.D, P0/M, Z24.D, Z23.D

0x42f690 DUP	Z26.D, Z26.D[0]

0x42f694 MOVPRFX	Z25, Z24

0x42f698 MUL	Z25.D, P0/M, Z25.D, Z1.D

0x42f69c SUB	Z25.D, Z23.D, Z25.D

0x42f6a0 ADD	Z23.D, Z23.D, Z7.D

0x42f6a4 LSL	Z27.D, Z25.D, #32

0x42f6a8 ADR	Z29.D, [Z19, Z25.D,SXTW #3]    [22]

0x42f6ac ADD	Z27.D, Z27.D, Z16.D

0x42f6b0 ASR	Z27.D, Z27.D, #-31

0x42f6b4 LD1D	{Z27.D}, P1/Z, [X15, Z27.D]    [26]

0x42f6b8 FCMGE	P1.D, P1/Z, Z27.D, Z26.D

0x42f6bc LD1D	{Z26.D}, P1/Z, [X15, Z25.D,SXTW #3]    [26]

0x42f6c0 LD1D	{Z27.D}, P1/Z, [X6, Z18.D,LSL #3]    [6]

0x42f6c4 FCMGT	P1.D, P1/Z, Z27.D, Z26.D

0x42f6c8 LSL	Z26.D, Z24.D, #32

0x42f6cc LDR	D27, [X10]    [18]

0x42f6d0 ADD	Z26.D, Z26.D, Z16.D

0x42f6d4 ASR	Z26.D, Z26.D, #-31

0x42f6d8 LD1D	{Z26.D}, P1/Z, [X16, Z26.D]    [29]

0x42f6dc DUP	Z27.D, Z27.D[0]

0x42f6e0 FCMGE	P1.D, P1/Z, Z26.D, Z27.D

0x42f6e4 LD1D	{Z26.D}, P1/Z, [X16, Z24.D,SXTW #3]    [29]

0x42f6e8 LD1D	{Z27.D}, P1/Z, [X5, Z18.D,LSL #3]    [2]

0x42f6ec FCMGT	P1.D, P1/Z, Z27.D, Z26.D

0x42f6f0 MOVPRFX	Z26, Z24

0x42f6f4 SXTW	Z26.D, P0/M, Z24.D

0x42f6f8 MUL	Z24.D, P0/M, Z24.D, Z1.D

0x42f6fc LD1D	{Z27.D}, P1/Z, [X11, Z18.D,LSL #3]    [20]

0x42f700 MOVPRFX	Z28, Z2

0x42f704 MUL	Z28.D, P0/M, Z28.D, Z26.D

0x42f708 SUB	Z24.D, Z0.D, Z24.D

0x42f70c ADD	Z0.D, Z0.D, Z7.D

0x42f710 ADR	Z28.D, [Z29, Z28.D,LSL #3]    [24]

0x42f714 ADR	Z29.D, [Z20, Z25.D,SXTW #3]    [7]

0x42f718 SXTW	Z25.D, P0/M, Z25.D

0x42f71c ST1D	{Z27.D}, P1, [V28.D]    [28]

0x42f720 MOVPRFX	Z28, Z3

0x42f724 MUL	Z28.D, P0/M, Z28.D, Z26.D

0x42f728 LD1D	{Z27.D}, P1/Z, [X12, Z18.D,LSL #3]    [21]

0x42f72c ADR	Z28.D, [Z29, Z28.D,LSL #3]    [31]

0x42f730 MOVPRFX	Z29, Z24

0x42f734 SXTW	Z29.D, P0/M, Z24.D

0x42f738 CMPGE	P2.D, P1/Z, Z25.D, Z29.D

0x42f73c ST1D	{Z27.D}, P1, [V28.D]    [27]

0x42f740 MOVPRFX	Z27, Z4

0x42f744 MUL	Z27.D, P0/M, Z27.D, Z26.D

0x42f748 ADR	Z27.D, [Z21, Z27.D,LSL #3]    [10]

0x42f74c ADR	Z30.D, [Z27, Z24.D,SXTW #3]    [5]

0x42f750 LD1D	{Z28.D}, P1/Z, [X13, Z18.D,LSL #3]    [23]

0x42f754 ST1D	{Z28.D}, P1, [V30.D]    [9]

0x42f758 MOVPRFX	Z30, Z5

0x42f75c MUL	Z30.D, P0/M, Z30.D, Z26.D

0x42f760 ADD	Z26.D, Z26.D, #1

0x42f764 LD1D	{Z28.D}, P1/Z, [X14, Z18.D,LSL #3]    [25]

0x42f768 ADR	Z30.D, [Z22, Z30.D,LSL #3]    [13]

0x42f76c ADR	Z31.D, [Z30, Z24.D,SXTW #3]    [8]

0x42f770 ST1D	{Z28.D}, P1, [V31.D]    [11]

0x42f774 ADR	Z28.D, [Z17, Z24.D,SXTW #3]    [19]

0x42f778 LD1D	{Z25.D}, P2/Z, [X13, Z18.D,LSL #3]    [23]

0x42f77c ADD	Z27.D, Z27.D, Z28.D

0x42f780 ST1D	{Z25.D}, P2, [V27.D]    [4]

0x42f784 ADD	Z27.D, Z30.D, Z28.D

0x42f788 LD1D	{Z25.D}, P2/Z, [X14, Z18.D,LSL #3]    [25]

0x42f78c ST1D	{Z25.D}, P2, [V27.D]    [3]

0x42f790 MOVPRFX	Z25, Z4

0x42f794 MUL	Z25.D, P0/M, Z25.D, Z26.D

0x42f798 MUL	Z26.D, P0/M, Z26.D, Z5.D

0x42f79c LD1D	{Z27.D}, P1/Z, [X13, Z18.D,LSL #3]    [23]

0x42f7a0 ADR	Z25.D, [Z21, Z25.D,LSL #3]    [10]

0x42f7a4 ADR	Z26.D, [Z22, Z26.D,LSL #3]    [13]

0x42f7a8 ADR	Z29.D, [Z25, Z24.D,SXTW #3]    [17]

0x42f7ac ADR	Z24.D, [Z26, Z24.D,SXTW #3]    [1]

0x42f7b0 ADD	Z25.D, Z25.D, Z28.D

0x42f7b4 ST1D	{Z27.D}, P1, [V29.D]    [30]

0x42f7b8 LD1D	{Z27.D}, P1/Z, [X14, Z18.D,LSL #3]    [25]

0x42f7bc ST1D	{Z27.D}, P1, [V24.D]    [14]

0x42f7c0 WHILELO	P1.D, X2, X4

0x42f7c4 LD1D	{Z24.D}, P2/Z, [X13, Z18.D,LSL #3]    [23]

0x42f7c8 ST1D	{Z24.D}, P2, [V25.D]    [16]

0x42f7cc ADD	Z25.D, Z26.D, Z28.D

0x42f7d0 LD1D	{Z24.D}, P2/Z, [X14, Z18.D,LSL #3]    [25]

0x42f7d4 ST1D	{Z24.D}, P2, [V25.D]    [15]

0x42f7d8 B.MI	42f680

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 86 - 98

--------------------------------------------------------------------------------

86:     for (int j = (0); j < (yrange); j++) {

87:       for (int i = (0); i < (xrange); i++) {

88:         double x_cent = state_xmin[state];

89:         double y_cent = state_ymin[state];

90:         if (state_geometry[state] == g_rect) {

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	stl_vector.h:735	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.21
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	generate_chunk(int, global_variables&) [clone .omp_outlined.1]
Source	context.h:46-46,context.h:69-69,generate_chunk.cpp:86-98
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	28.00
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	23.13
Front-end cycles	10.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	2.00
P5 cycles	0.25
P6 cycles	28.00
P7 cycles	28.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	13.00
P11 cycles	13.00
P12 cycles	2.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	87.00
Nb uops	87.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.77
Bytes prefetched	0.00
Bytes loaded	513.63
Bytes stored	320.00
Stride 0	8.00
Stride 1	0.00
Stride n	0.00
Stride unknown	21.00
Stride indirect	2.00
Vectorization ratio all	71.76
Vectorization ratio load	51.61
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	44.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	65.22
Vector-efficiency ratio all	85.88
Vector-efficiency ratio load	63.71
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	58.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.21
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	generate_chunk(int, global_variables&) [clone .omp_outlined.1]
Source	context.h:46-46,context.h:69-69,generate_chunk.cpp:86-98
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	28.00
CQA cycles if no scalar integer	28.00
CQA cycles if FP arith vectorized	28.00
CQA cycles if fully vectorized	23.13
Front-end cycles	10.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	2.00
P5 cycles	0.25
P6 cycles	28.00
P7 cycles	28.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	13.00
P11 cycles	13.00
P12 cycles	2.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	87.00
Nb uops	87.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	29.77
Bytes prefetched	0.00
Bytes loaded	513.63
Bytes stored	320.00
Stride 0	8.00
Stride 1	0.00
Stride n	0.00
Stride unknown	21.00
Stride indirect	2.00
Vectorization ratio all	71.76
Vectorization ratio load	51.61
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	44.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	65.22
Vector-efficiency ratio all	85.88
Vector-efficiency ratio load	63.71
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	58.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	generate_chunk(int, global_variables&) [clone .omp_outlined.1]
Source file and lines	generate_chunk.cpp:86-98
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:86-98

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 28.00 to 23.12 cycles (1.21x speedup).

Details

71% of VPU instructions are used in vector version (process two or more data elements in vector registers):

51% of VPU loads are used in vector version.
44% of VPU addition or subtraction instructions are used in vector version.
65% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 21 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 513 bytes. The binary loop is storing 320 bytes.

General properties

nb instructions	87
nb uops	87
loop length	348
used w registers	0
used x registers	14
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	7
used z registers	24
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.88 cycles
front end	10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	28.00	28.00	5.00	5.00	13.00	13.00	2.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	28.00	28.00	5.00	5.00	13.00	13.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	10.88
Dispatch	28.00
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	28.00

Vectorization ratios

INT

all	70%
load	51%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	71%
load	51%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	65%

Vector efficiency ratios

INT

all	85%
load	63%
store	100%
mul	100%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	85%
load	63%
store	100%
mul	100%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

19% of peak load performance is reached (18.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.43 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42f680

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z24.D, P1, Z1.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR D26, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X2, X2, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SDIVR Z24.D, P0/M, Z24.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DUP Z26.D, Z26.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z25.D, P0/M, Z25.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SUB Z25.D, Z23.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z23.D, Z23.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LSL Z27.D, Z25.D, #32	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADR Z29.D, [Z19, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z27.D, Z27.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ASR Z27.D, Z27.D, #-31	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X15, Z27.D]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FCMGE P1.D, P1/Z, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X15, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X6, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FCMGT P1.D, P1/Z, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LSL Z26.D, Z24.D, #32	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LDR D27, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD Z26.D, Z26.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ASR Z26.D, Z26.D, #-31	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X16, Z26.D]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
DUP Z27.D, Z27.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCMGE P1.D, P1/Z, Z26.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X16, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X5, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FCMGT P1.D, P1/Z, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z26, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z26.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MUL Z24.D, P0/M, Z24.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X11, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z28, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z28.D, P0/M, Z28.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SUB Z24.D, Z0.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z0.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z28.D, [Z29, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z20, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
SXTW Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ST1D {Z27.D}, P1, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z28, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z28.D, P0/M, Z28.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X12, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z28.D, [Z29, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z29, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z29.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
CMPGE P2.D, P1/Z, Z25.D, Z29.D	1	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
ST1D {Z27.D}, P1, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z27, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z27.D, [Z21, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z27, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z28.D}, P1/Z, [X13, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z28.D}, P1, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z30, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z30.D, P0/M, Z30.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z26.D, Z26.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z28.D}, P1/Z, [X14, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z30.D, [Z22, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z30, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z28.D}, P1, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
ADR Z28.D, [Z17, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z25.D}, P2/Z, [X13, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z27.D, Z27.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z25.D}, P2, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
ADD Z27.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P2/Z, [X14, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z25.D}, P2, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z25, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z25.D, P0/M, Z25.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z26.D, P0/M, Z26.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X13, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z25.D, [Z21, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z22, Z26.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z25, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z24.D, [Z26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z25.D, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z27.D}, P1, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X14, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z27.D}, P1, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X2, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LD1D {Z24.D}, P2/Z, [X13, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z24.D}, P2, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
ADD Z25.D, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X14, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z24.D}, P2, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
B.MI 42f680 <_Z14generate_chunkiR16global_variables.omp_outlined.1+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	generate_chunk(int, global_variables&) [clone .omp_outlined.1]
Source file and lines	generate_chunk.cpp:86-98
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:86-98

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

71% of VPU instructions are used in vector version (process two or more data elements in vector registers):

51% of VPU loads are used in vector version.
44% of VPU addition or subtraction instructions are used in vector version.
65% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 21 occurrence(s)
Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 513 bytes. The binary loop is storing 320 bytes.

General properties

nb instructions	87
nb uops	87
loop length	348
used w registers	0
used x registers	14
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	7
used z registers	24
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.88 cycles
front end	10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	28.00	28.00	5.00	5.00	13.00	13.00	2.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	28.00	28.00	5.00	5.00	13.00	13.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	10.88
Dispatch	28.00
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	28.00

Vectorization ratios

INT

all	70%
load	51%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	60%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	71%
load	51%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	65%

Vector efficiency ratios

INT

all	85%
load	63%
store	100%
mul	100%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	85%
load	63%
store	100%
mul	100%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

19% of peak load performance is reached (18.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.43 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42f680

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z24.D, P1, Z1.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR D26, [X9, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X2, X2, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
SDIVR Z24.D, P0/M, Z24.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
DUP Z26.D, Z26.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z25, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z25.D, P0/M, Z25.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SUB Z25.D, Z23.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z23.D, Z23.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LSL Z27.D, Z25.D, #32	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADR Z29.D, [Z19, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z27.D, Z27.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ASR Z27.D, Z27.D, #-31	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X15, Z27.D]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FCMGE P1.D, P1/Z, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X15, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X6, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FCMGT P1.D, P1/Z, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LSL Z26.D, Z24.D, #32	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LDR D27, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD Z26.D, Z26.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ASR Z26.D, Z26.D, #-31	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X16, Z26.D]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
DUP Z27.D, Z27.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCMGE P1.D, P1/Z, Z26.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z26.D}, P1/Z, [X16, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X5, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FCMGT P1.D, P1/Z, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z26, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z26.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MUL Z24.D, P0/M, Z24.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X11, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z28, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z28.D, P0/M, Z28.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SUB Z24.D, Z0.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z0.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z28.D, [Z29, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z20, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
SXTW Z25.D, P0/M, Z25.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ST1D {Z27.D}, P1, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z28, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z28.D, P0/M, Z28.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X12, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z28.D, [Z29, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z29, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z29.D, P0/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
CMPGE P2.D, P1/Z, Z25.D, Z29.D	1	0	0	0	0	1	0	1	0	0	0	0	0	0	4	1	vect (100.0%)
ST1D {Z27.D}, P1, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z27, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z27.D, [Z21, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z27, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z28.D}, P1/Z, [X13, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z28.D}, P1, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z30, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z30.D, P0/M, Z30.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z26.D, Z26.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z28.D}, P1/Z, [X14, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z30.D, [Z22, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z30, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z28.D}, P1, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
ADR Z28.D, [Z17, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z25.D}, P2/Z, [X13, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z27.D, Z27.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z25.D}, P2, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
ADD Z27.D, Z30.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z25.D}, P2/Z, [X14, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z25.D}, P2, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z25, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z25.D, P0/M, Z25.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z26.D, P0/M, Z26.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X13, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z25.D, [Z21, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z22, Z26.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z25, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z24.D, [Z26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z25.D, Z25.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ST1D {Z27.D}, P1, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [X14, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z27.D}, P1, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X2, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LD1D {Z24.D}, P2/Z, [X13, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z24.D}, P2, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
ADD Z25.D, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z24.D}, P2/Z, [X14, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ST1D {Z24.D}, P2, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
B.MI 42f680 <_Z14generate_chunkiR16global_variables.omp_outlined.1+0x520>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code