OV - exec - Loop 254

	Loop Id: 254	Module: exec	Source: PdV.cpp:70-83 [...]	Coverage: 7.77%

0x434120 DUP	Z0.D, #1

0x434124 SUB	X17, X29, #64

0x434128 ADD	X16, X16, X14

0x43412c LDR	Z3, [X17, #511, MUL VL]    [55]

0x434130 LDR	Z26, [X17, #510, MUL VL]    [55]

0x434134 LDR	Z31, [X17, #508, MUL VL]    [55]

0x434138 SEL	Z11.D, P1, Z1.D, Z0.D

0x43413c SDIVR	Z11.D, P0/M, Z11.D, Z2.D

0x434140 ADD	Z13.D, Z3.D, Z11.D

0x434144 LDR	Z3, [X17, #507, MUL VL]    [55]

0x434148 MOVPRFX	Z0, Z2

0x43414c MLS	Z0.D, P0/M, Z11.D, Z1.D

0x434150 ADD	Z2.D, Z2.D, Z14.D

0x434154 MOVPRFX	Z15, Z13

0x434158 SXTW	Z15.D, P0/M, Z13.D

0x43415c MOVPRFX	Z7, Z5

0x434160 MUL	Z7.D, P0/M, Z7.D, Z15.D

0x434164 MOVPRFX	Z18, Z21

0x434168 MUL	Z18.D, P0/M, Z18.D, Z15.D

0x43416c MOVPRFX	Z6, Z3

0x434170 MUL	Z6.D, P0/M, Z6.D, Z15.D

0x434174 LDR	Z3, [X17, #509, MUL VL]    [55]

0x434178 ADD	Z11.D, Z11.D, Z3.D

0x43417c MOVPRFX	Z13, Z11

0x434180 SXTW	Z13.D, P0/M, Z11.D

0x434184 ADD	Z11.D, Z26.D, Z0.D

0x434188 ADD	Z0.D, Z0.D, Z31.D

0x43418c MOVPRFX	Z4, Z5

0x434190 MUL	Z4.D, P0/M, Z4.D, Z13.D

0x434194 ADR	Z27.D, [Z17, Z11.D,SXTW #3]    [40]

0x434198 MOVPRFX	Z3, Z21

0x43419c MUL	Z3.D, P0/M, Z3.D, Z13.D

0x4341a0 ADR	Z26.D, [Z16, Z11.D,SXTW #3]    [26]

0x4341a4 ADR	Z29.D, [Z20, Z11.D,SXTW #3]    [8]

0x4341a8 ADR	Z31.D, [Z16, Z0.D,SXTW #3]    [26]

0x4341ac ADR	Z28.D, [Z27, Z7.D,LSL #3]    [44]

0x4341b0 ADR	Z26.D, [Z26, Z6.D,LSL #3]    [30]

0x4341b4 ADR	Z30.D, [Z29, Z18.D,LSL #3]    [52]

0x4341b8 ADR	Z6.D, [Z31, Z6.D,LSL #3]    [17]

0x4341bc ADR	Z31.D, [Z17, Z0.D,SXTW #3]    [40]

0x4341c0 LD1D	{Z28.D}, P1/Z, [V28.D]    [49]

0x4341c4 ADR	Z7.D, [Z31, Z7.D,LSL #3]    [16]

0x4341c8 ADR	Z27.D, [Z27, Z4.D,LSL #3]    [44]

0x4341cc ADR	Z29.D, [Z29, Z3.D,LSL #3]    [52]

0x4341d0 ADR	Z4.D, [Z31, Z4.D,LSL #3]    [16]

0x4341d4 LD1D	{Z30.D}, P1/Z, [V30.D]    [11]

0x4341d8 ADR	Z31.D, [Z20, Z0.D,SXTW #3]    [8]

0x4341dc ADR	Z18.D, [Z31, Z18.D,LSL #3]    [15]

0x4341e0 ADR	Z3.D, [Z31, Z3.D,LSL #3]    [15]

0x4341e4 LD1D	{Z27.D}, P1/Z, [V27.D]    [43]

0x4341e8 LD1D	{Z29.D}, P1/Z, [V29.D]    [51]

0x4341ec LD1D	{Z7.D}, P1/Z, [V7.D]    [14]

0x4341f0 LD1D	{Z4.D}, P1/Z, [V4.D]    [2]

0x4341f4 LD1D	{Z26.D}, P1/Z, [V26.D]    [29]

0x4341f8 LD1D	{Z6.D}, P1/Z, [V6.D]    [6]

0x4341fc LD1D	{Z18.D}, P1/Z, [V18.D]    [47]

0x434200 LD1D	{Z3.D}, P1/Z, [V3.D]    [60]

0x434204 FADD	Z27.D, Z28.D, Z27.D

0x434208 MOVPRFX	Z28, Z22

0x43420c MUL	Z28.D, P0/M, Z28.D, Z15.D

0x434210 FADD	Z4.D, Z7.D, Z4.D

0x434214 ADR	Z7.D, [Z24, Z0.D,SXTW #3]    [19]

0x434218 ADR	Z0.D, [Z25, Z0.D,SXTW #3]    [23]

0x43421c FADD	Z27.D, Z27.D, Z30.D

0x434220 FADD	Z4.D, Z4.D, Z18.D

0x434224 ADR	Z18.D, [Z25, Z11.D,SXTW #3]    [23]

0x434228 FADD	Z27.D, Z27.D, Z29.D

0x43422c ADR	Z29.D, [Z24, Z11.D,SXTW #3]    [19]

0x434230 FADD	Z3.D, Z4.D, Z3.D

0x434234 ADR	Z30.D, [Z29, Z28.D,LSL #3]    [50]

0x434238 FMUL	Z26.D, Z26.D, Z27.D

0x43423c ADR	Z27.D, [Z7, Z28.D,LSL #3]    [13]

0x434240 FMUL	Z3.D, Z6.D, Z3.D

0x434244 MOVPRFX	Z6, Z23

0x434248 MUL	Z6.D, P0/M, Z6.D, Z15.D

0x43424c LD1D	{Z30.D}, P1/Z, [V30.D]    [10]

0x434250 LD1D	{Z27.D}, P1/Z, [V27.D]    [42]

0x434254 FMUL	Z3.D, Z3.D, Z12.D

0x434258 FADD	Z4.D, Z30.D, Z27.D

0x43425c ADR	Z27.D, [Z18, Z6.D,LSL #3]    [46]

0x434260 ADR	Z6.D, [Z0, Z6.D,LSL #3]    [1]

0x434264 LD1D	{Z27.D}, P1/Z, [V27.D]    [41]

0x434268 LD1D	{Z6.D}, P1/Z, [V6.D]    [5]

0x43426c FADD	Z4.D, Z4.D, Z27.D

0x434270 MOVPRFX	Z27, Z19

0x434274 MUL	Z27.D, P0/M, Z27.D, Z15.D

0x434278 FADD	Z4.D, Z4.D, Z6.D

0x43427c LDR	Z6, [X17, #506, MUL VL]    [55]

0x434280 ADR	Z6.D, [Z6, Z11.D,SXTW #3]    [4]

0x434284 ADR	Z27.D, [Z6, Z27.D,LSL #3]    [34]

0x434288 LD1D	{Z27.D}, P1/Z, [V27.D]    [54]

0x43428c FMUL	Z4.D, Z27.D, Z4.D

0x434290 MOVPRFX	Z27, Z19

0x434294 MUL	Z27.D, P0/M, Z27.D, Z13.D

0x434298 FMUL	Z4.D, Z4.D, Z12.D

0x43429c ADR	Z6.D, [Z6, Z27.D,LSL #3]    [34]

0x4342a0 MOVPRFX	Z27, Z22

0x4342a4 MUL	Z27.D, P0/M, Z27.D, Z13.D

0x4342a8 MUL	Z13.D, P0/M, Z13.D, Z23.D

0x4342ac ADR	Z28.D, [Z29, Z27.D,LSL #3]    [50]

0x4342b0 ADR	Z7.D, [Z7, Z27.D,LSL #3]    [13]

0x4342b4 ADR	Z18.D, [Z18, Z13.D,LSL #3]    [46]

0x4342b8 ADR	Z0.D, [Z0, Z13.D,LSL #3]    [1]

0x4342bc LD1D	{Z6.D}, P1/Z, [V6.D]    [33]

0x4342c0 LD1D	{Z27.D}, P1/Z, [V28.D]    [48]

0x4342c4 LD1D	{Z7.D}, P1/Z, [V7.D]    [12]

0x4342c8 LD1D	{Z18.D}, P1/Z, [V18.D]    [45]

0x4342cc LD1D	{Z0.D}, P1/Z, [V0.D]    [53]

0x4342d0 FADD	Z7.D, Z27.D, Z7.D

0x4342d4 FADD	Z7.D, Z7.D, Z18.D

0x4342d8 FMUL	Z18.D, Z26.D, Z12.D

0x4342dc LDR	D26, [X8]    [56]

0x4342e0 FADD	Z0.D, Z7.D, Z0.D

0x4342e4 DUP	Z7.D, X9

0x4342e8 FMUL	Z0.D, Z6.D, Z0.D

0x4342ec ADR	Z6.D, [Z10, Z11.D,SXTW #3]    [7]

0x4342f0 ADR	Z7.D, [Z7, Z11.D,SXTW #3]    [39]

0x4342f4 DUP	Z26.D, Z26.D[0]

0x4342f8 FMUL	Z0.D, Z0.D, Z12.D

0x4342fc FMUL	Z18.D, Z26.D, Z18.D

0x434300 FMUL	Z3.D, Z26.D, Z3.D

0x434304 FMUL	Z4.D, Z26.D, Z4.D

0x434308 FMUL	Z0.D, Z26.D, Z0.D

0x43430c DUP	Z26.D, X10

0x434310 FSUB	Z3.D, Z3.D, Z18.D

0x434314 LDR	Z18, [X17, #502, MUL VL]    [55]

0x434318 FADD	Z0.D, Z3.D, Z0.D

0x43431c LDR	Z3, [X17, #505, MUL VL]    [55]

0x434320 ADR	Z26.D, [Z26, Z11.D,SXTW #3]    [28]

0x434324 FSUB	Z0.D, Z0.D, Z4.D

0x434328 ADR	Z4.D, [Z9, Z11.D,SXTW #3]    [18]

0x43432c MUL	Z18.D, P0/M, Z18.D, Z15.D

0x434330 MUL	Z3.D, P0/M, Z3.D, Z15.D

0x434334 ADR	Z18.D, [Z26, Z18.D,LSL #3]    [27]

0x434338 ADR	Z3.D, [Z4, Z3.D,LSL #3]    [25]

0x43433c LDR	Z4, [X17, #504, MUL VL]    [55]

0x434340 LD1D	{Z18.D}, P1/Z, [V18.D]    [59]

0x434344 LD1D	{Z3.D}, P1/Z, [V3.D]    [22]

0x434348 MUL	Z4.D, P0/M, Z4.D, Z15.D

0x43434c ADR	Z4.D, [Z6, Z4.D,LSL #3]    [32]

0x434350 LDR	Z6, [X17, #503, MUL VL]    [55]

0x434354 LD1D	{Z4.D}, P1/Z, [V4.D]    [24]

0x434358 MUL	Z6.D, P0/M, Z6.D, Z15.D

0x43435c ADR	Z6.D, [Z7, Z6.D,LSL #3]    [38]

0x434360 LD1D	{Z7.D}, P1/Z, [V6.D]    [31]

0x434364 FDIV	Z4.D, P0/M, Z4.D, Z7.D

0x434368 FDIVR	Z7.D, P0/M, Z7.D, Z18.D

0x43436c FDUP	Z18.D, #112

0x434370 FDIV	Z18.D, P0/M, Z18.D, Z3.D

0x434374 FADD	Z4.D, Z4.D, Z7.D

0x434378 LDR	Z7, [X17, #501, MUL VL]    [55]

0x43437c FMUL	Z4.D, Z0.D, Z4.D

0x434380 FADD	Z0.D, Z3.D, Z0.D

0x434384 FDIVR	Z0.D, P0/M, Z0.D, Z3.D

0x434388 FMUL	Z4.D, Z18.D, Z4.D

0x43438c DUP	Z18.D, X11

0x434390 MUL	Z7.D, P0/M, Z7.D, Z15.D

0x434394 ADR	Z18.D, [Z18, Z11.D,SXTW #3]    [58]

0x434398 ADR	Z7.D, [Z18, Z7.D,LSL #3]    [57]

0x43439c LDR	Z18, [X17, #500, MUL VL]    [55]

0x4343a0 LD1D	{Z7.D}, P1/Z, [V7.D]    [37]

0x4343a4 MUL	Z18.D, P0/M, Z18.D, Z15.D

0x4343a8 MUL	Z15.D, P0/M, Z15.D, Z8.D

0x4343ac FSUB	Z4.D, Z7.D, Z4.D

0x4343b0 DUP	Z7.D, X12

0x4343b4 ADR	Z7.D, [Z7, Z11.D,SXTW #3]    [36]

0x4343b8 ADR	Z7.D, [Z7, Z18.D,LSL #3]    [35]

0x4343bc ST1D	{Z4.D}, P1, [V7.D]    [9]

0x4343c0 LD1D	{Z3.D}, P1/Z, [V6.D]    [31]

0x4343c4 FMUL	Z0.D, Z0.D, Z3.D

0x4343c8 DUP	Z3.D, X13

0x4343cc ADR	Z3.D, [Z3, Z11.D,SXTW #3]    [21]

0x4343d0 ADR	Z3.D, [Z3, Z15.D,LSL #3]    [20]

0x4343d4 ST1D	{Z0.D}, P1, [V3.D]    [3]

0x4343d8 WHILELO	P1.D, X16, X15

0x4343dc B.MI	434120

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 70 - 83

--------------------------------------------------------------------------------

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►98.37+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.63+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	PdV(global_variables&, bool)	PdV.cpp:99	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.40 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P6, P8,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.1]
Source	PdV.cpp:70-83,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	63.00 - 76.34
CQA cycles if no scalar integer	63.00 - 76.34
CQA cycles if FP arith vectorized	63.00 - 76.34
CQA cycles if fully vectorized	45.16 - 76.34
Front-end cycles	22.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	6.00
P5 cycles	0.50
P6 cycles	63.00
P7 cycles	63.00
P8 cycles	16.50
P9 cycles	16.50
P10 cycles	13.67
P11 cycles	13.67
P12 cycles	13.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	28.85 - 76.34
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	176.00
Nb uops	176.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.35 - 1.94
Nb FLOP add-sub	72.00
Nb FLOP mul	60.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.84 - 20.41
Bytes prefetched	0.00
Bytes loaded	1221.63
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	46.00
Stride indirect	13.00
Vectorization ratio all	61.63
Vectorization ratio load	45.24
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	34.78
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	16.67
Vector-efficiency ratio all	76.64
Vector-efficiency ratio load	58.93
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	51.09
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	76.30

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.40 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	P6, P8,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.1]
Source	PdV.cpp:70-83,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	63.00 - 76.34
CQA cycles if no scalar integer	63.00 - 76.34
CQA cycles if FP arith vectorized	63.00 - 76.34
CQA cycles if fully vectorized	45.16 - 76.34
Front-end cycles	22.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	6.00
P5 cycles	0.50
P6 cycles	63.00
P7 cycles	63.00
P8 cycles	16.50
P9 cycles	16.50
P10 cycles	13.67
P11 cycles	13.67
P12 cycles	13.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	28.85 - 76.34
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	176.00
Nb uops	176.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.35 - 1.94
Nb FLOP add-sub	72.00
Nb FLOP mul	60.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.84 - 20.41
Bytes prefetched	0.00
Bytes loaded	1221.63
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	46.00
Stride indirect	13.00
Vectorization ratio all	61.63
Vectorization ratio load	45.24
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	34.78
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	16.67
Vector-efficiency ratio all	76.64
Vector-efficiency ratio load	58.93
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	51.09
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	76.30

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.1]
Source file and lines	PdV.cpp:70-83
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70-83
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 76% of vector register length is used (average across all VPU instructions).

Details

61% of VPU instructions are used in vector version (process two or more data elements in vector registers):

45% of VPU loads are used in vector version.
34% of VPU addition or subtraction instructions are used in vector version.
16% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 76.34 to 60.50 cycles (1.26x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 46 occurrence(s)
Irregular (variable stride) or indirect: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction
60: multiply
16: divide

The binary loop is loading 1221 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	176
nb uops	176
loop length	704
used w registers	0
used x registers	11
used b registers	0
used h registers	0
used s registers	0
used d registers	1
used q registers	0
used v registers	11
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.00 cycles
front end	22.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	6.00	0.50	63.00	63.00	14.00	14.00	13.67	13.67	13.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	6.00	0.50	63.00	63.00	16.50	16.50	13.67	13.67	13.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	28.85-76.34
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	22.00
Dispatch	63.00
DIV/SQRT	28.85-76.34
Data deps.	2.00
Overall L1	63.00-76.34

Vectorization ratios

INT

all	51%
load	45%
store	100%
mul	100%
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	0%

INT+FP

all	61%
load	45%
store	100%
mul	100%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	16%

Vector efficiency ratios

INT

all	70%
load	58%
store	100%
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	3%

INT+FP

all	76%
load	58%
store	100%
mul	100%
add-sub	51%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	76%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 76.34 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 434120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X17, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z3, [X17, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z26, [X17, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z31, [X17, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SEL Z11.D, P1, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SDIVR Z11.D, P0/M, Z11.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z13.D, Z3.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z3, [X17, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z0, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z0.D, P0/M, Z11.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z2.D, Z2.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z15, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z15.D, P0/M, Z13.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z7, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z7.D, P0/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z18, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z18.D, P0/M, Z18.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z6, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LDR Z3, [X17, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z11.D, Z11.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z13.D, P0/M, Z11.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADD Z11.D, Z26.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z0.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z4, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P0/M, Z4.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z27.D, [Z17, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z3, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z3.D, P0/M, Z3.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z26.D, [Z16, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z20, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z16, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z28.D, [Z27, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z26, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z29, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z31, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z17, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z28.D}, P1/Z, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z7.D, [Z31, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z27, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z29, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z31, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z30.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z31.D, [Z20, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z18.D, [Z31, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z31, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z29.D}, P1/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P1/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z26.D}, P1/Z, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z18.D}, P1/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z3.D}, P1/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z27.D, Z28.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z28, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z28.D, P0/M, Z28.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FADD Z4.D, Z7.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z7.D, [Z24, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z25, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z27.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z4.D, Z4.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z18.D, [Z25, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z27.D, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z29.D, [Z24, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z30.D, [Z29, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z26.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z27.D, [Z7, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z3.D, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z6, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z30.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z3.D, Z3.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z4.D, Z30.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z27.D, [Z18, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z0, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z4.D, Z4.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z27, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FADD Z4.D, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z6, [X17, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z6.D, [Z6, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z6, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z4.D, Z27.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z27, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMUL Z4.D, Z4.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z6.D, [Z6, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z27, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z13.D, P0/M, Z13.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z28.D, [Z29, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z7, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z18.D, [Z18, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z0, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P1/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z18.D}, P1/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P1/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z7.D, Z27.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z26.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LDR D26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD Z0.D, Z7.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z7.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
FMUL Z0.D, Z6.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z6.D, [Z10, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z7, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
DUP Z26.D, Z26.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.D, Z0.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z18.D, Z26.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z3.D, Z26.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z4.D, Z26.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z0.D, Z26.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
DUP Z26.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
FSUB Z3.D, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z18, [X17, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z3, [X17, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z26.D, [Z26, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FSUB Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z4.D, [Z9, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MUL Z18.D, P0/M, Z18.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z3.D, P0/M, Z3.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z18.D, [Z26, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z4, [X17, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z18.D}, P1/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z3.D}, P1/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z4.D, P0/M, Z4.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z4.D, [Z6, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z6, [X17, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z6.D, [Z7, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z7.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FDIV Z4.D, P0/M, Z4.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z7.D, P0/M, Z7.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDUP Z18.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
FDIV Z18.D, P0/M, Z18.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z4.D, Z4.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z7, [X17, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z4.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z0.D, P0/M, Z0.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z4.D, Z18.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
DUP Z18.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MUL Z7.D, P0/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z18.D, [Z18, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z18, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z18, [X17, #500, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z7.D}, P1/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z18.D, P0/M, Z18.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z15.D, P0/M, Z15.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FSUB Z4.D, Z7.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z7.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADR Z7.D, [Z7, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z7, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z4.D}, P1, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z3.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
DUP Z3.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADR Z3.D, [Z3, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z3, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z0.D}, P1, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X16, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 434120 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.1+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.1]
Source file and lines	PdV.cpp:70-83
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70-83
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 76% of vector register length is used (average across all VPU instructions).

Details

61% of VPU instructions are used in vector version (process two or more data elements in vector registers):

45% of VPU loads are used in vector version.
34% of VPU addition or subtraction instructions are used in vector version.
16% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 76.34 to 60.50 cycles (1.26x speedup).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 46 occurrence(s)
Irregular (variable stride) or indirect: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction
60: multiply
16: divide

The binary loop is loading 1221 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	176
nb uops	176
loop length	704
used w registers	0
used x registers	11
used b registers	0
used h registers	0
used s registers	0
used d registers	1
used q registers	0
used v registers	11
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.20

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.00 cycles
front end	22.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	6.00	0.50	63.00	63.00	14.00	14.00	13.67	13.67	13.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	6.00	0.50	63.00	63.00	16.50	16.50	13.67	13.67	13.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	28.85-76.34
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	22.00
Dispatch	63.00
DIV/SQRT	28.85-76.34
Data deps.	2.00
Overall L1	63.00-76.34

Vectorization ratios

INT

all	51%
load	45%
store	100%
mul	100%
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	0%

INT+FP

all	61%
load	45%
store	100%
mul	100%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	16%

Vector efficiency ratios

INT

all	70%
load	58%
store	100%
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	3%

INT+FP

all	76%
load	58%
store	100%
mul	100%
add-sub	51%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	76%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 76.34 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.84 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 434120

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X17, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X16, X16, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z3, [X17, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z26, [X17, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z31, [X17, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SEL Z11.D, P1, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SDIVR Z11.D, P0/M, Z11.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z13.D, Z3.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z3, [X17, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z0, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z0.D, P0/M, Z11.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z2.D, Z2.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z15, Z13	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z15.D, P0/M, Z13.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z7, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z7.D, P0/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z18, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z18.D, P0/M, Z18.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z6, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LDR Z3, [X17, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z11.D, Z11.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z13.D, P0/M, Z11.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADD Z11.D, Z26.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z0.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z4, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P0/M, Z4.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z27.D, [Z17, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z3, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z3.D, P0/M, Z3.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z26.D, [Z16, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z20, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z16, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z28.D, [Z27, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z26, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z29, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z31, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z17, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z28.D}, P1/Z, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z7.D, [Z31, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z27, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z29, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z31, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z30.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z31.D, [Z20, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z18.D, [Z31, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z31, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z29.D}, P1/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P1/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z26.D}, P1/Z, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z18.D}, P1/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z3.D}, P1/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z27.D, Z28.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z28, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z28.D, P0/M, Z28.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FADD Z4.D, Z7.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z7.D, [Z24, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z25, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z27.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z4.D, Z4.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z18.D, [Z25, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z27.D, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z29.D, [Z24, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z3.D, Z4.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z30.D, [Z29, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z26.D, Z26.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z27.D, [Z7, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z3.D, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z6, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z30.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z3.D, Z3.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z4.D, Z30.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z27.D, [Z18, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z0, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z4.D, Z4.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z27, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FADD Z4.D, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z6, [X17, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z6.D, [Z6, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z6, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z4.D, Z27.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z27, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMUL Z4.D, Z4.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z6.D, [Z6, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z27, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z13.D, P0/M, Z13.D, Z23.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z28.D, [Z29, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z7, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z18.D, [Z18, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z0, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P1/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z18.D}, P1/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P1/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z7.D, Z27.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z7.D, Z7.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z18.D, Z26.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LDR D26, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FADD Z0.D, Z7.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z7.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
FMUL Z0.D, Z6.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z6.D, [Z10, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z7, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
DUP Z26.D, Z26.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.D, Z0.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z18.D, Z26.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z3.D, Z26.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z4.D, Z26.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z0.D, Z26.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
DUP Z26.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
FSUB Z3.D, Z3.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z18, [X17, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z3, [X17, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z26.D, [Z26, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FSUB Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z4.D, [Z9, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MUL Z18.D, P0/M, Z18.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z3.D, P0/M, Z3.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z18.D, [Z26, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z4, [X17, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z18.D}, P1/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z3.D}, P1/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z4.D, P0/M, Z4.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z4.D, [Z6, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z6, [X17, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z6.D, [Z7, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z7.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FDIV Z4.D, P0/M, Z4.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z7.D, P0/M, Z7.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDUP Z18.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
FDIV Z18.D, P0/M, Z18.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z4.D, Z4.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z7, [X17, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z4.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z0.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z0.D, P0/M, Z0.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z4.D, Z18.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
DUP Z18.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MUL Z7.D, P0/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z18.D, [Z18, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z18, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z18, [X17, #500, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z7.D}, P1/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z18.D, P0/M, Z18.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z15.D, P0/M, Z15.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FSUB Z4.D, Z7.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z7.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADR Z7.D, [Z7, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z7, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z4.D}, P1, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z3.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
DUP Z3.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADR Z3.D, [Z3, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z3, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z0.D}, P1, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X16, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 434120 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.1+0x1f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code