OV - exec - Loop 700

	Loop Id: 700	Module: exec	Source: viscosity.cpp:37-64 [...]	Coverage: 2.75%

0x448380 DUP	Z1.D, #1

0x448384 SUB	X13, X29, #64

0x448388 ADD	X12, X12, X8

0x44838c SEL	Z30.D, P0, Z2.D, Z1.D

0x448390 LDR	Z1, [X13, #509, MUL VL]    [33]

0x448394 MOVPRFX	Z8, Z29

0x448398 SDIV	Z8.D, P1/M, Z8.D, Z30.D

0x44839c ADD	Z11.D, Z1.D, Z8.D

0x4483a0 MOVPRFX	Z13, Z29

0x4483a4 MLS	Z13.D, P1/M, Z8.D, Z2.D

0x4483a8 LDR	Z1, [X13, #508, MUL VL]    [33]

0x4483ac ADD	Z29.D, Z29.D, Z18.D

0x4483b0 MOVPRFX	Z30, Z11

0x4483b4 SXTW	Z30.D, P1/M, Z11.D

0x4483b8 LD1D	{Z11.D}, P0/Z, [X11, Z11.D,SXTW #3]    [28]

0x4483bc MOVPRFX	Z10, Z0

0x4483c0 MUL	Z10.D, P1/M, Z10.D, Z30.D

0x4483c4 ADD	Z9.D, Z13.D, Z19.D

0x4483c8 ADR	Z31.D, [Z22, Z9.D,SXTW #3]    [17]

0x4483cc ADR	Z12.D, [Z31, Z10.D,LSL #3]    [14]

0x4483d0 LD1D	{Z14.D}, P0/Z, [V12.D]    [15]

0x4483d4 ADD	Z12.D, Z8.D, Z20.D

0x4483d8 SXTW	Z12.D, P1/M, Z12.D

0x4483dc MOVPRFX	Z15, Z0

0x4483e0 MUL	Z15.D, P1/M, Z15.D, Z12.D

0x4483e4 ADR	Z31.D, [Z31, Z15.D,LSL #3]    [14]

0x4483e8 LD1D	{Z21.D}, P0/Z, [V31.D]    [13]

0x4483ec ADD	Z31.D, Z1.D, Z13.D

0x4483f0 MOVPRFX	Z1, Z17

0x4483f4 MUL	Z1.D, P1/M, Z1.D, Z30.D

0x4483f8 ADR	Z26.D, [Z22, Z31.D,SXTW #3]    [17]

0x4483fc ADR	Z5.D, [Z23, Z31.D,SXTW #3]    [18]

0x448400 ADR	Z10.D, [Z26, Z10.D,LSL #3]    [26]

0x448404 ADR	Z26.D, [Z26, Z15.D,LSL #3]    [26]

0x448408 MOVPRFX	Z15, Z17

0x44840c MUL	Z15.D, P1/M, Z15.D, Z12.D

0x448410 MUL	Z12.D, P1/M, Z12.D, Z3.D

0x448414 LD1D	{Z4.D}, P0/Z, [V10.D]    [10]

0x448418 LD1D	{Z26.D}, P0/Z, [V26.D]    [25]

0x44841c FADD	Z10.D, Z14.D, Z21.D

0x448420 ADR	Z6.D, [Z5, Z15.D,LSL #3]    [5]

0x448424 ADR	Z5.D, [Z5, Z1.D,LSL #3]    [5]

0x448428 LD1D	{Z6.D}, P0/Z, [V6.D]    [11]

0x44842c FADD	Z7.D, Z4.D, Z26.D

0x448430 LD1D	{Z5.D}, P0/Z, [V5.D]    [4]

0x448434 FSUB	Z10.D, Z10.D, Z7.D

0x448438 ADR	Z7.D, [Z23, Z9.D,SXTW #3]    [18]

0x44843c ADR	Z15.D, [Z7, Z15.D,LSL #3]    [12]

0x448440 ADR	Z1.D, [Z7, Z1.D,LSL #3]    [12]

0x448444 LD1D	{Z15.D}, P0/Z, [V15.D]    [21]

0x448448 LD1D	{Z1.D}, P0/Z, [V1.D]    [19]

0x44844c FADD	Z16.D, Z6.D, Z15.D

0x448450 FADD	Z7.D, Z5.D, Z1.D

0x448454 FADD	Z1.D, Z15.D, Z1.D

0x448458 FSUB	Z7.D, Z16.D, Z7.D

0x44845c FADD	Z16.D, Z21.D, Z26.D

0x448460 FSUB	Z1.D, Z1.D, Z5.D

0x448464 MOVPRFX	Z5, Z3

0x448468 MUL	Z5.D, P1/M, Z5.D, Z30.D

0x44846c FSUB	Z4.D, Z16.D, Z4.D

0x448470 LDR	Z16, [X13, #507, MUL VL]    [33]

0x448474 FSUB	Z1.D, Z1.D, Z6.D

0x448478 ADR	Z6.D, [Z24, Z9.D,SXTW #3]    [20]

0x44847c LD1D	{Z21.D}, P0/Z, [X9, Z9.D,SXTW #3]    [16]

0x448480 FSUB	Z4.D, Z4.D, Z14.D

0x448484 FMUL	Z1.D, P1/M, Z1.D, #0.0000000

0x448488 ADR	Z6.D, [Z6, Z5.D,LSL #3]    [9]

0x44848c FMUL	Z4.D, P1/M, Z4.D, #0.0000000

0x448490 LD1D	{Z6.D}, P0/Z, [V6.D]    [8]

0x448494 ADD	Z16.D, Z16.D, Z13.D

0x448498 LD1D	{Z13.D}, P0/Z, [X9, Z31.D,SXTW #3]    [16]

0x44849c FDIV	Z4.D, P1/M, Z4.D, Z11.D

0x4484a0 ADR	Z16.D, [Z24, Z16.D,SXTW #3]    [20]

0x4484a4 ADR	Z5.D, [Z16, Z5.D,LSL #3]    [24]

0x4484a8 LDR	Z16, [X13, #506, MUL VL]    [33]

0x4484ac ADD	X13, X11, #16

0x4484b0 LD1D	{Z5.D}, P0/Z, [V5.D]    [3]

0x4484b4 FDIV	Z1.D, P1/M, Z1.D, Z13.D

0x4484b8 FADD	Z21.D, Z13.D, Z21.D

0x4484bc ADD	Z16.D, Z16.D, Z8.D

0x4484c0 SXTW	Z16.D, P1/M, Z16.D

0x4484c4 MUL	Z16.D, P1/M, Z16.D, Z3.D

0x4484c8 FADD	Z1.D, Z4.D, Z1.D

0x4484cc FSUB	Z4.D, Z6.D, Z5.D

0x4484d0 ADR	Z5.D, [Z24, Z31.D,SXTW #3]    [20]

0x4484d4 ADR	Z6.D, [Z5, Z12.D,LSL #3]    [2]

0x4484d8 ADR	Z5.D, [Z5, Z16.D,LSL #3]    [2]

0x4484dc LSL	Z16.D, Z30.D, #3

0x4484e0 FDIV	Z4.D, P1/M, Z4.D, Z21.D

0x4484e4 FMUL	Z21.D, Z7.D, Z11.D

0x4484e8 FMUL	Z7.D, P1/M, Z7.D, #0.0000000

0x4484ec LD1D	{Z6.D}, P0/Z, [V6.D]    [7]

0x4484f0 LD1D	{Z5.D}, P0/Z, [V5.D]    [1]

0x4484f4 LD1D	{Z16.D}, P0/Z, [X13, Z16.D]    [32]

0x4484f8 SUB	X13, X29, #64

0x4484fc FMLA	Z21.D, P1/M, Z13.D, Z10.D

0x448500 FMUL	Z10.D, P1/M, Z10.D, #0.0000000

0x448504 FDIV	Z7.D, P1/M, Z7.D, Z11.D

0x448508 FDIV	Z10.D, P1/M, Z10.D, Z13.D

0x44850c FCMGE	P2.D, P1/Z, Z21.D, #0.0000000

0x448510 FSUB	Z5.D, Z6.D, Z5.D

0x448514 FADD	Z6.D, Z11.D, Z16.D

0x448518 FDIV	Z5.D, P1/M, Z5.D, Z6.D

0x44851c FMUL	Z6.D, Z4.D, Z4.D

0x448520 FMUL	Z1.D, Z1.D, Z4.D

0x448524 FCMLT	P3.D, P1/Z, Z4.D, #0.0000000

0x448528 FABS	Z4.D, P1/M, Z4.D

0x44852c FMAXNM	Z4.D, P1/M, Z4.D, Z25.D

0x448530 FNEG	Z4.D, P3/M, Z4.D

0x448534 FCMLT	P3.D, P1/Z, Z4.D, #0.0000000

0x448538 FMUL	Z16.D, Z5.D, Z5.D

0x44853c FMUL	Z7.D, Z7.D, Z16.D

0x448540 FMLA	Z7.D, P1/M, Z10.D, Z6.D

0x448544 FADD	Z6.D, Z6.D, Z16.D

0x448548 FMAXNM	Z6.D, P1/M, Z6.D, Z25.D

0x44854c FMAD	Z1.D, P1/M, Z5.D, Z7.D

0x448550 FABS	Z5.D, P1/M, Z5.D

0x448554 FMAXNM	Z5.D, P1/M, Z5.D, Z25.D

0x448558 FNEG	Z5.D, P3/M, Z5.D

0x44855c FDIV	Z1.D, P1/M, Z1.D, Z6.D

0x448560 FMUL	Z6.D, Z5.D, Z5.D

0x448564 FMLA	Z6.D, P1/M, Z4.D, Z4.D

0x448568 FSQRT	Z6.D, P1/M, Z6.D

0x44856c FCMGT	P3.D, P1/Z, Z1.D, #0.0000000

0x448570 EOR	P3.B, P1/Z, P3.B, P1.B

0x448574 BIC	P2.B, P3/Z, P3.B, P2.B

0x448578 AND	P3.B, P0/Z, P0.B, P2.B

0x44857c FMUL	Z7.D, Z13.D, Z6.D

0x448580 FMUL	Z6.D, Z11.D, Z6.D

0x448584 FDIVR	Z4.D, P1/M, Z4.D, Z7.D

0x448588 FDIVR	Z5.D, P1/M, Z5.D, Z6.D

0x44858c ADR	Z6.D, [Z27, Z31.D,SXTW #3]    [29]

0x448590 FABS	Z4.D, P1/M, Z4.D

0x448594 FABS	Z5.D, P1/M, Z5.D

0x448598 FMINNM	Z4.D, P1/M, Z4.D, Z5.D

0x44859c LDR	Z5, [X13, #511, MUL VL]    [31]

0x4485a0 FMUL	Z4.D, Z4.D, Z4.D

0x4485a4 MUL	Z5.D, P1/M, Z5.D, Z30.D

0x4485a8 ADR	Z5.D, [Z6, Z5.D,LSL #3]    [27]

0x4485ac LD1D	{Z5.D}, P3/Z, [V5.D]    [6]

0x4485b0 FADD	Z5.D, Z5.D, Z5.D

0x4485b4 FMUL	Z4.D, Z4.D, Z5.D

0x4485b8 MOVI	V5.2D, #0

0x4485bc FMUL	Z4.D, Z1.D, Z4.D

0x4485c0 FMUL	Z1.D, Z1.D, Z4.D

0x4485c4 LDR	Z4, [X13, #510, MUL VL]    [31]

0x4485c8 SEL	Z1.D, P2, Z1.D, Z5.D

0x4485cc MUL	Z30.D, P1/M, Z30.D, Z4.D

0x4485d0 ADR	Z4.D, [Z28, Z31.D,SXTW #3]    [30]

0x4485d4 ADR	Z4.D, [Z4, Z30.D,LSL #3]    [23]

0x4485d8 ST1D	{Z1.D}, P0, [V4.D]    [22]

0x4485dc WHILELO	P0.D, X12, X10

0x4485e0 B.MI	448380

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp: 37 - 64

--------------------------------------------------------------------------------

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

Coverage (%)	Name	Source Location	Module
►98.45+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.55+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	viscosity(global_variables&)	viscosity.cpp:76	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:64	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19 - 2.70
Bottlenecks	P6, P8,
Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	context.h:46-46,context.h:69-69,viscosity.cpp:37-64
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	70.80 - 160.85
CQA cycles if no scalar integer	70.80 - 160.85
CQA cycles if FP arith vectorized	70.80 - 160.85
CQA cycles if fully vectorized	70.80 - 160.85
Front-end cycles	19.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.50
P3 cycles	1.25
P4 cycles	4.00
P5 cycles	1.25
P6 cycles	59.50
P7 cycles	59.50
P8 cycles	19.50
P9 cycles	19.50
P10 cycles	8.17
P11 cycles	7.83
P12 cycles	8.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	70.80 - 160.85
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	153.00
Nb uops	153.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.99 - 1.32
Nb FLOP add-sub	76.00
Nb FLOP mul	64.00
Nb FLOP fma	16.00
Nb FLOP div	36.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.79 - 10.89
Bytes prefetched	0.00
Bytes loaded	738.88
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	25.00
Stride indirect	8.00
Vectorization ratio all	77.55
Vectorization ratio load	50.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	54.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	69.70
Vector-efficiency ratio all	85.31
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	65.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	86.84

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19 - 2.70
Bottlenecks	P6, P8,
Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	context.h:46-46,context.h:69-69,viscosity.cpp:37-64
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	70.80 - 160.85
CQA cycles if no scalar integer	70.80 - 160.85
CQA cycles if FP arith vectorized	70.80 - 160.85
CQA cycles if fully vectorized	70.80 - 160.85
Front-end cycles	19.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.50
P3 cycles	1.25
P4 cycles	4.00
P5 cycles	1.25
P6 cycles	59.50
P7 cycles	59.50
P8 cycles	19.50
P9 cycles	19.50
P10 cycles	8.17
P11 cycles	7.83
P12 cycles	8.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	70.80 - 160.85
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	153.00
Nb uops	153.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.99 - 1.32
Nb FLOP add-sub	76.00
Nb FLOP mul	64.00
Nb FLOP fma	16.00
Nb FLOP div	36.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.79 - 10.89
Bytes prefetched	0.00
Bytes loaded	738.88
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	25.00
Stride indirect	8.00
Vectorization ratio all	77.55
Vectorization ratio load	50.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	54.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	69.70
Vector-efficiency ratio all	85.31
Vector-efficiency ratio load	62.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	65.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	86.84

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	viscosity.cpp:37-64
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37-64

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions).

Details

77% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
54% of VPU addition or subtraction instructions are used in vector version.
69% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 160.85 to 54.00 cycles (2.98x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 25 occurrence(s)
Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 212 FP arithmetical operations:

92: addition or subtraction (16 inside FMA instructions)
80: multiply (16 inside FMA instructions)
36: divide
4: square root

The binary loop is loading 738 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	153
nb uops	153
loop length	612
used w registers	0
used x registers	7
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	9
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.13 cycles
front end	19.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.25	4.00	1.25	59.50	59.50	7.50	7.50	8.17	7.83	8.00	0.00	0.00
cycles	0.50	0.50	1.50	1.25	4.00	1.25	59.50	59.50	19.50	19.50	8.17	7.83	8.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	70.80-160.85
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	19.13
Dispatch	59.50
DIV/SQRT	70.80-160.85
Data deps.	0.00
Overall L1	70.80-160.85

Vectorization ratios

INT

all	60%
load	50%
store	100%
mul	100%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	77%
load	50%
store	100%
mul	100%
add-sub	54%
fma	100%
div/sqrt	100%
other	69%

Vector efficiency ratios

INT

all	74%
load	62%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	78%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	85%
load	62%
store	100%
mul	100%
add-sub	65%
fma	100%
div/sqrt	100%
other	86%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 160.85 cycles. At this rate:

4% of peak load performance is reached (4.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 448380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z1.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X13, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SEL Z30.D, P0, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z1, [X13, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z8, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SDIV Z8.D, P1/M, Z8.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z11.D, Z1.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z13.D, P1/M, Z8.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X13, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z29.D, Z29.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z30.D, P1/M, Z11.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z11.D}, P0/Z, [X11, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z10, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z10.D, P1/M, Z10.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z9.D, Z13.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z31.D, [Z22, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z12.D, [Z31, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z14.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z12.D, Z8.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z12.D, P1/M, Z12.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z15, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P1/M, Z15.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z31.D, [Z31, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z21.D}, P0/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z31.D, Z1.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z1, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z1.D, P1/M, Z1.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z26.D, [Z22, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z23, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z26, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z26, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z15, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P1/M, Z15.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z12.D, P1/M, Z12.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z26.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z10.D, Z14.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z6.D, [Z5, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z5, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z7.D, Z4.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z10.D, Z10.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z7.D, [Z23, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z7, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z7, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z15.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z1.D}, P0/Z, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z16.D, Z6.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z7.D, Z5.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z1.D, Z15.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z7.D, Z16.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z16.D, Z21.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z1.D, Z1.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z5, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P1/M, Z5.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FSUB Z4.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z16, [X13, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z1.D, Z1.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z6.D, [Z24, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z21.D}, P0/Z, [X9, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z4.D, Z4.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z1.D, P1/M, Z1.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z6.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z4.D, P1/M, Z4.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z16.D, Z16.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z13.D}, P0/Z, [X9, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FDIV Z4.D, P1/M, Z4.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z16.D, [Z24, Z16.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z16, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z16, [X13, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X13, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FDIV Z1.D, P1/M, Z1.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z21.D, Z13.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z16.D, Z16.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z16.D, P1/M, Z16.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MUL Z16.D, P1/M, Z16.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FADD Z1.D, Z4.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z4.D, Z6.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z5.D, [Z24, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z5, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z5, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LSL Z16.D, Z30.D, #3	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z4.D, P1/M, Z4.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z21.D, Z7.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z7.D, P1/M, Z7.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z16.D}, P0/Z, [X13, Z16.D]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SUB X13, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMLA Z21.D, P1/M, Z13.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z10.D, P1/M, Z10.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z7.D, P1/M, Z7.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z10.D, P1/M, Z10.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCMGE P2.D, P1/Z, Z21.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FSUB Z5.D, Z6.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, Z11.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z5.D, P1/M, Z5.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z6.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z1.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMLT P3.D, P1/Z, Z4.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FABS Z4.D, P1/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z4.D, P1/M, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FNEG Z4.D, P3/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCMLT P3.D, P1/Z, Z4.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z16.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z7.D, P1/M, Z10.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FADD Z6.D, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z6.D, P1/M, Z6.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z1.D, P1/M, Z5.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FABS Z5.D, P1/M, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z5.D, P1/M, Z5.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FNEG Z5.D, P3/M, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z1.D, P1/M, Z1.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z6.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z6.D, P1/M, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z6.D, P1/M, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FCMGT P3.D, P1/Z, Z1.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P3.B, P1/Z, P3.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
BIC P2.B, P3/Z, P3.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P3.B, P0/Z, P0.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMUL Z7.D, Z13.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z11.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z4.D, P1/M, Z4.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z5.D, P1/M, Z5.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z6.D, [Z27, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FABS Z4.D, P1/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABS Z5.D, P1/M, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z4.D, P1/M, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z5, [X13, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z4.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MUL Z5.D, P1/M, Z5.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z5.D}, P3/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z5.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVI V5.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL Z4.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z1.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LDR Z4, [X13, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SEL Z1.D, P2, Z1.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z30.D, P1/M, Z30.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z4.D, [Z28, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z4, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z1.D}, P0, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P0.D, X12, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 448380 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	viscosity.cpp:37-64
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37-64

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions).

Details

77% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU loads are used in vector version.
54% of VPU addition or subtraction instructions are used in vector version.
69% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 160.85 to 54.00 cycles (2.98x speedup).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 25 occurrence(s)
Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 212 FP arithmetical operations:

92: addition or subtraction (16 inside FMA instructions)
80: multiply (16 inside FMA instructions)
36: divide
4: square root

The binary loop is loading 738 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	153
nb uops	153
loop length	612
used w registers	0
used x registers	7
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	9
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.19

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.13 cycles
front end	19.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.25	4.00	1.25	59.50	59.50	7.50	7.50	8.17	7.83	8.00	0.00	0.00
cycles	0.50	0.50	1.50	1.25	4.00	1.25	59.50	59.50	19.50	19.50	8.17	7.83	8.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	70.80-160.85
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	19.13
Dispatch	59.50
DIV/SQRT	70.80-160.85
Data deps.	0.00
Overall L1	70.80-160.85

Vectorization ratios

INT

all	60%
load	50%
store	100%
mul	100%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	77%
load	50%
store	100%
mul	100%
add-sub	54%
fma	100%
div/sqrt	100%
other	69%

Vector efficiency ratios

INT

all	74%
load	62%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	78%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	85%
load	62%
store	100%
mul	100%
add-sub	65%
fma	100%
div/sqrt	100%
other	86%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 160.85 cycles. At this rate:

4% of peak load performance is reached (4.59 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 448380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z1.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X13, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X12, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SEL Z30.D, P0, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z1, [X13, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z8, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SDIV Z8.D, P1/M, Z8.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z11.D, Z1.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z13.D, P1/M, Z8.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LDR Z1, [X13, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z29.D, Z29.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z11	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z30.D, P1/M, Z11.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z11.D}, P0/Z, [X11, Z11.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z10, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z10.D, P1/M, Z10.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z9.D, Z13.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z31.D, [Z22, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z12.D, [Z31, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z14.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z12.D, Z8.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z12.D, P1/M, Z12.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z15, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P1/M, Z15.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z31.D, [Z31, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z21.D}, P0/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z31.D, Z1.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z1, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z1.D, P1/M, Z1.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z26.D, [Z22, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z23, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z26, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z26, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z15, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P1/M, Z15.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z12.D, P1/M, Z12.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z26.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z10.D, Z14.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z6.D, [Z5, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z5, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z7.D, Z4.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z10.D, Z10.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z7.D, [Z23, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z7, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z7, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z15.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z1.D}, P0/Z, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z16.D, Z6.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z7.D, Z5.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z1.D, Z15.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z7.D, Z16.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z16.D, Z21.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z1.D, Z1.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z5, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P1/M, Z5.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FSUB Z4.D, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z16, [X13, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z1.D, Z1.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z6.D, [Z24, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z21.D}, P0/Z, [X9, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z4.D, Z4.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z1.D, P1/M, Z1.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z6.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z4.D, P1/M, Z4.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z16.D, Z16.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z13.D}, P0/Z, [X9, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FDIV Z4.D, P1/M, Z4.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z16.D, [Z24, Z16.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z16, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z16, [X13, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD X13, X11, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FDIV Z1.D, P1/M, Z1.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z21.D, Z13.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z16.D, Z16.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z16.D, P1/M, Z16.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MUL Z16.D, P1/M, Z16.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FADD Z1.D, Z4.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z4.D, Z6.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z5.D, [Z24, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z5, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z5, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LSL Z16.D, Z30.D, #3	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z4.D, P1/M, Z4.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z21.D, Z7.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z7.D, P1/M, Z7.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z16.D}, P0/Z, [X13, Z16.D]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SUB X13, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
FMLA Z21.D, P1/M, Z13.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z10.D, P1/M, Z10.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z7.D, P1/M, Z7.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z10.D, P1/M, Z10.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCMGE P2.D, P1/Z, Z21.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FSUB Z5.D, Z6.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, Z11.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z5.D, P1/M, Z5.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z6.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z1.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMLT P3.D, P1/Z, Z4.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FABS Z4.D, P1/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z4.D, P1/M, Z4.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FNEG Z4.D, P3/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FCMLT P3.D, P1/Z, Z4.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FMUL Z16.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z7.D, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z7.D, P1/M, Z10.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FADD Z6.D, Z6.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z6.D, P1/M, Z6.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z1.D, P1/M, Z5.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FABS Z5.D, P1/M, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z5.D, P1/M, Z5.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FNEG Z5.D, P3/M, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z1.D, P1/M, Z1.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z6.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z6.D, P1/M, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FSQRT Z6.D, P1/M, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FCMGT P3.D, P1/Z, Z1.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
EOR P3.B, P1/Z, P3.B, P1.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
BIC P2.B, P3/Z, P3.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
AND P3.B, P0/Z, P0.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMUL Z7.D, Z13.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z6.D, Z11.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z4.D, P1/M, Z4.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z5.D, P1/M, Z5.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z6.D, [Z27, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FABS Z4.D, P1/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABS Z5.D, P1/M, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z4.D, P1/M, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z5, [X13, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMUL Z4.D, Z4.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MUL Z5.D, P1/M, Z5.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z5.D}, P3/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z5.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVI V5.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL Z4.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z1.D, Z1.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LDR Z4, [X13, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SEL Z1.D, P2, Z1.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z30.D, P1/M, Z30.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z4.D, [Z28, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z4, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z1.D}, P0, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P0.D, X12, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 448380 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x1a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code