OV - exec - Function initialise_chunk(int, global_variables&) [clone ._omp

	Function: initialise_chunk(int, global_variables&) [clone ._omp_fn.4]	Module: exec	Source: initialise_chunk.cpp:77-82 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp: 77 - 82

--------------------------------------------------------------------------------

77: #pragma omp parallel for simd collapse(2)

78:   for (int j = (0); j < (yrange1); j++) {

79:     for (int i = (0); i < (xrange1); i++) {

80:       field.volume(i, j) = dx * dy;

81:       field.xarea(i, j) = field.celldy[j];

82:       field.yarea(i, j) = field.celldx[i];

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x431690 STP	X29, X30, [SP, #960]!

0x431694 ADD	X29, SP, #0

0x431698 STP	X19, X20, [SP, #16]

0x43169c LDP	W19, W20, [X0, #24]

0x4316a0 CMP	W20, #0

0x4316a4 B.LE	4317e8

0x4316a8 CMP	W19, #0

0x4316ac B.LE	4317e8

0x4316b0 STP	X21, X22, [SP, #32]

0x4316b4 ORR	X22, XZR, X0

0x4316b8 STR	X23, [SP, #48]

0x4316bc MUL	W23, W20, W19

0x4316c0 BL	410670

0x4316c4 ORR	W21, WZR, W0

0x4316c8 BL	410550

0x4316cc UDIV	W1, W23, W21

0x4316d0 ORR	W2, WZR, W0

0x4316d4 MSUB	W3, W1, W21, W23

0x4316d8 CMP	W0, W3

0x4316dc B.CC	4317f4

0x4316e0 MADD	W2, W1, W2, W3

0x4316e4 ADD	W13, W1, W2

0x4316e8 CMP	W2, W13

0x4316ec B.CS	4317e0

0x4316f0 UDIV	W7, W2, W19

0x4316f4 LDR	X9, [X22, #16]

0x4316f8 CNTD	X8, ALL

0x4316fc PTRUE	P6.B, ALL

0x431700 LDP	D30, D31, [X22]

0x431704 MSUB	W5, W7, W19, W2

0x431708 SBFM	X7, X7, #0, #31

0x43170c SUB	W0, W19, W5

0x431710 CMP	W1, W0

0x431714 CSEL	W1, W1, W0, #9

0x431718 ADD	W10, W2, W1

0x43171c CMP	W2, W10

0x431720 B.CS	4317d0

  (265) 0x431724 ADD	X15, X9, #672

  (265) 0x431728 LDR	X4, [X9, #656]

  (265) 0x43172c SBFM	X11, X5, #0, #31

  (265) 0x431730 LDP	X14, X3, [X15]

  (265) 0x431734 MOVZ	X0, #0

  (265) 0x431738 FMUL	D29, D31, D30

  (265) 0x43173c WHILELO	P7.D, WZR, W1

  (265) 0x431740 DUP	Z29.D, Z29.D[0]

  (265) 0x431744 LDP	X12, X2, [X15, #24]

  (265) 0x431748 MADD	X4, X7, X4, X11

  (265) 0x43174c MADD	X3, X7, X3, X11

  (265) 0x431750 LDR	X6, [X9, #584]

  (265) 0x431754 ADD	X4, X14, X4,LSL #3

  (265) 0x431758 MADD	X2, X7, X2, X11

  (265) 0x43175c LDR	X11, [X9, #720]

  (265) 0x431760 ADD	X3, X12, X3,LSL #3

  (265) 0x431764 LDR	X14, [X9, #552]

  (265) 0x431768 ADD	X5, X14, W5,UXTW #3

  (265) 0x43176c ADD	X6, X6, X7,LSL #3

  (265) 0x431770 ADD	X2, X11, X2,LSL #3

  (265) 0x431774 HINT	#0

  (265) 0x431778 HINT	#0

  (265) 0x43177c HINT	#0

    (264) 0x431780 ST1D	{Z29.D}, P7, [X4, X0,LSL #3]

    (264) 0x431784 LD1RD	{Z0.D}, P6/Z, [X6]

    (264) 0x431788 ST1D	{Z0.D}, P7, [X3, X0,LSL #3]

    (264) 0x43178c LD1D	{Z28.D}, P7/Z, [X5, X0,LSL #3]

    (264) 0x431790 ST1D	{Z28.D}, P7, [X2, X0,LSL #3]

    (264) 0x431794 ADD	X0, X0, X8

    (264) 0x431798 WHILELO	P7.D, W0, W1

    (264) 0x43179c B.NE	431780

  (265) 0x4317a0 ADD	X7, X7, #1

  (265) 0x4317a4 CMP	W20, W7

  (265) 0x4317a8 B.LE	4317e0

  (265) 0x4317ac SUB	W1, W13, W10

  (265) 0x4317b0 ORR	W0, WZR, W19

  (265) 0x4317b4 ORR	W2, WZR, W10

  (265) 0x4317b8 CMP	W1, W0

  (265) 0x4317bc CSEL	W1, W1, W0, #9

  (265) 0x4317c0 ADD	W10, W2, W1

  (265) 0x4317c4 MOVZ	W5, #0

  (265) 0x4317c8 CMP	W2, W10

  (265) 0x4317cc B.CC	431724

(266) 0x4317d0 ADD	X7, X7, #1

(266) 0x4317d4 ORR	W10, WZR, W2

(266) 0x4317d8 CMP	W20, W7

(266) 0x4317dc B.GT	4317ac

0x4317e0 LDR	X23, [SP, #48]

0x4317e4 LDP	X21, X22, [SP, #32]

0x4317e8 LDP	X19, X20, [SP, #16]

0x4317ec LDP	X29, X30, [SP], #64

0x4317f0 RET

0x4317f4 ADD	W1, W1, #1

0x4317f8 MOVZ	W3, #0

0x4317fc B	4316e0

Coverage (%)	Name	Source Location	Module
►98.50+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.50+	GOMP_parallel		libgomp.so.1.0.0
○	initialise_chunk(int, global_v[...]	initialise_chunk.cpp:85	exec
○	start(parallel_&, global_confi[...]	start.cpp:83	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	clover_leaf.cpp:204	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	initialise_chunk.cpp:77-82
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-82
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 25.00 to 15.62 cycles (1.60x speedup).

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

16% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 6.50 cycles (3.85x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	45
nb uops	45
loop length	180
used w registers	13
used x registers	12
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.63 cycles
front end	5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.67	3.67	3.67	2.00	2.00
cycles	4.50	4.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.67	3.67	3.67	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	5.63
Dispatch	7.00
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	3%
load	16%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	28%
load	37%
store	43%
mul	12%
add-sub	16%
fma	12%
div/sqrt	12%
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 431690

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W19, W20, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4317e8 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4317e8 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL W23, W20, W19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W23, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W3, W1, W21, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 4317f4 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W3	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W13, W1, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 4317e0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W2, W19	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
LDR X9, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
LDP D30, D31, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MSUB W5, W7, W19, W2	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
SBFM X7, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SUB W0, W19, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W1, W1, W0, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W10, W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 4317d0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #64	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
B 4316e0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	initialise_chunk.cpp:77-82
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-82
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

3% of VPU instructions are used in vector version (process two or more data elements in vector registers):

16% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU divide and square root instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 6.50 cycles (3.85x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	45
nb uops	45
loop length	180
used w registers	13
used x registers	12
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.63 cycles
front end	5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.67	3.67	3.67	2.00	2.00
cycles	4.50	4.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	3.67	3.67	3.67	2.00	2.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	5.63
Dispatch	7.00
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	3%
load	16%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	28%
load	37%
store	43%
mul	12%
add-sub	16%
fma	12%
div/sqrt	12%
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 431690

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #960]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W19, W20, [X0, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W20, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4317e8 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 4317e8 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x158>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR X23, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MUL W23, W20, W19	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W23, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W3, W1, W21, W23	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 4317f4 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x164>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W3	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W13, W1, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 4317e0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W2, W19	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
LDR X9, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (100.0%)
LDP D30, D31, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
MSUB W5, W7, W19, W2	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
SBFM X7, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
SUB W0, W19, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W1, W1, W0, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W10, W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 4317d0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x140>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #64	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W3, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
B 4316e0 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼initialise_chunk(int, global_variables&) [clone ._omp_fn.4]–	0.03	0.04
▼Loop 266 - initialise_chunk.cpp:77-82 - exec–	0.00	0.00
▼Loop 265 - initialise_chunk.cpp:77-82 - exec–	0.00	0.00
○Loop 264 - initialise_chunk.cpp:80-82 - exec	0.03	0.04

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code