OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage (incl. loops): 8.13% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 69 - 83

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69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

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69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4352cc STP	X29, X30, [SP, #736]!

0x4352d0 ADD	X29, SP, #0

0x4352d4 STP	X19, X20, [SP, #16]

0x4352d8 ORR	X20, XZR, X0

0x4352dc STP	X21, X22, [SP, #32]

0x4352e0 LDP	W22, W1, [X0, #120]

0x4352e4 LDR	W0, [X0, #112]

0x4352e8 LDR	W2, [X20, #116]

0x4352ec ADD	W1, W1, #2

0x4352f0 ADD	W22, W22, #1

0x4352f4 ADD	W0, W0, #1

0x4352f8 STP	W1, W0, [SP, #232]

0x4352fc CMP	W22, W1

0x435300 B.GE	435770

0x435304 ADD	W19, W2, #2

0x435308 STP	X23, X24, [SP, #48]

0x43530c SUB	W23, W1, W22

0x435310 CMP	W0, W19

0x435314 B.GE	435780

0x435318 SUB	W0, W19, W0

0x43531c MUL	W23, W23, W0

0x435320 STR	W0, [SP, #240]

0x435324 BL	410670

0x435328 ORR	W21, WZR, W0

0x43532c BL	410550

0x435330 UDIV	W4, W23, W21

0x435334 ORR	W3, WZR, W0

0x435338 MSUB	W0, W4, W21, W23

0x43533c CMP	W3, W0

0x435340 B.CC	435794

0x435344 MADD	W3, W4, W3, W0

0x435348 ADD	W0, W4, W3

0x43534c STR	W0, [SP, #244]

0x435350 CMP	W3, W0

0x435354 B.CS	435780

0x435358 LDR	W1, [SP, #240]

0x43535c PTRUE	P7.B, ALL

0x435360 FDUP	Z30.D, #80

0x435364 STP	X25, X26, [SP, #64]

0x435368 FDUP	Z29.D, #112

0x43536c STP	X27, X28, [SP, #80]

0x435370 LD1RD	{Z31.D}, P7/Z, [X20]

0x435374 UDIV	W0, W3, W1

0x435378 LDR	X2, [X20, #8]

0x43537c STR	X2, [SP, #112]

0x435380 LDR	X2, [X20, #16]

0x435384 MSUB	W1, W0, W1, W3

0x435388 ADD	W0, W0, W22

0x43538c SBFM	X28, X0, #0, #31

0x435390 LDR	X0, [X20, #56]

0x435394 STR	X0, [SP, #160]

0x435398 LDR	W0, [SP, #236]

0x43539c ADD	W1, W1, W0

0x4353a0 LDR	X0, [X20, #64]

0x4353a4 ORR	W12, WZR, W1

0x4353a8 STP	X2, X0, [SP, #120]

0x4353ac LDR	X0, [X20, #72]

0x4353b0 LDR	X2, [X20, #24]

0x4353b4 STR	X0, [SP, #144]

0x4353b8 LDR	X0, [X20, #80]

0x4353bc STR	X2, [SP, #280]

0x4353c0 LDR	X2, [X20, #32]

0x4353c4 STR	X0, [SP, #248]

0x4353c8 LDR	X0, [X20, #88]

0x4353cc STR	X2, [SP, #136]

0x4353d0 LDR	X2, [X20, #40]

0x4353d4 STR	X0, [SP, #256]

0x4353d8 LDR	X0, [X20, #96]

0x4353dc STR	X2, [SP, #168]

0x4353e0 LDR	X2, [X20, #48]

0x4353e4 STR	X0, [SP, #264]

0x4353e8 LDR	X0, [X20, #104]

0x4353ec STR	X2, [SP, #152]

0x4353f0 SUB	W2, W19, W1

0x4353f4 CMP	W4, W2

0x4353f8 CSEL	W1, W4, W2, #9

0x4353fc STR	X0, [SP, #272]

0x435400 ADD	W0, W3, W1

0x435404 STR	W0, [SP, #108]

0x435408 CMP	W3, W0

0x43540c B.CS	435750

  (312) 0x435410 LDR	X0, [SP, #280]

  (312) 0x435414 SBFM	X12, X12, #0, #31

  (312) 0x435418 ORR	W1, WZR, W1

  (312) 0x43541c LDP	X18, X20, [SP, #144]

  (312) 0x435420 WHILELO	P7.D, XZR, X1

  (312) 0x435424 LDP	X15, X16, [SP, #128]

  (312) 0x435428 LDP	X24, X25, [SP, #160]

  (312) 0x43542c LDP	X11, X2, [SP, #112]

  (312) 0x435430 LDP	X19, X21, [SP, #248]

  (312) 0x435434 LDP	X22, X23, [SP, #264]

  (312) 0x435438 LDR	X13, [X0]

  (312) 0x43543c LDR	X7, [X2]

  (312) 0x435440 LDR	X14, [X15]

  (312) 0x435444 MADD	X17, X28, X13, X12

  (312) 0x435448 LDR	X13, [X18]

  (312) 0x43544c LDR	X2, [X11]

  (312) 0x435450 MUL	X11, X28, X7

  (312) 0x435454 LDR	X6, [X19]

  (312) 0x435458 MADD	X15, X28, X13, X12

  (312) 0x43545c ADD	X7, X7, X11

  (312) 0x435460 ADD	X11, X11, X12

  (312) 0x435464 LDR	X13, [X25]

  (312) 0x435468 ADD	X7, X7, X12

  (312) 0x43546c MADD	X27, X28, X2, X12

  (312) 0x435470 LDR	X5, [X21]

  (312) 0x435474 MUL	X10, X28, X6

  (312) 0x435478 LDR	X4, [X22]

  (312) 0x43547c MADD	X30, X28, X13, X12

  (312) 0x435480 LDR	X3, [X23]

  (312) 0x435484 ADD	X6, X6, X10

  (312) 0x435488 ADD	X10, X10, X12

  (312) 0x43548c MUL	X9, X28, X5

  (312) 0x435490 ADD	X6, X6, X12

  (312) 0x435494 LDR	X18, [X24]

  (312) 0x435498 MUL	X8, X28, X4

  (312) 0x43549c LDR	X2, [X16]

  (312) 0x4354a0 MADD	X16, X28, X14, X12

  (312) 0x4354a4 ADD	X5, X5, X9

  (312) 0x4354a8 MUL	X26, X28, X3

  (312) 0x4354ac ADD	X9, X9, X12

  (312) 0x4354b0 ADD	X5, X5, X12

  (312) 0x4354b4 LDR	X14, [X20]

  (312) 0x4354b8 ADD	X4, X4, X8

  (312) 0x4354bc ADD	X8, X8, X12

  (312) 0x4354c0 ADD	X4, X4, X12

  (312) 0x4354c4 LDR	X13, [SP, #112]

  (312) 0x4354c8 ADD	X3, X3, X26

  (312) 0x4354cc ADD	X26, X26, X12

  (312) 0x4354d0 ADD	X3, X3, X12

  (312) 0x4354d4 MADD	X2, X28, X2, X12

  (312) 0x4354d8 LDR	X20, [X19, #16]

  (312) 0x4354dc MADD	X19, X28, X18, X12

  (312) 0x4354e0 MADD	X14, X28, X14, X12

  (312) 0x4354e4 LDR	X18, [X22, #16]

  (312) 0x4354e8 STR	X19, [SP, #224]

  (312) 0x4354ec LDR	X12, [X23, #16]

  (312) 0x4354f0 ADD	X24, X20, X10,LSL #3

  (312) 0x4354f4 LDR	X19, [X21, #16]

  (312) 0x4354f8 ADD	X25, X20, X6,LSL #3

  (312) 0x4354fc ADD	X10, X20, X10,LSL #3

  (312) 0x435500 ADD	X24, X24, #8

  (312) 0x435504 LDR	X13, [X13, #16]

  (312) 0x435508 ADD	X6, X20, X6,LSL #3

  (312) 0x43550c ADD	X25, X25, #8

  (312) 0x435510 ADD	X22, X18, X4,LSL #3

  (312) 0x435514 LDR	X21, [SP, #120]

  (312) 0x435518 ADD	X4, X18, X4,LSL #3

  (312) 0x43551c ADD	X23, X19, X5,LSL #3

  (312) 0x435520 ADD	X22, X22, #8

  (312) 0x435524 LDR	X0, [X0, #16]

  (312) 0x435528 ADD	X20, X19, X9,LSL #3

  (312) 0x43552c ADD	X5, X19, X5,LSL #3

  (312) 0x435530 ADD	X23, X23, #8

  (312) 0x435534 ORR	X9, XZR, X20

  (312) 0x435538 ADD	X20, X20, #8

  (312) 0x43553c LDR	X21, [X21, #16]

  (312) 0x435540 STP	X21, X0, [SP, #176]

  (312) 0x435544 ADD	X21, X12, X3,LSL #3

  (312) 0x435548 ORR	X3, XZR, X21

  (312) 0x43554c ADD	X21, X21, #8

  (312) 0x435550 LDR	X0, [SP, #128]

  (312) 0x435554 LDR	X0, [X0, #16]

  (312) 0x435558 STR	X0, [SP, #192]

  (312) 0x43555c LDR	X0, [SP, #136]

  (312) 0x435560 LDR	X19, [X0, #16]

  (312) 0x435564 LDR	X0, [SP, #152]

  (312) 0x435568 STR	X19, [SP, #200]

  (312) 0x43556c ADD	X19, X18, X8,LSL #3

  (312) 0x435570 LDR	X18, [SP, #144]

  (312) 0x435574 ORR	X8, XZR, X19

  (312) 0x435578 ADD	X19, X19, #8

  (312) 0x43557c LDR	X18, [X18, #16]

  (312) 0x435580 STR	X18, [SP, #208]

  (312) 0x435584 ADD	X18, X12, X26,LSL #3

  (312) 0x435588 LDR	X26, [X0, #16]

  (312) 0x43558c ORR	X12, XZR, X18

  (312) 0x435590 ADD	X18, X18, #8

  (312) 0x435594 LDR	X0, [SP, #160]

  (312) 0x435598 STR	X26, [SP, #216]

  (312) 0x43559c LDR	X26, [SP, #176]

  (312) 0x4355a0 ADD	X7, X26, X7,LSL #3

  (312) 0x4355a4 ADD	X11, X26, X11,LSL #3

  (312) 0x4355a8 ADD	X26, X13, X27,LSL #3

  (312) 0x4355ac LDR	X27, [X0, #16]

  (312) 0x4355b0 LDR	X0, [SP, #184]

  (312) 0x4355b4 ORR	X13, XZR, X26

  (312) 0x4355b8 ADD	X26, X26, #8

  (312) 0x4355bc ADD	X17, X0, X17,LSL #3

  (312) 0x4355c0 LDR	X0, [SP, #192]

  (312) 0x4355c4 ADD	X16, X0, X16,LSL #3

  (312) 0x4355c8 LDR	X0, [SP, #168]

  (312) 0x4355cc LDR	X0, [X0, #16]

  (312) 0x4355d0 STR	X0, [SP, #176]

  (312) 0x4355d4 LDR	X0, [SP, #200]

  (312) 0x4355d8 ADD	X2, X0, X2,LSL #3

  (312) 0x4355dc LDR	X0, [SP, #208]

  (312) 0x4355e0 ADD	X15, X0, X15,LSL #3

  (312) 0x4355e4 LDR	X0, [SP, #216]

  (312) 0x4355e8 ADD	X14, X0, X14,LSL #3

  (312) 0x4355ec LDR	X0, [SP, #224]

  (312) 0x4355f0 ADD	X27, X27, X0,LSL #3

  (312) 0x4355f4 LDR	X0, [SP, #176]

  (312) 0x4355f8 ADD	X30, X0, X30,LSL #3

  (312) 0x4355fc MOVZ	X0, #0

    (311) 0x435600 LD1D	{Z21.D}, P7/Z, [X25, X0,LSL #3]

    (311) 0x435604 LD1D	{Z26.D}, P7/Z, [X20, X0,LSL #3]

    (311) 0x435608 LD1D	{Z2.D}, P7/Z, [X23, X0,LSL #3]

    (311) 0x43560c LD1D	{Z7.D}, P7/Z, [X6, X0,LSL #3]

    (311) 0x435610 LD1D	{Z25.D}, P7/Z, [X9, X0,LSL #3]

    (311) 0x435614 LD1D	{Z24.D}, P7/Z, [X5, X0,LSL #3]

    (311) 0x435618 LD1D	{Z0.D}, P7/Z, [X19, X0,LSL #3]

    (311) 0x43561c LD1D	{Z22.D}, P7/Z, [X24, X0,LSL #3]

    (311) 0x435620 LD1D	{Z1.D}, P7/Z, [X26, X0,LSL #3]

    (311) 0x435624 LD1D	{Z3.D}, P7/Z, [X10, X0,LSL #3]

    (311) 0x435628 FADD	Z22.D, P7/M, Z22.D, Z21.D

    (311) 0x43562c FADD	Z3.D, P7/M, Z3.D, Z7.D

    (311) 0x435630 FADD	Z22.D, P7/M, Z22.D, Z26.D

    (311) 0x435634 FADD	Z3.D, P7/M, Z3.D, Z25.D

    (311) 0x435638 FADD	Z22.D, P7/M, Z22.D, Z2.D

    (311) 0x43563c FADD	Z3.D, P7/M, Z3.D, Z24.D

    (311) 0x435640 FMUL	Z1.D, P7/M, Z1.D, Z22.D

    (311) 0x435644 FMUL	Z1.D, P7/M, Z1.D, Z30.D

    (311) 0x435648 LD1D	{Z22.D}, P7/Z, [X2, X0,LSL #3]

    (311) 0x43564c LD1D	{Z28.D}, P7/Z, [X13, X0,LSL #3]

    (311) 0x435650 LD1D	{Z6.D}, P7/Z, [X4, X0,LSL #3]

    (311) 0x435654 LD1D	{Z17.D}, P7/Z, [X22, X0,LSL #3]

    (311) 0x435658 LD1D	{Z16.D}, P7/Z, [X3, X0,LSL #3]

    (311) 0x43565c LD1D	{Z7.D}, P7/Z, [X21, X0,LSL #3]

    (311) 0x435660 LD1D	{Z5.D}, P7/Z, [X7, X0,LSL #3]

    (311) 0x435664 LD1D	{Z18.D}, P7/Z, [X8, X0,LSL #3]

    (311) 0x435668 LD1D	{Z20.D}, P7/Z, [X12, X0,LSL #3]

    (311) 0x43566c LD1D	{Z19.D}, P7/Z, [X18, X0,LSL #3]

    (311) 0x435670 LD1D	{Z27.D}, P7/Z, [X11, X0,LSL #3]

    (311) 0x435674 LD1D	{Z21.D}, P7/Z, [X15, X0,LSL #3]

    (311) 0x435678 MOVPRFX	Z4, Z31

    (311) 0x43567c FMUL	Z4.D, P7/M, Z4.D, Z1.D

    (311) 0x435680 FMUL	Z28.D, P7/M, Z28.D, Z3.D

    (311) 0x435684 LD1D	{Z1.D}, P7/Z, [X16, X0,LSL #3]

    (311) 0x435688 LD1D	{Z3.D}, P7/Z, [X17, X0,LSL #3]

    (311) 0x43568c FADD	Z18.D, P7/M, Z18.D, Z0.D

    (311) 0x435690 FMUL	Z28.D, P7/M, Z28.D, Z30.D

    (311) 0x435694 LD1D	{Z0.D}, P7/Z, [X14, X0,LSL #3]

    (311) 0x435698 FADD	Z6.D, P7/M, Z6.D, Z17.D

    (311) 0x43569c FMLS	Z4.D, P7/M, Z31.D, Z28.D

    (311) 0x4356a0 FADD	Z6.D, P7/M, Z6.D, Z16.D

    (311) 0x4356a4 FADD	Z18.D, P7/M, Z18.D, Z20.D

    (311) 0x4356a8 FADD	Z6.D, P7/M, Z6.D, Z7.D

    (311) 0x4356ac FADD	Z18.D, P7/M, Z18.D, Z19.D

    (311) 0x4356b0 FMUL	Z5.D, P7/M, Z5.D, Z6.D

    (311) 0x4356b4 FMUL	Z27.D, P7/M, Z27.D, Z18.D

    (311) 0x4356b8 FMUL	Z5.D, P7/M, Z5.D, Z30.D

    (311) 0x4356bc MOVPRFX	Z23, Z29

    (311) 0x4356c0 FDIV	Z23.D, P7/M, Z23.D, Z3.D

    (311) 0x4356c4 MOVPRFX	Z25, Z31

    (311) 0x4356c8 FMUL	Z25.D, P7/M, Z25.D, Z5.D

    (311) 0x4356cc FMUL	Z27.D, P7/M, Z27.D, Z30.D

    (311) 0x4356d0 FADD	Z25.D, P7/M, Z25.D, Z4.D

    (311) 0x4356d4 FDIV	Z1.D, P7/M, Z1.D, Z22.D

    (311) 0x4356d8 FMLS	Z25.D, P7/M, Z27.D, Z31.D

    (311) 0x4356dc FDIV	Z21.D, P7/M, Z21.D, Z22.D

    (311) 0x4356e0 MOVPRFX	Z2, Z25

    (311) 0x4356e4 FADD	Z2.D, P7/M, Z2.D, Z3.D

    (311) 0x4356e8 FADD	Z1.D, P7/M, Z1.D, Z21.D

    (311) 0x4356ec MOVPRFX	Z26, Z3

    (311) 0x4356f0 FDIV	Z26.D, P7/M, Z26.D, Z2.D

    (311) 0x4356f4 FMUL	Z25.D, P7/M, Z25.D, Z1.D

    (311) 0x4356f8 FMLS	Z0.D, P7/M, Z25.D, Z23.D

    (311) 0x4356fc ST1D	{Z0.D}, P7, [X27, X0,LSL #3]

    (311) 0x435700 LD1D	{Z24.D}, P7/Z, [X2, X0,LSL #3]

    (311) 0x435704 FMUL	Z26.D, P7/M, Z26.D, Z24.D

    (311) 0x435708 ST1D	{Z26.D}, P7, [X30, X0,LSL #3]

    (311) 0x43570c INCD	X0, ALL

    (311) 0x435710 WHILELO	P7.D, X0, X1

    (311) 0x435714 B.NE	435600

  (312) 0x435718 LDR	W0, [SP, #232]

  (312) 0x43571c ADD	X28, X28, #1

  (312) 0x435720 CMP	W0, W28

  (312) 0x435724 B.LE	435764

  (312) 0x435728 LDR	W3, [SP, #108]

  (312) 0x43572c LDR	W0, [SP, #244]

  (312) 0x435730 LDP	W12, W2, [SP, #236]

  (312) 0x435734 SUB	W4, W0, W3

  (312) 0x435738 CMP	W4, W2

  (312) 0x43573c CSEL	W1, W4, W2, #9

  (312) 0x435740 ADD	W0, W3, W1

  (312) 0x435744 STR	W0, [SP, #108]

  (312) 0x435748 CMP	W3, W0

  (312) 0x43574c B.CC	435410

(313) 0x435750 LDR	W0, [SP, #232]

(313) 0x435754 ADD	X28, X28, #1

(313) 0x435758 STR	W3, [SP, #108]

(313) 0x43575c CMP	W0, W28

(313) 0x435760 B.GT	435728

0x435764 LDP	X23, X24, [SP, #48]

0x435768 LDP	X25, X26, [SP, #64]

0x43576c LDP	X27, X28, [SP, #80]

0x435770 LDP	X19, X20, [SP, #16]

0x435774 LDP	X21, X22, [SP, #32]

0x435778 LDP	X29, X30, [SP], #288

0x43577c RET

0x435780 LDP	X23, X24, [SP, #48]

0x435784 LDP	X19, X20, [SP, #16]

0x435788 LDP	X21, X22, [SP, #32]

0x43578c LDP	X29, X30, [SP], #288

0x435790 RET

0x435794 ADD	W4, W4, #1

0x435798 MOVZ	W0, #0

0x43579c B	435344

Coverage (%)	Name	Source Location	Module
►98.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	GOMP_parallel		libgomp.so.1.0.0
○	PdV(global_variables&, bool)	PdV.cpp:69	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 17.17 cycles (1.46x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 9 bytes.

General properties

nb instructions	96
nb uops	96
loop length	384
used w registers	11
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	3
nb stack references	34

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.00 cycles
front end	12.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.00	9.00	9.00	9.00	1.00	1.00	0.00	0.00	17.17	16.83	17.00	11.00	11.00
cycles	5.00	5.00	9.00	9.00	9.00	9.00	1.00	1.00	0.00	0.00	17.17	16.83	17.00	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	12.00
Dispatch	17.17
DIV/SQRT	10.00-25.00
Overall L1	17.17-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	28%
load	34%
store	31%
mul	12%
add-sub	14%
fma	12%
other	27%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	27%
load	34%
store	31%
mul	12%
add-sub	14%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4352cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W22, W1, [X0, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [X0, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X20, #116]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W1, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP W1, W0, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 435770 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W23, W1, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W0, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 435780 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL W23, W23, W0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W0, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W0, W4, W21, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 435794 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W4, W3, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W4, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #244]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 435780 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FDUP Z30.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
FDUP Z29.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LD1RD {Z31.D}, P7/Z, [X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
UDIV W0, W3, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X2, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X20, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB W1, W0, W1, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W0, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X28, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDR X0, [X20, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W0, [SP, #236]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X0, [X20, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W12, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X2, X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X20, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X20, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X20, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X20, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W2, W19, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W1, W4, W2, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X0, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W0, W3, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #108]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 435750 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 435344 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 17.17 cycles (1.46x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 9 bytes.

General properties

nb instructions	96
nb uops	96
loop length	384
used w registers	11
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	3
nb stack references	34

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.00 cycles
front end	12.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.00	9.00	9.00	9.00	1.00	1.00	0.00	0.00	17.17	16.83	17.00	11.00	11.00
cycles	5.00	5.00	9.00	9.00	9.00	9.00	1.00	1.00	0.00	0.00	17.17	16.83	17.00	11.00	11.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	12.00
Dispatch	17.17
DIV/SQRT	10.00-25.00
Overall L1	17.17-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	28%
load	34%
store	31%
mul	12%
add-sub	14%
fma	12%
other	27%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	27%
load	34%
store	31%
mul	12%
add-sub	14%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4352cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W22, W1, [X0, #120]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [X0, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X20, #116]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W1, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP W1, W0, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 435770 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W23, W1, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W0, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 435780 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MUL W23, W23, W0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W0, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W3, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W0, W4, W21, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	N/A
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 435794 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W3, W4, W3, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W4, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #244]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 435780 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x4b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #240]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FDUP Z30.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
FDUP Z29.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LD1RD {Z31.D}, P7/Z, [X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
UDIV W0, W3, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X2, [X20, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X20, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB W1, W0, W1, W3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W0, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X28, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDR X0, [X20, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W0, [SP, #236]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W1, W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X0, [X20, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W12, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X2, X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X0, [X20, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X20, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #280]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X20, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X20, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #256]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X20, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #264]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X2, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W2, W19, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W1, W4, W2, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X0, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W0, W3, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #108]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 435750 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #288	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
B 435344 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	8.13	11.09
▼Loop 313 - PdV.cpp:71-83 - exec–	0.00	0.00
▼Loop 312 - PdV.cpp:71-83 - exec–	0.02	0.03
○Loop 311 - PdV.cpp:72-83 - exec	8.11	10.77

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