OV - exec - Function viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, ...	Module: exec	Source: viscosity.cpp:36-64 [...]	Coverage (incl. loops): 2.43% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp: 36 - 64

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

0x443d80 STP	X29, X30, [SP, #912]!

0x443d84 ADD	X29, SP, #0

0x443d88 STP	X19, X20, [SP, #16]

0x443d8c LDP	W4, W19, [X0, #64]

0x443d90 LDP	W20, W3, [X0, #56]

0x443d94 ADD	W4, W4, #1

0x443d98 ADD	W19, W19, #2

0x443d9c CMP	W4, W19

0x443da0 B.GE	444090

0x443da4 ADD	W20, W20, #1

0x443da8 STP	X21, X22, [SP, #32]

0x443dac ADD	W21, W3, #2

0x443db0 STP	X25, X26, [SP, #64]

0x443db4 SUB	W25, W19, W4

0x443db8 STR	W4, [SP, #104]

0x443dbc CMP	W20, W21

0x443dc0 B.GE	4440ec

0x443dc4 STP	X23, X24, [SP, #48]

0x443dc8 SUB	W24, W21, W20

0x443dcc ORR	X22, XZR, X0

0x443dd0 MUL	W25, W25, W24

0x443dd4 STP	X27, X28, [SP, #80]

0x443dd8 BL	410670

0x443ddc ORR	W23, WZR, W0

0x443de0 BL	410550

0x443de4 UDIV	W1, W25, W23

0x443de8 ORR	W2, WZR, W0

0x443dec LDR	W4, [SP, #104]

0x443df0 MSUB	W0, W1, W23, W25

0x443df4 CMP	W2, W0

0x443df8 B.CC	4440e0

0x443dfc MADD	W2, W1, W2, W0

0x443e00 ADD	W27, W1, W2

0x443e04 CMP	W2, W27

0x443e08 B.CS	444080

0x443e0c UDIV	W0, W2, W24

0x443e10 ADRP	X3,

0x443e14 LDP	X30, X26, [X22, #16]

0x443e18 FMOV	D31, #0.5000000

0x443e1c LDP	X25, X23, [X22, #32]

0x443e20 LDR	D30, [X3, #344]

0x443e24 LDP	X3, X28, [X22]

0x443e28 LDR	X22, [X22, #48]

0x443e2c STR	X3, [SP, #104]

0x443e30 MSUB	W3, W0, W24, W2

0x443e34 ADD	W0, W0, W4

0x443e38 SBFM	X13, X0, #0, #31

0x443e3c ADD	W0, W3, W20

0x443e40 SUB	W3, W21, W0

(719) 0x443e44 CMP	W1, W3

(719) 0x443e48 CSEL	W8, W1, W3, #9

(719) 0x443e4c ADD	W16, W2, W8

(719) 0x443e50 CMP	W2, W16

(719) 0x443e54 B.CS	4440b4

(719) 0x443e58 LDR	X15, [X26]

(719) 0x443e5c SBFM	X1, X0, #0, #31

(719) 0x443e60 SUB	W8, W8, #1

(719) 0x443e64 ADD	X2, X1, #2

(719) 0x443e68 ADD	X3, X1, #1

(719) 0x443e6c LDR	X10, [X25]

(719) 0x443e70 ADD	X8, X8, X2

(719) 0x443e74 SUB	W11, W13, #1

(719) 0x443e78 SBFM	X11, X11, #0, #31

(719) 0x443e7c ADD	W0, W0, #1

(719) 0x443e80 LDR	X9, [X26, #16]

(719) 0x443e84 ADD	W12, W13, #2

(719) 0x443e88 SBFM	X0, X0, #0, #31

(719) 0x443e8c MUL	X6, X13, X15

(719) 0x443e90 ADD	X21, X13, #1

(719) 0x443e94 LDR	X4, [X22]

(719) 0x443e98 MUL	X11, X11, X15

(719) 0x443e9c MUL	X10, X13, X10

(719) 0x443ea0 ADD	X2, X3, X6

(719) 0x443ea4 LDR	X5, [X23]

(719) 0x443ea8 ADD	X2, X9, X2,LSL #3

(719) 0x443eac SUB	X11, X11, X6

(719) 0x443eb0 LDR	X9, [X25, #16]

(719) 0x443eb4 UBFM	X10, X10, #61, #60

(719) 0x443eb8 SUB	X10, X10, #8

(719) 0x443ebc MADD	X6, X13, X4, X4

(719) 0x443ec0 LDR	X14, [X28, #8]

(719) 0x443ec4 ADD	X12, X14, W12,SXTW #3

(719) 0x443ec8 MUL	X18, X13, X5

(719) 0x443ecc LDR	X17, [X22, #16]

(719) 0x443ed0 SUB	X4, X6, X4

(719) 0x443ed4 ADD	X10, X9, X10

(719) 0x443ed8 LDR	X9, [SP, #104]

(719) 0x443edc ADD	X5, X5, X18

(719) 0x443ee0 ADD	X14, X14, X13,LSL #3

(719) 0x443ee4 LDR	X7, [X23, #16]

(719) 0x443ee8 ADD	X4, X17, X4,LSL #3

(719) 0x443eec ADD	X6, X17, X6,LSL #3

(719) 0x443ef0 LDR	X9, [X9, #8]

(719) 0x443ef4 ADD	X5, X7, X5,LSL #3

(719) 0x443ef8 ADD	X7, X7, X18,LSL #3

(719) 0x443efc HINT	#0

  (720) 0x443f00 LDR	D21, [X4, X1,LSL #3]

  (720) 0x443f04 SUB	X17, X2, #8

  (720) 0x443f08 LDR	D6, [X6, X0,LSL #3]

  (720) 0x443f0c LDR	D27, [X7, X1,LSL #3]

  (720) 0x443f10 LDR	D3, [X5, X1,LSL #3]

  (720) 0x443f14 LDR	D28, [X5, X0,LSL #3]

  (720) 0x443f18 LDR	D5, [X4, X0,LSL #3]

  (720) 0x443f1c FADD	D2, D3, D27

  (720) 0x443f20 LDR	D23, [X6, X1,LSL #3]

  (720) 0x443f24 FADD	D3, D3, D28

  (720) 0x443f28 LDR	D29, [X7, X0,LSL #3]

  (720) 0x443f2c FADD	D18, D5, D21

  (720) 0x443f30 FADD	D5, D5, D6

  (720) 0x443f34 LDR	D17, [X9, X1,LSL #3]

  (720) 0x443f38 LDR	D0, [X14]

  (720) 0x443f3c FADD	D19, D6, D23

  (720) 0x443f40 FSUB	D3, D3, S27

  (720) 0x443f44 LDR	D7, [X17, X15,LSL #3]

  (720) 0x443f48 FADD	D25, D28, D29

  (720) 0x443f4c FSUB	D5, D5, S21

  (720) 0x443f50 LDR	D6, [X17, X11,LSL #3]

  (720) 0x443f54 MOVI	D21, #0

  (720) 0x443f58 LDR	D20, [X12]

  (720) 0x443f5c FSUB	D18, D19, S18

  (720) 0x443f60 FSUB	D3, D3, S29

  (720) 0x443f64 LDUR	D1, [X2, #496]

  (720) 0x443f68 FSUB	D2, D25, S2

  (720) 0x443f6c FSUB	D5, D5, S23

  (720) 0x443f70 LDR	D4, [X2]

  (720) 0x443f74 FSUB	D6, D7, S6

  (720) 0x443f78 LDR	D22, [X9, X0,LSL #3]

  (720) 0x443f7c FADD	D20, D0, D20

  (720) 0x443f80 FMUL	D3, D3, D31

  (720) 0x443f84 FMUL	D5, D5, D31

  (720) 0x443f88 FSUB	D1, D4, S1

  (720) 0x443f8c FMUL	D4, D18, D31

  (720) 0x443f90 FDIV	D20, D6, D20

  (720) 0x443f94 FADD	D22, D17, D22

  (720) 0x443f98 FDIV	D5, D5, D17

  (720) 0x443f9c FDIV	D3, D3, D0

  (720) 0x443fa0 FMUL	D23, D20, D20

  (720) 0x443fa4 FDIV	D22, D1, D22

  (720) 0x443fa8 FDIV	D4, D4, D0

  (720) 0x443fac FADD	D3, D5, D3

  (720) 0x443fb0 FMUL	D5, D2, D31

  (720) 0x443fb4 FMUL	D25, D22, D22

  (720) 0x443fb8 FMUL	D3, D22, D3

  (720) 0x443fbc FDIV	D5, D5, D17

  (720) 0x443fc0 FMUL	D4, D4, D23

  (720) 0x443fc4 FADD	D23, D23, D25

  (720) 0x443fc8 FMAXNM	D23, D23, D30

  (720) 0x443fcc FMADD	D4, D5, D25, D4

  (720) 0x443fd0 FMADD	D3, D3, D20, D4

  (720) 0x443fd4 FDIV	D23, D3, D23

  (720) 0x443fd8 FCMPE	D23, D21

  (720) 0x443fdc B.GT	444060

  (720) 0x443fe0 FMUL	D2, D17, D2

  (720) 0x443fe4 FMADD	D2, D0, D18, D2

  (720) 0x443fe8 FCMPE	D2, D21

  (720) 0x443fec B.GE	444060

  (720) 0x443ff0 FCMPE	D22, D21

  (720) 0x443ff4 FABS	D19, D22

  (720) 0x443ff8 FMAXNM	D19, D19, D30

  (720) 0x443ffc B.MI	44409c

  (720) 0x444000 FMOV	D26, #1.0000000

  (720) 0x444004 FABS	D20, D20

  (720) 0x444008 FMAXNM	D20, D20, D30

  (720) 0x44400c FMUL	D20, D20, D26

  (720) 0x444010 LDR	X18, [X30]

  (720) 0x444014 LDR	X17, [X30, #16]

  (720) 0x444018 FMUL	D24, D20, D20

  (720) 0x44401c MADD	X1, X13, X18, X1

  (720) 0x444020 LDR	D16, [X17, X1,LSL #3]

  (720) 0x444024 FMADD	D24, D19, D19, D24

  (720) 0x444028 FADD	D16, D16, D16

  (720) 0x44402c FSQRT	D24, D24

  (720) 0x444030 FMUL	D0, D24, D0

  (720) 0x444034 FMUL	D24, D24, D17

  (720) 0x444038 FDIV	D0, D0, D20

  (720) 0x44403c FDIV	D24, D24, D19

  (720) 0x444040 FABS	D0, D0

  (720) 0x444044 FABS	D24, D24

  (720) 0x444048 FMINNM	D24, D0, D24

  (720) 0x44404c FMUL	D24, D24, D24

  (720) 0x444050 FMUL	D24, D16, D24

  (720) 0x444054 FMUL	D24, D24, D23

  (720) 0x444058 FMUL	D21, D24, D23

  (720) 0x44405c HINT	#0

  (720) 0x444060 STR	D21, [X10, X0,LSL #3]

  (720) 0x444064 ADD	X0, X0, #1

  (720) 0x444068 ADD	X2, X2, #8

  (720) 0x44406c ORR	X1, XZR, X3

  (720) 0x444070 CMP	X0, X8

  (720) 0x444074 B.EQ	4440c0

  (720) 0x444078 ADD	X3, X3, #1

  (720) 0x44407c B	443f00

0x444080 LDP	X21, X22, [SP, #32]

0x444084 LDP	X23, X24, [SP, #48]

0x444088 LDP	X25, X26, [SP, #64]

0x44408c LDP	X27, X28, [SP, #80]

0x444090 LDP	X19, X20, [SP, #16]

0x444094 LDP	X29, X30, [SP], #112

0x444098 RET

  (720) 0x44409c FNEG	D1, D19

  (720) 0x4440a0 FCMPE	D19, #0

  (720) 0x4440a4 FMOV	D26, #-1.0000000

  (720) 0x4440a8 FMOV	D19, D1

  (720) 0x4440ac B.GT	444004

  (720) 0x4440b0 B	444000

(719) 0x4440b4 ORR	W16, WZR, W2

(719) 0x4440b8 ADD	X21, X13, #1

(719) 0x4440bc HINT	#0

(719) 0x4440c0 ORR	X13, XZR, X21

(719) 0x4440c4 CMP	W19, W21

(719) 0x4440c8 B.LE	444080

(719) 0x4440cc SUB	W1, W27, W16

(719) 0x4440d0 ORR	W2, WZR, W16

(719) 0x4440d4 ORR	W3, WZR, W24

(719) 0x4440d8 ORR	W0, WZR, W20

(719) 0x4440dc B	443e44

0x4440e0 ADD	W1, W1, #1

0x4440e4 MOVZ	W0, #0

0x4440e8 B	443dfc

0x4440ec LDP	X21, X22, [SP, #32]

0x4440f0 LDP	X25, X26, [SP, #64]

0x4440f4 B	444090

0x4440f8 HINT	#0

0x4440fc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	GOMP_parallel		libgomp.so.1.0.0
○	viscosity(global_variables&)	viscosity.cpp:76	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:64	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:60	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.00 cycles (3.13x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	64
nb uops	62
loop length	256
used w registers	13
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.75 cycles
front end	7.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	7.75	7.75	7.75	7.75	0.25	0.25	0.25	0.25	8.00	8.00	8.00	4.00	4.00
cycles	4.50	4.50	7.75	7.75	7.75	7.75	0.25	0.25	0.25	0.25	8.00	8.00	8.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.75
Dispatch	8.00
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	30%
load	42%
store	42%
mul	12%
add-sub	14%
fma	12%
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	30%
load	42%
store	42%
mul	12%
add-sub	14%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 443d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W4, W19, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP W20, W3, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 444090 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W21, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W25, W19, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W20, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4440ec <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W24, W21, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL W25, W25, W24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W23, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W25, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MSUB W0, W1, W23, W25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 4440e0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W27, W1, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 444080 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W2, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ADRP X3, <452e10>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X30, X26, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
FMOV D31, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X25, X23, [X22, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR D30, [X3, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X3, X28, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X22, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MSUB W3, W0, W24, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W0, W0, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X13, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W0, W3, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W3, W21, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 443dfc <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 444090 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 30% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.00 cycles (3.13x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:37

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 3 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	64
nb uops	62
loop length	256
used w registers	13
used x registers	16
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	0
used z registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.75 cycles
front end	7.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	7.75	7.75	7.75	7.75	0.25	0.25	0.25	0.25	8.00	8.00	8.00	4.00	4.00
cycles	4.50	4.50	7.75	7.75	7.75	7.75	0.25	0.25	0.25	0.25	8.00	8.00	8.00	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.75
Dispatch	8.00
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	30%
load	42%
store	42%
mul	12%
add-sub	14%
fma	12%
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	30%
load	42%
store	42%
mul	12%
add-sub	14%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.12 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 443d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W4, W19, [X0, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP W20, W3, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 444090 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W21, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W25, W19, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W20, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4440ec <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W24, W21, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL W25, W25, W24	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W23, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W1, W25, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W4, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
MSUB W0, W1, W23, W25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 4440e0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W27, W1, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 444080 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x300>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W2, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ADRP X3, <452e10>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X30, X26, [X22, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
FMOV D31, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDP X25, X23, [X22, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDR D30, [X3, #344]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X3, X28, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X22, [X22, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
MSUB W3, W0, W24, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD W0, W0, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X13, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W0, W3, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB W3, W21, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #112	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 443dfc <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
B 444090 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x310>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	2.43	3.32
▼Loop 719 - viscosity.cpp:38-64 - exec–	0.00	0.02
○Loop 720 - viscosity.cpp:39-64 - exec	2.42	3.22

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Matching between your function (in the source code) and the binary function

General properties

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Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code