OV - exec - Function accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D< ...	Module: exec	Source: accelerate.cpp:40-53 [...]	Coverage (incl. loops): 7.26% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp: 40 - 53

--------------------------------------------------------------------------------

40: #pragma omp parallel for simd collapse(2)

41:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

42:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

43:       double stepbymass_s = halfdt / ((density0(i - 1, j - 1) * volume(i - 1, j - 1) + density0(i - 1, j + 0) * volume(i - 1, j + 0) +

44:                                        density0(i, j) * volume(i, j) + density0(i + 0, j - 1) * volume(i + 0, j - 1)) *

45:                                       0.25);

46:       xvel1(i, j) = xvel0(i, j) - stepbymass_s * (xarea(i, j) * (pressure(i, j) - pressure(i - 1, j + 0)) +

47:                                                   xarea(i + 0, j - 1) * (pressure(i + 0, j - 1) - pressure(i - 1, j - 1)));

48:       yvel1(i, j) = yvel0(i, j) - stepbymass_s * (yarea(i, j) * (pressure(i, j) - pressure(i + 0, j - 1)) +

49:                                                   yarea(i - 1, j + 0) * (pressure(i - 1, j + 0) - pressure(i - 1, j - 1)));

50:       xvel1(i, j) = xvel1(i, j) - stepbymass_s * (xarea(i, j) * (viscosity(i, j) - viscosity(i - 1, j + 0)) +

51:                                                   xarea(i + 0, j - 1) * (viscosity(i + 0, j - 1) - viscosity(i - 1, j - 1)));

52:       yvel1(i, j) = yvel1(i, j) - stepbymass_s * (yarea(i, j) * (viscosity(i, j) - viscosity(i + 0, j - 1)) +

53:                                                   yarea(i - 1, j + 0) * (viscosity(i - 1, j + 0) - viscosity(i - 1, j - 1)));

0x428ee0 STP	X29, X30, [SP, #800]!

0x428ee4 ADD	X29, SP, #0

0x428ee8 STP	X19, X20, [SP, #16]

0x428eec ORR	X20, XZR, X0

0x428ef0 STP	X21, X22, [SP, #32]

0x428ef4 LDP	W22, W1, [X0, #96]

0x428ef8 LDR	W0, [X0, #88]

0x428efc LDR	W3, [X20, #92]

0x428f00 ADD	W1, W1, #3

0x428f04 ADD	W22, W22, #1

0x428f08 ADD	W0, W0, #1

0x428f0c STP	W1, W0, [SP, #184]

0x428f10 CMP	W22, W1

0x428f14 B.GE	42932c

0x428f18 ADD	W19, W3, #3

0x428f1c STP	X23, X24, [SP, #48]

0x428f20 SUB	W23, W1, W22

0x428f24 CMP	W0, W19

0x428f28 B.GE	42933c

0x428f2c SUB	W0, W19, W0

0x428f30 MUL	W23, W23, W0

0x428f34 STR	W0, [SP, #192]

0x428f38 BL	410670

0x428f3c ORR	W21, WZR, W0

0x428f40 BL	410550

0x428f44 UDIV	W4, W23, W21

0x428f48 ORR	W2, WZR, W0

0x428f4c MSUB	W0, W4, W21, W23

0x428f50 CMP	W2, W0

0x428f54 B.CC	429350

0x428f58 MADD	W2, W4, W2, W0

0x428f5c ADD	W0, W4, W2

0x428f60 STR	W0, [SP, #196]

0x428f64 CMP	W2, W0

0x428f68 B.CS	42933c

0x428f6c LDR	W1, [SP, #192]

0x428f70 PTRUE	P7.B, ALL

0x428f74 FDUP	Z30.D, #80

0x428f78 STP	X25, X26, [SP, #64]

0x428f7c STP	X27, X28, [SP, #80]

0x428f80 CNTD	X27, ALL

0x428f84 LD1RD	{Z31.D}, P7/Z, [X20, #10]

0x428f88 UDIV	W0, W2, W1

0x428f8c LDR	X3, [X20]

0x428f90 LDR	X28, [X20, #64]

0x428f94 STR	X3, [SP, #120]

0x428f98 LDR	X3, [X20, #8]

0x428f9c ORR	X26, XZR, X28

0x428fa0 MSUB	W1, W0, W1, W2

0x428fa4 ADD	W0, W0, W22

0x428fa8 SBFM	X0, X0, #0, #31

0x428fac STR	X3, [SP, #136]

0x428fb0 LDR	X3, [X20, #16]

0x428fb4 STR	X0, [SP, #96]

0x428fb8 LDR	X0, [X20, #48]

0x428fbc STR	X3, [SP, #208]

0x428fc0 LDR	X3, [X20, #24]

0x428fc4 STR	X0, [SP, #112]

0x428fc8 LDR	W0, [SP, #188]

0x428fcc STR	X3, [SP, #200]

0x428fd0 LDR	X3, [X20, #32]

0x428fd4 ADD	W1, W1, W0

0x428fd8 LDR	X0, [X20, #56]

0x428fdc ORR	W6, WZR, W1

0x428fe0 STR	X3, [SP, #216]

0x428fe4 LDR	X3, [X20, #40]

0x428fe8 STR	X0, [SP, #128]

0x428fec LDR	X0, [X20, #72]

0x428ff0 STR	X3, [SP, #152]

0x428ff4 SUB	W3, W19, W1

0x428ff8 CMP	W4, W3

0x428ffc CSEL	W4, W4, W3, #9

0x429000 STR	X0, [SP, #144]

0x429004 ADD	W0, W2, W4

0x429008 STR	W0, [SP, #108]

0x42900c CMP	W2, W0

0x429010 B.CS	429300

0x429014 HINT	#0

0x429018 HINT	#0

0x42901c HINT	#0

  (154) 0x429020 ORR	W2, WZR, W4

  (154) 0x429024 LDR	X4, [SP, #152]

  (154) 0x429028 SBFM	X6, X6, #0, #31

  (154) 0x42902c LDP	X9, X7, [SP, #112]

  (154) 0x429030 MOVZ	X0, #0

  (154) 0x429034 WHILELO	P7.D, XZR, X2

  (154) 0x429038 LDP	X12, X13, [SP, #200]

  (154) 0x42903c LDP	X10, X3, [SP, #128]

  (154) 0x429040 LDR	X11, [SP, #96]

  (154) 0x429044 LDR	X4, [X4]

  (154) 0x429048 LDR	X30, [X7]

  (154) 0x42904c SUB	W1, W11, #1

  (154) 0x429050 SBFM	X1, X1, #0, #31

  (154) 0x429054 LDR	X19, [X9]

  (154) 0x429058 MADD	X9, X4, X11, X6

  (154) 0x42905c LDR	X15, [SP, #216]

  (154) 0x429060 MADD	X7, X1, X4, X6

  (154) 0x429064 LDP	X5, X4, [SP, #144]

  (154) 0x429068 MADD	X19, X11, X19, X6

  (154) 0x42906c LDR	X25, [X12]

  (154) 0x429070 LDR	X24, [X13]

  (154) 0x429074 LDR	X28, [X15]

  (154) 0x429078 MADD	X16, X1, X25, X6

  (154) 0x42907c LDR	X17, [X10]

  (154) 0x429080 MADD	X25, X11, X25, X6

  (154) 0x429084 MADD	X14, X1, X24, X6

  (154) 0x429088 LDR	X10, [X5]

  (154) 0x42908c MADD	X24, X11, X24, X6

  (154) 0x429090 UBFM	X16, X16, #61, #60

  (154) 0x429094 MADD	X8, X1, X28, X6

  (154) 0x429098 UBFM	X25, X25, #61, #60

  (154) 0x42909c SUB	X23, X16, #8

  (154) 0x4290a0 LDR	X18, [X26]

  (154) 0x4290a4 MADD	X28, X28, X11, X6

  (154) 0x4290a8 SUB	X22, X25, #8

  (154) 0x4290ac MADD	X17, X11, X17, X6

  (154) 0x4290b0 UBFM	X24, X24, #61, #60

  (154) 0x4290b4 UBFM	X14, X14, #61, #60

  (154) 0x4290b8 LDR	X3, [X3]

  (154) 0x4290bc MADD	X1, X1, X30, X6

  (154) 0x4290c0 SUB	X21, X14, #8

  (154) 0x4290c4 MADD	X30, X30, X11, X6

  (154) 0x4290c8 SUB	X20, X24, #8

  (154) 0x4290cc LDR	X5, [X15, #16]

  (154) 0x4290d0 MADD	X18, X11, X18, X6

  (154) 0x4290d4 LDR	X15, [X12, #16]

  (154) 0x4290d8 MADD	X3, X11, X3, X6

  (154) 0x4290dc MADD	X11, X11, X10, X6

  (154) 0x4290e0 LDR	X6, [SP, #136]

  (154) 0x4290e4 ADD	X12, X5, X28,LSL #3

  (154) 0x4290e8 LDR	X4, [X4, #16]

  (154) 0x4290ec STR	X11, [SP, #176]

  (154) 0x4290f0 ADD	X23, X15, X23

  (154) 0x4290f4 ADD	X16, X15, X16

  (154) 0x4290f8 LDR	X13, [X13, #16]

  (154) 0x4290fc ADD	X22, X15, X22

  (154) 0x429100 ADD	X15, X15, X25

  (154) 0x429104 LDR	X11, [X6, #16]

  (154) 0x429108 ADD	X25, X4, X9,LSL #3

  (154) 0x42910c SUB	X9, X12, #8

  (154) 0x429110 LDR	X6, [SP, #120]

  (154) 0x429114 ADD	X10, X4, X7,LSL #3

  (154) 0x429118 ADD	X21, X13, X21

  (154) 0x42911c ADD	X14, X13, X14

  (154) 0x429120 ADD	X20, X13, X20

  (154) 0x429124 ADD	X13, X13, X24

  (154) 0x429128 STR	X11, [SP, #160]

  (154) 0x42912c ADD	X11, X5, X8,LSL #3

  (154) 0x429130 ORR	X5, XZR, X12

  (154) 0x429134 LDR	X12, [SP, #112]

  (154) 0x429138 ORR	X7, XZR, X10

  (154) 0x42913c ORR	X4, XZR, X25

  (154) 0x429140 ORR	X8, XZR, X11

  (154) 0x429144 SUB	X10, X10, #8

  (154) 0x429148 LDR	X6, [X6, #16]

  (154) 0x42914c SUB	X25, X25, #8

  (154) 0x429150 SUB	X11, X11, #8

  (154) 0x429154 LDR	X28, [X12, #16]

  (154) 0x429158 LDR	X24, [SP, #128]

  (154) 0x42915c ADD	X1, X6, X1,LSL #3

  (154) 0x429160 ADD	X6, X6, X30,LSL #3

  (154) 0x429164 LDR	X30, [SP, #160]

  (154) 0x429168 ADD	X19, X28, X19,LSL #3

  (154) 0x42916c LDR	X12, [X26, #16]

  (154) 0x429170 LDR	X24, [X24, #16]

  (154) 0x429174 ADD	X18, X12, X18,LSL #3

  (154) 0x429178 LDR	X12, [SP, #176]

  (154) 0x42917c STR	X24, [SP, #168]

  (154) 0x429180 ADD	X24, X30, X3,LSL #3

  (154) 0x429184 LDR	X30, [SP, #144]

  (154) 0x429188 ORR	X3, XZR, X24

  (154) 0x42918c SUB	X28, X24, #8

  (154) 0x429190 LDR	X24, [SP, #168]

  (154) 0x429194 LDR	X30, [X30, #16]

  (154) 0x429198 ADD	X17, X24, X17,LSL #3

  (154) 0x42919c ADD	X30, X30, X12,LSL #3

    (153) 0x4291a0 LD1D	{Z20.D}, P7/Z, [X21, X0,LSL #3]

    (153) 0x4291a4 LD1D	{Z2.D}, P7/Z, [X22, X0,LSL #3]

    (153) 0x4291a8 LD1D	{Z3.D}, P7/Z, [X20, X0,LSL #3]

    (153) 0x4291ac LD1D	{Z7.D}, P7/Z, [X15, X0,LSL #3]

    (153) 0x4291b0 LD1D	{Z24.D}, P7/Z, [X13, X0,LSL #3]

    (153) 0x4291b4 LD1D	{Z16.D}, P7/Z, [X16, X0,LSL #3]

    (153) 0x4291b8 LD1D	{Z6.D}, P7/Z, [X14, X0,LSL #3]

    (153) 0x4291bc LD1D	{Z4.D}, P7/Z, [X9, X0,LSL #3]

    (153) 0x4291c0 LD1D	{Z28.D}, P7/Z, [X11, X0,LSL #3]

    (153) 0x4291c4 LD1D	{Z0.D}, P7/Z, [X1, X0,LSL #3]

    (153) 0x4291c8 LD1D	{Z29.D}, P7/Z, [X23, X0,LSL #3]

    (153) 0x4291cc LD1D	{Z5.D}, P7/Z, [X5, X0,LSL #3]

    (153) 0x4291d0 LD1D	{Z1.D}, P7/Z, [X6, X0,LSL #3]

    (153) 0x4291d4 LD1D	{Z27.D}, P7/Z, [X8, X0,LSL #3]

    (153) 0x4291d8 LD1D	{Z25.D}, P7/Z, [X19, X0,LSL #3]

    (153) 0x4291dc FSUB	Z5.D, P7/M, Z5.D, Z4.D

    (153) 0x4291e0 FSUB	Z27.D, P7/M, Z27.D, Z28.D

    (153) 0x4291e4 FMUL	Z29.D, P7/M, Z29.D, Z20.D

    (153) 0x4291e8 FMUL	Z1.D, P7/M, Z1.D, Z5.D

    (153) 0x4291ec FMLA	Z29.D, P7/M, Z3.D, Z2.D

    (153) 0x4291f0 FMLA	Z1.D, P7/M, Z27.D, Z0.D

    (153) 0x4291f4 FMLA	Z29.D, P7/M, Z24.D, Z7.D

    (153) 0x4291f8 FMLA	Z29.D, P7/M, Z6.D, Z16.D

    (153) 0x4291fc FMUL	Z29.D, P7/M, Z29.D, Z30.D

    (153) 0x429200 MOVPRFX	Z26, Z31

    (153) 0x429204 FDIV	Z26.D, P7/M, Z26.D, Z29.D

    (153) 0x429208 FMLS	Z25.D, P7/M, Z1.D, Z26.D

    (153) 0x42920c ADD	X24, X18, X0,LSL #3

    (153) 0x429210 ADD	X12, X30, X0,LSL #3

    (153) 0x429214 ST1D	{Z25.D}, P7, [X24, MUL VL]

    (153) 0x429218 LD1D	{Z22.D}, P7/Z, [X5, X0,LSL #3]

    (153) 0x42921c LD1D	{Z23.D}, P7/Z, [X8, X0,LSL #3]

    (153) 0x429220 LD1D	{Z18.D}, P7/Z, [X3, X0,LSL #3]

    (153) 0x429224 LD1D	{Z19.D}, P7/Z, [X9, X0,LSL #3]

    (153) 0x429228 LD1D	{Z20.D}, P7/Z, [X11, X0,LSL #3]

    (153) 0x42922c LD1D	{Z21.D}, P7/Z, [X28, X0,LSL #3]

    (153) 0x429230 LD1D	{Z17.D}, P7/Z, [X17, X0,LSL #3]

    (153) 0x429234 FSUB	Z22.D, P7/M, Z22.D, Z23.D

    (153) 0x429238 FSUB	Z19.D, P7/M, Z19.D, Z20.D

    (153) 0x42923c FMUL	Z18.D, P7/M, Z18.D, Z22.D

    (153) 0x429240 FMLA	Z18.D, P7/M, Z19.D, Z21.D

    (153) 0x429244 FMLS	Z17.D, P7/M, Z18.D, Z26.D

    (153) 0x429248 ST1D	{Z17.D}, P7, [X12, MUL VL]

    (153) 0x42924c LD1D	{Z3.D}, P7/Z, [X6, X0,LSL #3]

    (153) 0x429250 LD1D	{Z7.D}, P7/Z, [X4, X0,LSL #3]

    (153) 0x429254 LD1D	{Z16.D}, P7/Z, [X25, X0,LSL #3]

    (153) 0x429258 LD1D	{Z6.D}, P7/Z, [X1, X0,LSL #3]

    (153) 0x42925c LD1D	{Z4.D}, P7/Z, [X7, X0,LSL #3]

    (153) 0x429260 LD1D	{Z2.D}, P7/Z, [X24, MUL VL]

    (153) 0x429264 FSUB	Z7.D, P7/M, Z7.D, Z16.D

    (153) 0x429268 LD1D	{Z5.D}, P7/Z, [X10, X0,LSL #3]

    (153) 0x42926c FMUL	Z3.D, P7/M, Z3.D, Z7.D

    (153) 0x429270 FSUB	Z4.D, P7/M, Z4.D, Z5.D

    (153) 0x429274 FMLA	Z3.D, P7/M, Z4.D, Z6.D

    (153) 0x429278 FMLS	Z2.D, P7/M, Z3.D, Z26.D

    (153) 0x42927c ST1D	{Z2.D}, P7, [X24, MUL VL]

    (153) 0x429280 LD1D	{Z0.D}, P7/Z, [X4, X0,LSL #3]

    (153) 0x429284 LD1D	{Z1.D}, P7/Z, [X7, X0,LSL #3]

    (153) 0x429288 LD1D	{Z24.D}, P7/Z, [X3, X0,LSL #3]

    (153) 0x42928c LD1D	{Z27.D}, P7/Z, [X25, X0,LSL #3]

    (153) 0x429290 LD1D	{Z28.D}, P7/Z, [X10, X0,LSL #3]

    (153) 0x429294 LD1D	{Z25.D}, P7/Z, [X28, X0,LSL #3]

    (153) 0x429298 LD1D	{Z29.D}, P7/Z, [X12, MUL VL]

    (153) 0x42929c FSUB	Z0.D, P7/M, Z0.D, Z1.D

    (153) 0x4292a0 FSUB	Z27.D, P7/M, Z27.D, Z28.D

    (153) 0x4292a4 FMUL	Z24.D, P7/M, Z24.D, Z0.D

    (153) 0x4292a8 FMLA	Z24.D, P7/M, Z27.D, Z25.D

    (153) 0x4292ac FMLS	Z29.D, P7/M, Z24.D, Z26.D

    (153) 0x4292b0 ST1D	{Z29.D}, P7, [X12, MUL VL]

    (153) 0x4292b4 ADD	X0, X0, X27

    (153) 0x4292b8 WHILELO	P7.D, X0, X2

    (153) 0x4292bc B.NE	4291a0

  (154) 0x4292c0 LDR	X0, [SP, #96]

  (154) 0x4292c4 LDR	W1, [SP, #184]

  (154) 0x4292c8 ADD	X0, X0, #1

  (154) 0x4292cc STR	X0, [SP, #96]

  (154) 0x4292d0 CMP	W1, W0

  (154) 0x4292d4 B.LE	429320

  (154) 0x4292d8 LDR	W2, [SP, #108]

  (154) 0x4292dc LDR	W0, [SP, #196]

  (154) 0x4292e0 LDP	W6, W3, [SP, #188]

  (154) 0x4292e4 SUB	W4, W0, W2

  (154) 0x4292e8 CMP	W4, W3

  (154) 0x4292ec CSEL	W4, W4, W3, #9

  (154) 0x4292f0 ADD	W0, W2, W4

  (154) 0x4292f4 STR	W0, [SP, #108]

  (154) 0x4292f8 CMP	W2, W0

  (154) 0x4292fc B.CC	429020

(155) 0x429300 LDR	X0, [SP, #96]

(155) 0x429304 STR	W2, [SP, #108]

(155) 0x429308 LDR	W1, [SP, #184]

(155) 0x42930c ADD	X0, X0, #1

(155) 0x429310 STR	X0, [SP, #96]

(155) 0x429314 CMP	W1, W0

(155) 0x429318 B.GT	4292d8

0x42931c HINT	#0

0x429320 LDP	X23, X24, [SP, #48]

0x429324 LDP	X25, X26, [SP, #64]

0x429328 LDP	X27, X28, [SP, #80]

0x42932c LDP	X19, X20, [SP, #16]

0x429330 LDP	X21, X22, [SP, #32]

0x429334 LDP	X29, X30, [SP], #224

0x429338 RET

0x42933c LDP	X23, X24, [SP, #48]

0x429340 LDP	X19, X20, [SP, #16]

0x429344 LDP	X21, X22, [SP, #32]

0x429348 LDP	X29, X30, [SP], #224

0x42934c RET

0x429350 ADD	W4, W4, #1

0x429354 MOVZ	W0, #0

0x429358 B	428f58

0x42935c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.43+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	GOMP_parallel		libgomp.so.1.0.0
○	accelerate(global_variables&)	accelerate.cpp:66	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 26% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 15.50 cycles (1.61x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:42
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:42

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 9 bytes.

General properties

nb instructions	97
nb uops	92
loop length	388
used w registers	11
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	2
nb stack references	32

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.50	9.50	9.50	9.50	0.50	0.50	0.00	0.00	15.50	15.17	15.33	10.00	10.00
cycles	5.00	5.00	9.50	9.50	9.50	9.50	0.50	0.50	0.00	0.00	15.50	15.17	15.33	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	11.50
Dispatch	15.50
DIV/SQRT	10.00-25.00
Overall L1	15.50-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	27%
load	34%
store	30%
mul	12%
add-sub	14%
fma	12%
other	21%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	26%
load	34%
store	30%
mul	12%
add-sub	14%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 428ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #800]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W22, W1, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W3, [X20, #92]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W1, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W1, W0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42932c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W23, W1, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W0, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42933c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x45c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL W23, W23, W0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W0, W4, W21, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 429350 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W4, W2, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #196]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42933c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x45c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FDUP Z30.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CNTD X27, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LD1RD {Z31.D}, P7/Z, [X20, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
UDIV W0, W2, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X28, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X26, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MSUB W1, W0, W1, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W0, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X0, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W0, [SP, #188]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W1, W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X0, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W6, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X3, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W3, W19, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W4, W4, W3, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W0, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 429300 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #224	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #224	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 428f58 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 26% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 15.50 cycles (1.61x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:42
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:42

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 9 bytes.

General properties

nb instructions	97
nb uops	92
loop length	388
used w registers	11
used x registers	15
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	2
nb stack references	32

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.50 cycles
front end	11.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.00	5.00	9.50	9.50	9.50	9.50	0.50	0.50	0.00	0.00	15.50	15.17	15.33	10.00	10.00
cycles	5.00	5.00	9.50	9.50	9.50	9.50	0.50	0.50	0.00	0.00	15.50	15.17	15.33	10.00	10.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	11.50
Dispatch	15.50
DIV/SQRT	10.00-25.00
Overall L1	15.50-25.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	27%
load	34%
store	30%
mul	12%
add-sub	14%
fma	12%
other	21%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	26%
load	34%
store	30%
mul	12%
add-sub	14%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 428ee0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #800]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W22, W1, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W3, [X20, #92]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W1, W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP W1, W0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42932c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x44c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W3, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W23, W1, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W0, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42933c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x45c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W0, W19, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MUL W23, W23, W0	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W0, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W4, W23, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W0, W4, W21, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 429350 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W4, W2, W0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #196]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42933c <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x45c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
PTRUE P7.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
FDUP Z30.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CNTD X27, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LD1RD {Z31.D}, P7/Z, [X20, #10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
UDIV W0, W2, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X3, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X28, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X26, XZR, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MSUB W1, W0, W1, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W0, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SBFM X0, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X3, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W0, [SP, #188]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD W1, W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X0, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR W6, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR X3, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X3, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X0, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X3, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W3, W19, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W4, W4, W3, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X0, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD W0, W2, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #108]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 429300 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #224	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #224	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 428f58 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	7.26	9.91
▼Loop 155 - accelerate.cpp:42-53 - exec–	0.00	0.00
▼Loop 154 - accelerate.cpp:42-53 - exec–	0.01	0.02
○Loop 153 - accelerate.cpp:43-53 - exec	7.25	9.63

Report Configuration

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code