OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:44-48 [...]	Coverage (incl. loops): 1.35% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:           pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

48:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x429500 STP	X29, X30, [SP, #944]!

0x429504 ADD	X29, SP, #0

0x429508 STP	X19, X20, [SP, #16]

0x42950c STP	X23, X24, [SP, #48]

0x429510 ORR	X23, XZR, X0

0x429514 STP	X25, X26, [SP, #64]

0x429518 LDP	W25, W19, [X0, #48]

0x42951c LDR	W20, [X0, #40]

0x429520 LDR	W0, [X0, #44]

0x429524 SUB	W25, W25, #1

0x429528 ADD	W19, W19, #4

0x42952c CMP	W25, W19

0x429530 B.GE	4296d0

0x429534 SUB	W20, W20, #1

0x429538 STP	X21, X22, [SP, #32]

0x42953c ADD	W22, W0, #4

0x429540 SUB	W26, W19, W25

0x429544 CMP	W20, W22

0x429548 B.GE	4296cc

0x42954c SUB	W21, W22, W20

0x429550 BL	410670

0x429554 MUL	W26, W26, W21

0x429558 ORR	W24, WZR, W0

0x42955c BL	410550

0x429560 ORR	W2, WZR, W0

0x429564 UDIV	W1, W26, W24

0x429568 MSUB	W0, W1, W24, W26

0x42956c CMP	W2, W0

0x429570 B.CC	4296e4

0x429574 MADD	W2, W1, W2, W0

0x429578 ADD	W16, W1, W2

0x42957c CMP	W2, W16

0x429580 B.CS	4296cc

0x429584 UDIV	W0, W2, W21

0x429588 LDR	X11, [X23, #32]

0x42958c CNTD	X10, ALL

0x429590 LDP	X15, X14, [X23]

0x429594 LDP	X13, X12, [X23, #16]

0x429598 MSUB	W9, W0, W21, W2

0x42959c ADD	W0, W0, W25

0x4295a0 SBFM	X30, X0, #0, #31

0x4295a4 ADD	W9, W9, W20

0x4295a8 SUB	W0, W22, W9

0x4295ac CMP	W1, W0

0x4295b0 CSEL	X1, X1, X0, #9

0x4295b4 ADD	W17, W2, W1

0x4295b8 CMP	W2, W17

0x4295bc B.CS	4296b8

  (158) 0x4295c0 LDR	X5, [X13]

  (158) 0x4295c4 SBFM	X9, X9, #0, #31

  (158) 0x4295c8 ADD	X18, X30, #1

  (158) 0x4295cc MOVZ	X0, #0

  (158) 0x4295d0 WHILELO	P7.D, XZR, X1

  (158) 0x4295d4 LDR	X3, [X11]

  (158) 0x4295d8 LDR	X4, [X12]

  (158) 0x4295dc MADD	X8, X30, X5, X5

  (158) 0x4295e0 LDR	X2, [X14]

  (158) 0x4295e4 MADD	X3, X30, X3, X9

  (158) 0x4295e8 LDR	X7, [X15]

  (158) 0x4295ec SUB	X6, X8, X5

  (158) 0x4295f0 ADD	X8, X8, X9

  (158) 0x4295f4 MADD	X4, X30, X4, X9

  (158) 0x4295f8 ADD	X6, X6, X9

  (158) 0x4295fc LDR	X23, [X14, #16]

  (158) 0x429600 MADD	X2, X30, X2, X9

  (158) 0x429604 LDR	X22, [X13, #16]

  (158) 0x429608 MADD	X7, X30, X7, X9

  (158) 0x42960c LDR	X24, [X12, #16]

  (158) 0x429610 ADD	X2, X2, #1

  (158) 0x429614 ADD	X5, X23, X2,LSL #3

  (158) 0x429618 LDR	X9, [X11, #16]

  (158) 0x42961c ADD	X6, X22, X6,LSL #3

  (158) 0x429620 ORR	X2, XZR, X5

  (158) 0x429624 SUB	X5, X5, #8

  (158) 0x429628 LDR	X30, [X15, #16]

  (158) 0x42962c ADD	X8, X22, X8,LSL #3

  (158) 0x429630 ADD	X4, X24, X4,LSL #3

  (158) 0x429634 ADD	X3, X9, X3,LSL #3

  (158) 0x429638 ADD	X7, X30, X7,LSL #3

  (158) 0x42963c HINT	#0

    (157) 0x429640 LD1D	{Z0.D}, P7/Z, [X2, X0,LSL #3]

    (157) 0x429644 LD1D	{Z3.D}, P7/Z, [X5, X0,LSL #3]

    (157) 0x429648 LD1D	{Z2.D}, P7/Z, [X8, X0,LSL #3]

    (157) 0x42964c LD1D	{Z1.D}, P7/Z, [X6, X0,LSL #3]

    (157) 0x429650 LD1D	{Z31.D}, P7/Z, [X7, X0,LSL #3]

    (157) 0x429654 FSUB	Z0.D, P7/M, Z0.D, Z3.D

    (157) 0x429658 FADD	Z0.D, P7/M, Z0.D, Z2.D

    (157) 0x42965c FSUB	Z0.D, P7/M, Z0.D, Z1.D

    (157) 0x429660 FADD	Z31.D, P7/M, Z31.D, Z0.D

    (157) 0x429664 ST1D	{Z31.D}, P7, [X4, X0,LSL #3]

    (157) 0x429668 LD1D	{Z29.D}, P7/Z, [X2, X0,LSL #3]

    (157) 0x42966c LD1D	{Z30.D}, P7/Z, [X5, X0,LSL #3]

    (157) 0x429670 FSUB	Z29.D, P7/M, Z29.D, Z30.D

    (157) 0x429674 FSUB	Z31.D, P7/M, Z31.D, Z29.D

    (157) 0x429678 ST1D	{Z31.D}, P7, [X3, X0,LSL #3]

    (157) 0x42967c ADD	X0, X0, X10

    (157) 0x429680 WHILELO	P7.D, X0, X1

    (157) 0x429684 B.NE	429640

  (158) 0x429688 ORR	X30, XZR, X18

  (158) 0x42968c CMP	W19, W18

  (158) 0x429690 B.LE	4296cc

  (158) 0x429694 SUB	W1, W16, W17

  (158) 0x429698 ORR	W0, WZR, W21

  (158) 0x42969c ORR	W2, WZR, W17

  (158) 0x4296a0 CMP	W1, W0

  (158) 0x4296a4 CSEL	X1, X1, X0, #9

  (158) 0x4296a8 ADD	W17, W2, W1

  (158) 0x4296ac ORR	W9, WZR, W20

  (158) 0x4296b0 CMP	W2, W17

  (158) 0x4296b4 B.CC	4295c0

(159) 0x4296b8 ADD	X18, X30, #1

(159) 0x4296bc ORR	W17, WZR, W2

(159) 0x4296c0 ORR	X30, XZR, X18

(159) 0x4296c4 CMP	W19, W18

(159) 0x4296c8 B.GT	429694

0x4296cc LDP	X21, X22, [SP, #32]

0x4296d0 LDP	X19, X20, [SP, #16]

0x4296d4 LDP	X23, X24, [SP, #48]

0x4296d8 LDP	X25, X26, [SP, #64]

0x4296dc LDP	X29, X30, [SP], #80

0x4296e0 RET

0x4296e4 ADD	W1, W1, #1

0x4296e8 MOVZ	W0, #0

0x4296ec B	429574

Coverage (%)	Name	Source Location	Module
►98.44+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.56+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:80	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:44-48
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.25 cycles (3.03x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:45
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:45

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	57
nb uops	57
loop length	228
used w registers	14
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50
cycles	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.13
Dispatch	8.75
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	27%
load	40%
store	50%
mul	12%
add-sub	13%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 429500

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W20, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #44]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4296d0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4296cc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
MUL W26, W26, W21	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 4296e4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W16, W1, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 4296cc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W2, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X11, [X23, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X15, X14, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X13, X12, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W9, W0, W21, W2	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W0, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X30, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W9, W9, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W22, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X1, X1, X0, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W17, W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 4296b8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 429574 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:44-48
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 27% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.25 cycles (3.03x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:45
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:45

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	57
nb uops	57
loop length	228
used w registers	14
used x registers	19
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50
cycles	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.13
Dispatch	8.75
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	27%
load	40%
store	50%
mul	12%
add-sub	13%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 429500

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W25, W19, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W20, [X0, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #44]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W19, W19, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4296d0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W0, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 4296cc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
MUL W26, W26, W21	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W2, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
UDIV W1, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W1, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W2, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 4296e4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W2, W1, W2, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W16, W1, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 4296cc <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W2, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
LDR X11, [X23, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X15, X14, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X13, X12, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W9, W0, W21, W2	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W0, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X30, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W9, W9, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W22, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X1, X1, X0, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W17, W2, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W2, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 4296b8 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W1, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 429574 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.35	1.84
▼Loop 159 - advec_cell.cpp:46-48 - exec–	0.00	0.00
▼Loop 158 - advec_cell.cpp:46-48 - exec–	0.00	0.01
○Loop 157 - advec_cell.cpp:47-48 - exec	1.35	1.79

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code