OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:117-125 [...]	Coverage (incl. loops): 3.70% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 117 - 125

--------------------------------------------------------------------------------

117: #pragma omp parallel for simd collapse(2)

118:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

119:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

120:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

121:         double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0);

122:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s;

123:         double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0);

124:         density1(i, j) = post_mass_s / advec_vol_s;

125:         energy1(i, j) = post_ener_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x4298a0 STP	X29, X30, [SP, #944]!

0x4298a4 ADD	X29, SP, #0

0x4298a8 STP	X19, X20, [SP, #16]

0x4298ac STP	X23, X24, [SP, #48]

0x4298b0 ORR	X23, XZR, X0

0x4298b4 STP	X25, X26, [SP, #64]

0x4298b8 LDP	W25, W19, [X0, #56]

0x4298bc LDR	W20, [X0, #48]

0x4298c0 LDR	W0, [X0, #52]

0x4298c4 ADD	W25, W25, #1

0x4298c8 ADD	W19, W19, #2

0x4298cc CMP	W25, W19

0x4298d0 B.GE	429a8c

0x4298d4 ADD	W20, W20, #1

0x4298d8 STP	X21, X22, [SP, #32]

0x4298dc ADD	W22, W0, #2

0x4298e0 SUB	W26, W19, W25

0x4298e4 CMP	W20, W22

0x4298e8 B.GE	429a88

0x4298ec SUB	W21, W22, W20

0x4298f0 BL	410670

0x4298f4 MUL	W26, W26, W21

0x4298f8 ORR	W24, WZR, W0

0x4298fc BL	410550

0x429900 ORR	W1, WZR, W0

0x429904 UDIV	W3, W26, W24

0x429908 MSUB	W0, W3, W24, W26

0x42990c CMP	W1, W0

0x429910 B.CC	429aa0

0x429914 MADD	W1, W3, W1, W0

0x429918 ADD	W16, W3, W1

0x42991c CMP	W1, W16

0x429920 B.CS	429a88

0x429924 UDIV	W0, W1, W21

0x429928 LDP	X15, X14, [X23]

0x42992c CNTD	X9, ALL

0x429930 LDP	X13, X12, [X23, #16]

0x429934 LDP	X11, X10, [X23, #32]

0x429938 MSUB	W6, W0, W21, W1

0x42993c ADD	W0, W0, W25

0x429940 SBFM	X8, X0, #0, #31

0x429944 ADD	W6, W6, W20

0x429948 SUB	W0, W22, W6

0x42994c CMP	W3, W0

0x429950 CSEL	X3, X3, X0, #9

0x429954 ADD	W17, W1, W3

0x429958 CMP	W1, W17

0x42995c B.CS	429a78

  (164) 0x429960 LDR	X4, [X12]

  (164) 0x429964 SBFM	X6, X6, #0, #31

  (164) 0x429968 MOVZ	X0, #0

  (164) 0x42996c WHILELO	P7.D, XZR, X3

  (164) 0x429970 LDR	X7, [X10]

  (164) 0x429974 LDR	X5, [X11]

  (164) 0x429978 MADD	X4, X8, X4, X6

  (164) 0x42997c LDR	X30, [X13]

  (164) 0x429980 MADD	X7, X8, X7, X6

  (164) 0x429984 LDR	X1, [X14]

  (164) 0x429988 MADD	X5, X8, X5, X6

  (164) 0x42998c LDR	X2, [X15]

  (164) 0x429990 MADD	X30, X8, X30, X6

  (164) 0x429994 LDR	X23, [X12, #16]

  (164) 0x429998 MADD	X1, X8, X1, X6

  (164) 0x42999c LDR	X18, [X13, #16]

  (164) 0x4299a0 MADD	X2, X8, X2, X6

  (164) 0x4299a4 LDR	X24, [X10, #16]

  (164) 0x4299a8 ADD	X6, X23, X4,LSL #3

  (164) 0x4299ac LDR	X23, [X15, #16]

  (164) 0x4299b0 ADD	X22, X18, X30,LSL #3

  (164) 0x4299b4 ORR	X4, XZR, X6

  (164) 0x4299b8 ADD	X6, X6, #8

  (164) 0x4299bc ADD	X18, X24, X7,LSL #3

  (164) 0x4299c0 ORR	X30, XZR, X22

  (164) 0x4299c4 ADD	X22, X22, #8

  (164) 0x4299c8 ADD	X2, X23, X2,LSL #3

  (164) 0x4299cc LDR	X23, [X11, #16]

  (164) 0x4299d0 ORR	X7, XZR, X18

  (164) 0x4299d4 ADD	X18, X18, #8

  (164) 0x4299d8 ADD	X5, X23, X5,LSL #3

  (164) 0x4299dc LDR	X23, [X14, #16]

  (164) 0x4299e0 ADD	X1, X23, X1,LSL #3

    (163) 0x4299e4 LD1D	{Z30.D}, P7/Z, [X5, X0,LSL #3]

    (163) 0x4299e8 LD1D	{Z31.D}, P7/Z, [X2, X0,LSL #3]

    (163) 0x4299ec LD1D	{Z0.D}, P7/Z, [X4, X0,LSL #3]

    (163) 0x4299f0 LD1D	{Z29.D}, P7/Z, [X6, X0,LSL #3]

    (163) 0x4299f4 LD1D	{Z5.D}, P7/Z, [X30, X0,LSL #3]

    (163) 0x4299f8 LD1D	{Z3.D}, P7/Z, [X1, X0,LSL #3]

    (163) 0x4299fc LD1D	{Z2.D}, P7/Z, [X7, X0,LSL #3]

    (163) 0x429a00 LD1D	{Z1.D}, P7/Z, [X18, X0,LSL #3]

    (163) 0x429a04 LD1D	{Z4.D}, P7/Z, [X22, X0,LSL #3]

    (163) 0x429a08 FMUL	Z31.D, P7/M, Z31.D, Z30.D

    (163) 0x429a0c FADD	Z30.D, P7/M, Z30.D, Z0.D

    (163) 0x429a10 MOVPRFX	Z28, Z31

    (163) 0x429a14 FADD	Z28.D, P7/M, Z28.D, Z5.D

    (163) 0x429a18 FSUB	Z30.D, P7/M, Z30.D, Z29.D

    (163) 0x429a1c FSUB	Z28.D, P7/M, Z28.D, Z4.D

    (163) 0x429a20 FMUL	Z31.D, P7/M, Z31.D, Z3.D

    (163) 0x429a24 FADD	Z31.D, P7/M, Z31.D, Z2.D

    (163) 0x429a28 FSUB	Z31.D, P7/M, Z31.D, Z1.D

    (163) 0x429a2c FDIV	Z31.D, P7/M, Z31.D, Z28.D

    (163) 0x429a30 FDIV	Z28.D, P7/M, Z28.D, Z30.D

    (163) 0x429a34 ST1D	{Z28.D}, P7, [X2, X0,LSL #3]

    (163) 0x429a38 ST1D	{Z31.D}, P7, [X1, X0,LSL #3]

    (163) 0x429a3c ADD	X0, X0, X9

    (163) 0x429a40 WHILELO	P7.D, X0, X3

    (163) 0x429a44 B.NE	4299e4

  (164) 0x429a48 ADD	X8, X8, #1

  (164) 0x429a4c CMP	W19, W8

  (164) 0x429a50 B.LE	429a88

  (164) 0x429a54 SUB	W3, W16, W17

  (164) 0x429a58 ORR	W0, WZR, W21

  (164) 0x429a5c ORR	W1, WZR, W17

  (164) 0x429a60 CMP	W3, W0

  (164) 0x429a64 CSEL	X3, X3, X0, #9

  (164) 0x429a68 ADD	W17, W1, W3

  (164) 0x429a6c ORR	W6, WZR, W20

  (164) 0x429a70 CMP	W1, W17

  (164) 0x429a74 B.CC	429960

(165) 0x429a78 ADD	X8, X8, #1

(165) 0x429a7c ORR	W17, WZR, W1

(165) 0x429a80 CMP	W19, W8

(165) 0x429a84 B.GT	429a54

0x429a88 LDP	X21, X22, [SP, #32]

0x429a8c LDP	X19, X20, [SP, #16]

0x429a90 LDP	X23, X24, [SP, #48]

0x429a94 LDP	X25, X26, [SP, #64]

0x429a98 LDP	X29, X30, [SP], #80

0x429a9c RET

0x429aa0 ADD	W3, W3, #1

0x429aa4 MOVZ	W0, #0

0x429aa8 B	429914

Coverage (%)	Name	Module
►98.43+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.25 cycles (3.03x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	57
nb uops	57
loop length	228
used w registers	14
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50
cycles	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.13
Dispatch	8.75
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	43%
store	50%
mul	12%
add-sub	13%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4298a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W25, W19, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W20, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 429a8c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 429a88 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
MUL W26, W26, W21	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 429aa0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W1, W3, W1, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W16, W3, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W1, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 429a88 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W1, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X15, X14, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X13, X12, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X10, [X23, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W6, W0, W21, W1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W0, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X8, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W6, W6, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W22, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X3, X3, X0, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W17, W1, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W1, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 429a78 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 429914 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.25 cycles (3.03x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	57
nb uops	57
loop length	228
used w registers	14
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50
cycles	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.13
Dispatch	8.75
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	43%
store	50%
mul	12%
add-sub	13%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4298a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W25, W19, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W20, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 429a8c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x1ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 429a88 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
MUL W26, W26, W21	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 429aa0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W1, W3, W1, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W16, W3, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W1, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 429a88 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W1, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X15, X14, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X13, X12, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X11, X10, [X23, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W6, W0, W21, W1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W0, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X8, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W6, W6, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W22, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X3, X3, X0, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W17, W1, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W1, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 429a78 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x1d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 429914 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.70	5.05
▼Loop 165 - advec_cell.cpp:119-125 - exec–	0.00	0.00
▼Loop 164 - advec_cell.cpp:119-125 - exec–	0.00	0.01
○Loop 163 - advec_cell.cpp:120-125 - exec	3.70	4.91

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code