OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:208-216 [...]	Coverage (incl. loops): 4.07% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 208 - 216

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208: #pragma omp parallel for simd collapse(2)

209:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

210:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

211:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

212:         double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1);

213:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s;

214:         double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1);

215:         density1(i, j) = post_mass_s / advec_vol_s;

216:         energy1(i, j) = post_ener_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x429e60 STP	X29, X30, [SP, #944]!

0x429e64 ADD	X29, SP, #0

0x429e68 STP	X19, X20, [SP, #16]

0x429e6c STP	X23, X24, [SP, #48]

0x429e70 ORR	X23, XZR, X0

0x429e74 STP	X25, X26, [SP, #64]

0x429e78 LDP	W25, W19, [X0, #56]

0x429e7c LDR	W20, [X0, #48]

0x429e80 LDR	W0, [X0, #52]

0x429e84 ADD	W25, W25, #1

0x429e88 ADD	W19, W19, #2

0x429e8c CMP	W25, W19

0x429e90 B.GE	42a068

0x429e94 ADD	W20, W20, #1

0x429e98 STP	X21, X22, [SP, #32]

0x429e9c ADD	W22, W0, #2

0x429ea0 SUB	W26, W19, W25

0x429ea4 CMP	W20, W22

0x429ea8 B.GE	42a064

0x429eac SUB	W21, W22, W20

0x429eb0 BL	410670

0x429eb4 MUL	W26, W26, W21

0x429eb8 ORR	W24, WZR, W0

0x429ebc BL	410550

0x429ec0 ORR	W1, WZR, W0

0x429ec4 UDIV	W3, W26, W24

0x429ec8 MSUB	W0, W3, W24, W26

0x429ecc CMP	W1, W0

0x429ed0 B.CC	42a07c

0x429ed4 MADD	W1, W3, W1, W0

0x429ed8 ADD	W17, W3, W1

0x429edc CMP	W1, W17

0x429ee0 B.CS	42a064

0x429ee4 UDIV	W0, W1, W21

0x429ee8 LDP	X16, X15, [X23]

0x429eec CNTD	X10, ALL

0x429ef0 LDP	X14, X13, [X23, #16]

0x429ef4 LDP	X12, X11, [X23, #32]

0x429ef8 MSUB	W5, W0, W21, W1

0x429efc ADD	W0, W0, W25

0x429f00 SBFM	X9, X0, #0, #31

0x429f04 ADD	W5, W5, W20

0x429f08 SUB	W0, W22, W5

0x429f0c CMP	W3, W0

0x429f10 CSEL	X3, X3, X0, #9

0x429f14 ADD	W18, W1, W3

0x429f18 CMP	W1, W18

0x429f1c B.CS	42a054

  (173) 0x429f20 LDR	X7, [X11]

  (173) 0x429f24 SBFM	X5, X5, #0, #31

  (173) 0x429f28 MOVZ	X0, #0

  (173) 0x429f2c WHILELO	P7.D, XZR, X3

  (173) 0x429f30 LDR	X4, [X13]

  (173) 0x429f34 LDR	X30, [X14]

  (173) 0x429f38 MUL	X8, X9, X7

  (173) 0x429f3c LDR	X23, [X12]

  (173) 0x429f40 MUL	X6, X9, X4

  (173) 0x429f44 LDR	X1, [X15]

  (173) 0x429f48 ADD	X7, X7, X8

  (173) 0x429f4c ADD	X8, X8, X5

  (173) 0x429f50 MUL	X22, X9, X30

  (173) 0x429f54 ADD	X7, X7, X5

  (173) 0x429f58 LDR	X2, [X16]

  (173) 0x429f5c ADD	X4, X4, X6

  (173) 0x429f60 ADD	X6, X6, X5

  (173) 0x429f64 MADD	X23, X9, X23, X5

  (173) 0x429f68 ADD	X4, X4, X5

  (173) 0x429f6c ADD	X30, X30, X22

  (173) 0x429f70 LDR	X24, [X13, #16]

  (173) 0x429f74 ADD	X22, X22, X5

  (173) 0x429f78 MADD	X1, X9, X1, X5

  (173) 0x429f7c ADD	X30, X30, X5

  (173) 0x429f80 LDR	X25, [X11, #16]

  (173) 0x429f84 MADD	X2, X9, X2, X5

  (173) 0x429f88 LDR	X5, [X12, #16]

  (173) 0x429f8c ADD	X4, X24, X4,LSL #3

  (173) 0x429f90 LDR	X26, [X14, #16]

  (173) 0x429f94 ADD	X6, X24, X6,LSL #3

  (173) 0x429f98 ADD	X7, X25, X7,LSL #3

  (173) 0x429f9c LDR	X24, [X16, #16]

  (173) 0x429fa0 ADD	X8, X25, X8,LSL #3

  (173) 0x429fa4 ADD	X5, X5, X23,LSL #3

  (173) 0x429fa8 LDR	X23, [X15, #16]

  (173) 0x429fac ADD	X30, X26, X30,LSL #3

  (173) 0x429fb0 ADD	X22, X26, X22,LSL #3

  (173) 0x429fb4 ADD	X2, X24, X2,LSL #3

  (173) 0x429fb8 ADD	X1, X23, X1,LSL #3

  (173) 0x429fbc HINT	#0

    (172) 0x429fc0 LD1D	{Z30.D}, P7/Z, [X5, X0,LSL #3]

    (172) 0x429fc4 LD1D	{Z31.D}, P7/Z, [X2, X0,LSL #3]

    (172) 0x429fc8 LD1D	{Z0.D}, P7/Z, [X6, X0,LSL #3]

    (172) 0x429fcc LD1D	{Z29.D}, P7/Z, [X4, X0,LSL #3]

    (172) 0x429fd0 LD1D	{Z5.D}, P7/Z, [X22, X0,LSL #3]

    (172) 0x429fd4 LD1D	{Z3.D}, P7/Z, [X1, X0,LSL #3]

    (172) 0x429fd8 LD1D	{Z2.D}, P7/Z, [X8, X0,LSL #3]

    (172) 0x429fdc LD1D	{Z1.D}, P7/Z, [X7, X0,LSL #3]

    (172) 0x429fe0 LD1D	{Z4.D}, P7/Z, [X30, X0,LSL #3]

    (172) 0x429fe4 FMUL	Z31.D, P7/M, Z31.D, Z30.D

    (172) 0x429fe8 FADD	Z30.D, P7/M, Z30.D, Z0.D

    (172) 0x429fec MOVPRFX	Z28, Z31

    (172) 0x429ff0 FADD	Z28.D, P7/M, Z28.D, Z5.D

    (172) 0x429ff4 FSUB	Z30.D, P7/M, Z30.D, Z29.D

    (172) 0x429ff8 FSUB	Z28.D, P7/M, Z28.D, Z4.D

    (172) 0x429ffc FMUL	Z31.D, P7/M, Z31.D, Z3.D

    (172) 0x42a000 FADD	Z31.D, P7/M, Z31.D, Z2.D

    (172) 0x42a004 FSUB	Z31.D, P7/M, Z31.D, Z1.D

    (172) 0x42a008 FDIV	Z31.D, P7/M, Z31.D, Z28.D

    (172) 0x42a00c FDIV	Z28.D, P7/M, Z28.D, Z30.D

    (172) 0x42a010 ST1D	{Z28.D}, P7, [X2, X0,LSL #3]

    (172) 0x42a014 ST1D	{Z31.D}, P7, [X1, X0,LSL #3]

    (172) 0x42a018 ADD	X0, X0, X10

    (172) 0x42a01c WHILELO	P7.D, X0, X3

    (172) 0x42a020 B.NE	429fc0

  (173) 0x42a024 ADD	X9, X9, #1

  (173) 0x42a028 CMP	W19, W9

  (173) 0x42a02c B.LE	42a064

  (173) 0x42a030 SUB	W3, W17, W18

  (173) 0x42a034 ORR	W0, WZR, W21

  (173) 0x42a038 ORR	W1, WZR, W18

  (173) 0x42a03c CMP	W3, W0

  (173) 0x42a040 CSEL	X3, X3, X0, #9

  (173) 0x42a044 ADD	W18, W1, W3

  (173) 0x42a048 ORR	W5, WZR, W20

  (173) 0x42a04c CMP	W1, W18

  (173) 0x42a050 B.CC	429f20

(174) 0x42a054 ADD	X9, X9, #1

(174) 0x42a058 ORR	W18, WZR, W1

(174) 0x42a05c CMP	W19, W9

(174) 0x42a060 B.GT	42a030

0x42a064 LDP	X21, X22, [SP, #32]

0x42a068 LDP	X19, X20, [SP, #16]

0x42a06c LDP	X23, X24, [SP, #48]

0x42a070 LDP	X25, X26, [SP, #64]

0x42a074 LDP	X29, X30, [SP], #80

0x42a078 RET

0x42a07c ADD	W3, W3, #1

0x42a080 MOVZ	W0, #0

0x42a084 B	429ed4

Coverage (%)	Name	Module
►98.43+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.25 cycles (3.03x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	57
nb uops	57
loop length	228
used w registers	14
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50
cycles	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.13
Dispatch	8.75
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	43%
store	50%
mul	12%
add-sub	13%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 429e60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W25, W19, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W20, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42a068 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42a064 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
MUL W26, W26, W21	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 42a07c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W1, W3, W1, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W17, W3, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W1, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42a064 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W1, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X16, X15, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X14, X13, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X11, [X23, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W5, W0, W21, W1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W0, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X9, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W5, W5, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W22, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X3, X3, X0, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W18, W1, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W1, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42a054 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 429ed4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 8.25 cycles (3.03x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 6 bytes.

General properties

nb instructions	57
nb uops	57
loop length	228
used w registers	14
used x registers	21
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	7.13 cycles
front end	7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50
cycles	4.50	4.50	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	5.50	5.17	5.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	7.13
Dispatch	8.75
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	28%
load	43%
store	50%
mul	12%
add-sub	13%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 429e60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X23, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W25, W19, [X0, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W20, [X0, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W25, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W19, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W25, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42a068 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x208>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W20, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W22, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W26, W19, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W20, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42a064 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W21, W22, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410670 <@plt_start@+0x650>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
MUL W26, W26, W21	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (12.5%)
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410550 <@plt_start@+0x530>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A
ORR W1, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
UDIV W3, W26, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
MSUB W0, W3, W24, W26	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 42a07c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W1, W3, W1, W0	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W17, W3, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W1, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42a064 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x204>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W0, W1, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	5-12.50	N/A
LDP X16, X15, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CNTD X10, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDP X14, X13, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X12, X11, [X23, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
MSUB W5, W0, W21, W1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W0, W0, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
SBFM X9, X0, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ADD W5, W5, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W0, W22, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL X3, X3, X0, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD W18, W1, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W1, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42a054 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x1f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #80	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
B 429ed4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x74>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	4.07	5.56
▼Loop 174 - advec_cell.cpp:210-216 - exec–	0.00	0.00
▼Loop 173 - advec_cell.cpp:210-216 - exec–	0.01	0.02
○Loop 172 - advec_cell.cpp:211-216 - exec	4.06	5.39

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code