OV - exec - Loop 209

	Loop Id: 209	Module: exec	Source: context.h:69-69 [...]	Coverage: 3.66%

0x42bdc0 LD1D	{Z21.D}, P5/Z, [X7, X0,LSL #3]    [3]

0x42bdc4 MOVPRFX	Z19, Z25

0x42bdc8 ADD	Z19.S, Z19.S, #1

0x42bdcc FCMLT	P15.D, P3/Z, Z21.D, #0.0000000

0x42bdd0 SUNPKLO	Z23.D, Z25

0x42bdd4 SUNPKLO	Z18.D, Z19

0x42bdd8 SEL	Z7.D, P15, Z18.D, Z23.D

0x42bddc SEL	Z18.D, P15, Z23.D, Z18.D

0x42bde0 LD1D	{Z15.D}, P5/Z, [X1, Z7.D,LSL #3]    [7]

0x42bde4 LD1D	{Z20.D}, P4/Z, [X9, X0,LSL #3]    [5]

0x42bde8 LD1D	{Z3.D}, P5/Z, [X4, Z7.D,LSL #3]    [9]

0x42bdec FCMLT	P14.D, P3/Z, Z20.D, #0.0000000

0x42bdf0 LD1D	{Z7.D}, P5/Z, [X1, Z18.D,LSL #3]    [7]

0x42bdf4 UZP1	P7.S, P15.S, P14.S

0x42bdf8 FSUB	Z7.D, P5/M, Z7.D, Z15.D

0x42bdfc SUNPKHI	Z22.D, Z25

0x42be00 SUNPKHI	Z17.D, Z19

0x42be04 MOVPRFX	Z16, Z25

0x42be08 SUB	Z16.S, Z16.S, #1

0x42be0c SEL	Z6.D, P14, Z17.D, Z22.D

0x42be10 MOVPRFX	Z16.S, P7/M, Z25.S

0x42be14 ADD	Z16.S, P7/M, Z16.S, Z31.S

0x42be18 SEL	Z17.D, P14, Z22.D, Z17.D

0x42be1c SUNPKLO	Z13.D, Z16

0x42be20 SUNPKHI	Z16.D, Z16

0x42be24 LD1D	{Z12.D}, P5/Z, [X1, Z13.D,LSL #3]    [7]

0x42be28 MOVPRFX	Z23, Z15

0x42be2c FSUB	Z23.D, P5/M, Z23.D, Z12.D

0x42be30 MOVPRFX	Z18, Z23

0x42be34 FMUL	Z18.D, P5/M, Z18.D, Z7.D

0x42be38 LD1D	{Z14.D}, P4/Z, [X1, Z6.D,LSL #3]    [7]

0x42be3c FCMGT	P6.D, P5/Z, Z18.D, #0.0000000

0x42be40 LD1D	{Z24.D}, P4/Z, [X1, Z16.D,LSL #3]    [7]

0x42be44 LD1D	{Z2.D}, P4/Z, [X4, Z6.D,LSL #3]    [9]

0x42be48 MOVPRFX	Z22, Z14

0x42be4c FSUB	Z22.D, P4/M, Z22.D, Z24.D

0x42be50 LD1D	{Z6.D}, P4/Z, [X1, Z17.D,LSL #3]    [7]

0x42be54 MOVPRFX	Z5, Z21

0x42be58 FABS	Z5.D, P3/M, Z21.D

0x42be5c FSUB	Z6.D, P4/M, Z6.D, Z14.D

0x42be60 FDIV	Z5.D, P5/M, Z5.D, Z3.D

0x42be64 MOVPRFX	Z17, Z22

0x42be68 FMUL	Z17.D, P4/M, Z17.D, Z6.D

0x42be6c EOR	P7.B, P3/Z, P7.B, P3.B

0x42be70 MOVPRFX	Z18, Z5

0x42be74 FADD	Z18.D, P6/M, Z18.D, #0.0000000

0x42be78 MOVPRFX	Z16, Z27

0x42be7c FSUB	Z16.D, P6/M, Z16.D, Z5.D

0x42be80 MOVPRFX	Z19.S, P7/M, Z25.S

0x42be84 ADD	Z19.S, P7/M, Z19.S, Z30.S

0x42be88 FABS	Z23.D, P3/M, Z23.D

0x42be8c FCMGT	P7.D, P4/Z, Z17.D, #0.0000000

0x42be90 FCMLE	P14.D, P6/Z, Z7.D, #0.0000000

0x42be94 MOVPRFX	Z3, Z7

0x42be98 FABS	Z3.D, P3/M, Z7.D

0x42be9c MOVPRFX	Z4, Z20

0x42bea0 FABS	Z4.D, P3/M, Z20.D

0x42bea4 MOVPRFX	Z7, Z3

0x42bea8 FMUL	Z7.D, P6/M, Z7.D, Z16.D

0x42beac FDIV	Z4.D, P4/M, Z4.D, Z2.D

0x42beb0 MOVPRFX	Z16, Z23

0x42beb4 FMUL	Z16.D, P6/M, Z16.D, Z18.D

0x42beb8 MOVPRFX	Z24, Z27

0x42bebc FSUB	Z24.D, P7/M, Z24.D, Z4.D

0x42bec0 SUNPKLO	Z18.D, Z19

0x42bec4 MOVPRFX	Z17, Z4

0x42bec8 FADD	Z17.D, P7/M, Z17.D, #0.0000000

0x42becc LD1D	{Z1.D}, P5/Z, [X8, X0,LSL #3]    [4]

0x42bed0 LD1D	{Z0.D}, P4/Z, [X10, X0,LSL #3]    [6]

0x42bed4 FABS	Z22.D, P3/M, Z22.D

0x42bed8 FCMLE	P15.D, P7/Z, Z6.D, #0.0000000

0x42bedc MOVPRFX	Z2, Z6

0x42bee0 FABS	Z2.D, P3/M, Z6.D

0x42bee4 FDIV	Z7.D, P6/M, Z7.D, Z1.D

0x42bee8 MOVPRFX	Z6, Z2

0x42beec FMUL	Z6.D, P7/M, Z6.D, Z24.D

0x42bef0 SUNPKHI	Z19.D, Z19

0x42bef4 MOVPRFX	Z24, Z22

0x42bef8 FMUL	Z24.D, P7/M, Z24.D, Z17.D

0x42befc FDIV	Z6.D, P7/M, Z6.D, Z0.D

0x42bf00 LD1D	{Z17.D}, P6/Z, [X5, Z18.D,LSL #3]    [1]

0x42bf04 LD1D	{Z18.D}, P7/Z, [X5, Z19.D,LSL #3]    [1]

0x42bf08 FDIV	Z16.D, P6/M, Z16.D, Z17.D

0x42bf0c FDIV	Z24.D, P7/M, Z24.D, Z18.D

0x42bf10 FADD	Z7.D, P6/M, Z7.D, Z16.D

0x42bf14 FADD	Z6.D, P7/M, Z6.D, Z24.D

0x42bf18 FMUL	Z1.D, P6/M, Z1.D, Z7.D

0x42bf1c FMUL	Z0.D, P7/M, Z0.D, Z6.D

0x42bf20 SEL	Z7.D, P5, Z5.D, Z29.D

0x42bf24 SEL	Z6.D, P4, Z4.D, Z29.D

0x42bf28 FSUBR	Z7.D, P5/M, Z7.D, #0.0000000

0x42bf2c FSUBR	Z6.D, P4/M, Z6.D, #0.0000000

0x42bf30 EOR	P14.B, P6/Z, P14.B, P6.B

0x42bf34 EOR	P15.B, P7/Z, P15.B, P7.B

0x42bf38 MOVPRFX	Z13, Z28

0x42bf3c FCPY	Z13.D, P14/M, #1.0000000

0x42bf40 FDIV	Z1.D, P6/M, Z1.D, Z26.D

0x42bf44 FDIV	Z0.D, P7/M, Z0.D, Z26.D

0x42bf48 FMINNM	Z1.D, P3/M, Z1.D, Z23.D

0x42bf4c FMINNM	Z0.D, P3/M, Z0.D, Z22.D

0x42bf50 FMINNM	Z1.D, P3/M, Z1.D, Z3.D

0x42bf54 FMINNM	Z0.D, P3/M, Z0.D, Z2.D

0x42bf58 MOVPRFX	Z1.D, P6/Z, Z1.D

0x42bf5c FMUL	Z1.D, P6/M, Z1.D, Z13.D

0x42bf60 MOVPRFX	Z12, Z28

0x42bf64 FCPY	Z12.D, P15/M, #1.0000000

0x42bf68 FMLA	Z15.D, P5/M, Z1.D, Z7.D

0x42bf6c MOVPRFX	Z0.D, P7/Z, Z0.D

0x42bf70 FMUL	Z0.D, P7/M, Z0.D, Z12.D

0x42bf74 FMUL	Z21.D, P5/M, Z21.D, Z15.D

0x42bf78 FMLA	Z14.D, P4/M, Z0.D, Z6.D

0x42bf7c FMUL	Z20.D, P4/M, Z20.D, Z14.D

0x42bf80 ST1D	{Z21.D}, P5, [X3, X0,LSL #3]    [8]

0x42bf84 ST1D	{Z20.D}, P4, [X6, X0,LSL #3]    [2]

0x42bf88 ADD	X0, X0, X12

0x42bf8c WHILELO	P4.D, X0, X22

0x42bf90 INCW	Z25.S, ALL

0x42bf94 WHILELO	P5.D, X0, X2

0x42bf98 B.NE	42bdc0

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 114 - 139

--------------------------------------------------------------------------------

114:           if (node_flux(i, j) < 0.0) {

[...]

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

Coverage (%)	Name	Module
►98.41+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18 - 2.37
Bottlenecks	P6, P8,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source	context.h:69-69,advec_mom.cpp:114-114,advec_mom.cpp:120-139
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	55.94 - 112.68
CQA cycles if no scalar integer	55.94 - 112.68
CQA cycles if FP arith vectorized	55.94 - 112.68
CQA cycles if fully vectorized	55.94 - 112.68
Front-end cycles	14.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	6.00
P5 cycles	0.25
P6 cycles	47.50
P7 cycles	47.50
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	55.94 - 112.68
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	119.00
Nb uops	119.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.57 - 1.28
Nb FLOP add-sub	48.00
Nb FLOP mul	48.00
Nb FLOP fma	8.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.54 - 9.15
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	6.00
Stride indirect	3.00
Vectorization ratio all	73.04
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	48.33
Vector-efficiency ratio all	95.27
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	90.94

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18 - 2.37
Bottlenecks	P6, P8,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source	context.h:69-69,advec_mom.cpp:114-114,advec_mom.cpp:120-139
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	55.94 - 112.68
CQA cycles if no scalar integer	55.94 - 112.68
CQA cycles if FP arith vectorized	55.94 - 112.68
CQA cycles if fully vectorized	55.94 - 112.68
Front-end cycles	14.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	6.00
P5 cycles	0.25
P6 cycles	47.50
P7 cycles	47.50
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	55.94 - 112.68
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	119.00
Nb uops	119.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.57 - 1.28
Nb FLOP add-sub	48.00
Nb FLOP mul	48.00
Nb FLOP fma	8.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.54 - 9.15
Bytes prefetched	0.00
Bytes loaded	448.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	6.00
Stride indirect	3.00
Vectorization ratio all	73.04
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	48.33
Vector-efficiency ratio all	95.27
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	90.94

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:114,120-139

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

73% of VPU instructions are used in vector version (process two or more data elements in vector registers):

48% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 112.68 to 43.50 cycles (2.59x speedup).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 6 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
56: multiply (8 inside FMA instructions)
32: divide

The binary loop is loading 448 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	119
nb uops	119
loop length	476
used w registers	0
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	28
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.88 cycles
front end	14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	6.00	0.25	47.50	47.50	1.00	1.00	8.00	8.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	6.00	0.25	47.50	47.50	13.00	13.00	8.00	8.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	55.94-112.68
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	14.88
Dispatch	47.50
DIV/SQRT	55.94-112.68
Data deps.	2.00
Overall L1	55.94-112.68

Vectorization ratios

INT

all	53%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	73%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	48%

Vector efficiency ratios

INT

all	94%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	91%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	90%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 112.68 cycles. At this rate:

4% of peak load performance is reached (3.98 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42bdc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z21.D}, P5/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z19, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
ADD Z19.S, Z19.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLT P15.D, P3/Z, Z21.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SUNPKLO Z23.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKLO Z18.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SEL Z7.D, P15, Z18.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z18.D, P15, Z23.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z15.D}, P5/Z, [X1, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P4/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P5/Z, [X4, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMLT P14.D, P3/Z, Z20.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z7.D}, P5/Z, [X1, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
UZP1 P7.S, P15.S, P14.S	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (12.5%)
FSUB Z7.D, P5/M, Z7.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKHI Z22.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKHI Z17.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MOVPRFX Z16, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUB Z16.S, Z16.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z6.D, P14, Z17.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z16.S, P7/M, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD Z16.S, P7/M, Z16.S, Z31.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z17.D, P14, Z22.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKLO Z13.D, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKHI Z16.D, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
LD1D {Z12.D}, P5/Z, [X1, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z23, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z23.D, P5/M, Z23.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z18, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z18.D, P5/M, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z14.D}, P4/Z, [X1, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P6.D, P5/Z, Z18.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z24.D}, P4/Z, [X1, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P4/Z, [X4, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z22, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z22.D, P4/M, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z6.D}, P4/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z5, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z5.D, P3/M, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z6.D, P4/M, Z6.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z5.D, P5/M, Z5.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z17, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z17.D, P4/M, Z17.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
EOR P7.B, P3/Z, P7.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z18, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z18.D, P6/M, Z18.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z16, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z16.D, P6/M, Z16.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z19.S, P7/M, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD Z19.S, P7/M, Z19.S, Z30.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FABS Z23.D, P3/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P7.D, P4/Z, Z17.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMLE P14.D, P6/Z, Z7.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z3, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z3.D, P3/M, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z4, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z4.D, P3/M, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z7, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z7.D, P6/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z4.D, P4/M, Z4.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z16, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z16.D, P6/M, Z16.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z24, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z24.D, P7/M, Z24.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKLO Z18.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MOVPRFX Z17, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z17.D, P7/M, Z17.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z1.D}, P5/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z0.D}, P4/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FABS Z22.D, P3/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLE P15.D, P7/Z, Z6.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z2, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z2.D, P3/M, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z7.D, P6/M, Z7.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z6, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z6.D, P7/M, Z6.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
SUNPKHI Z19.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MOVPRFX Z24, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z24.D, P7/M, Z24.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z6.D, P7/M, Z6.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LD1D {Z17.D}, P6/Z, [X5, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X5, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIV Z16.D, P6/M, Z16.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z24.D, P7/M, Z24.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z7.D, P6/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z1.D, P6/M, Z1.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
SEL Z7.D, P5, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z6.D, P4, Z4.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z7.D, P5/M, Z7.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z6.D, P4/M, Z6.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
EOR P14.B, P6/Z, P14.B, P6.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
EOR P15.B, P7/Z, P15.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z13, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCPY Z13.D, P14/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
FDIV Z1.D, P6/M, Z1.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z0.D, P7/M, Z0.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMINNM Z1.D, P3/M, Z1.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P3/M, Z0.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z1.D, P3/M, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P3/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z1.D, P6/Z, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z1.D, P6/M, Z1.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z12, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCPY Z12.D, P15/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
FMLA Z15.D, P5/M, Z1.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z0.D, P7/Z, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z21.D, P5/M, Z21.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z14.D, P4/M, Z0.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z20.D, P4/M, Z20.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z21.D}, P5, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z20.D}, P4, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X0, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P4.D, X0, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
INCW Z25.S, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P5.D, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 42bdc0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.6]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:114,120-139

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

73% of VPU instructions are used in vector version (process two or more data elements in vector registers):

48% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 112.68 to 43.50 cycles (2.59x speedup).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 6 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
56: multiply (8 inside FMA instructions)
32: divide

The binary loop is loading 448 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	119
nb uops	119
loop length	476
used w registers	0
used x registers	13
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	28
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.88 cycles
front end	14.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	6.00	0.25	47.50	47.50	1.00	1.00	8.00	8.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	6.00	0.25	47.50	47.50	13.00	13.00	8.00	8.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	55.94-112.68
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	14.88
Dispatch	47.50
DIV/SQRT	55.94-112.68
Data deps.	2.00
Overall L1	55.94-112.68

Vectorization ratios

INT

all	53%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	73%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	48%

Vector efficiency ratios

INT

all	94%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	91%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	90%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 112.68 cycles. At this rate:

4% of peak load performance is reached (3.98 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42bdc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z21.D}, P5/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z19, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
ADD Z19.S, Z19.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLT P15.D, P3/Z, Z21.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SUNPKLO Z23.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKLO Z18.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SEL Z7.D, P15, Z18.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z18.D, P15, Z23.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z15.D}, P5/Z, [X1, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P4/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P5/Z, [X4, Z7.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMLT P14.D, P3/Z, Z20.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z7.D}, P5/Z, [X1, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
UZP1 P7.S, P15.S, P14.S	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (12.5%)
FSUB Z7.D, P5/M, Z7.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKHI Z22.D, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKHI Z17.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MOVPRFX Z16, Z25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUB Z16.S, Z16.S, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z6.D, P14, Z17.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z16.S, P7/M, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD Z16.S, P7/M, Z16.S, Z31.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z17.D, P14, Z22.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKLO Z13.D, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKHI Z16.D, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
LD1D {Z12.D}, P5/Z, [X1, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z23, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z23.D, P5/M, Z23.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z18, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z18.D, P5/M, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z14.D}, P4/Z, [X1, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P6.D, P5/Z, Z18.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z24.D}, P4/Z, [X1, Z16.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P4/Z, [X4, Z6.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z22, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z22.D, P4/M, Z22.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z6.D}, P4/Z, [X1, Z17.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z5, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z5.D, P3/M, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z6.D, P4/M, Z6.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z5.D, P5/M, Z5.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z17, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z17.D, P4/M, Z17.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
EOR P7.B, P3/Z, P7.B, P3.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z18, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z18.D, P6/M, Z18.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z16, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z16.D, P6/M, Z16.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z19.S, P7/M, Z25.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
ADD Z19.S, P7/M, Z19.S, Z30.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FABS Z23.D, P3/M, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMGT P7.D, P4/Z, Z17.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMLE P14.D, P6/Z, Z7.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z3, Z7	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z3.D, P3/M, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z4, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z4.D, P3/M, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z7, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z7.D, P6/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z4.D, P4/M, Z4.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z16, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z16.D, P6/M, Z16.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z24, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z24.D, P7/M, Z24.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKLO Z18.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MOVPRFX Z17, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z17.D, P7/M, Z17.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z1.D}, P5/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z0.D}, P4/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FABS Z22.D, P3/M, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLE P15.D, P7/Z, Z6.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z2, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z2.D, P3/M, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z7.D, P6/M, Z7.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z6, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z6.D, P7/M, Z6.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
SUNPKHI Z19.D, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MOVPRFX Z24, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z24.D, P7/M, Z24.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z6.D, P7/M, Z6.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LD1D {Z17.D}, P6/Z, [X5, Z18.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X5, Z19.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIV Z16.D, P6/M, Z16.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z24.D, P7/M, Z24.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z7.D, P6/M, Z7.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z1.D, P6/M, Z1.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
SEL Z7.D, P5, Z5.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z6.D, P4, Z4.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z7.D, P5/M, Z7.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z6.D, P4/M, Z6.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
EOR P14.B, P6/Z, P14.B, P6.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
EOR P15.B, P7/Z, P15.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
MOVPRFX Z13, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCPY Z13.D, P14/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
FDIV Z1.D, P6/M, Z1.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIV Z0.D, P7/M, Z0.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMINNM Z1.D, P3/M, Z1.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P3/M, Z0.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z1.D, P3/M, Z1.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P3/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z1.D, P6/Z, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z1.D, P6/M, Z1.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z12, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCPY Z12.D, P15/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
FMLA Z15.D, P5/M, Z1.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z0.D, P7/Z, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z21.D, P5/M, Z21.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z14.D, P4/M, Z0.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z20.D, P4/M, Z20.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z21.D}, P5, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z20.D}, P4, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X0, X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P4.D, X0, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
INCW Z25.S, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P5.D, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 42bdc0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code