OV - exec - Loop 212

	Loop Id: 212	Module: exec	Source: context.h:69-69 [...]	Coverage: 3.90%

0x42c180 LD1D	{Z26.D}, P6/Z, [X7, X0,LSL #3]    [3]

0x42c184 LD1D	{Z27.D}, P5/Z, [X9, X0,LSL #3]    [5]

0x42c188 SUNPKHI	Z29.D, Z21

0x42c18c FCMLT	P14.D, P4/Z, Z26.D, #0.0000000

0x42c190 FCMLT	P15.D, P4/Z, Z27.D, #0.0000000

0x42c194 SUNPKLO	Z15.D, Z21

0x42c198 UZP1	P13.S, P14.S, P15.S

0x42c19c SEL	Z31.S, P13, Z6.S, Z20.S

0x42c1a0 SUNPKLO	Z30.D, Z31

0x42c1a4 SUNPKHI	Z31.D, Z31

0x42c1a8 MAD	Z30.D, P4/M, Z25.D, Z15.D

0x42c1ac MAD	Z31.D, P4/M, Z25.D, Z29.D

0x42c1b0 LD1D	{Z5.D}, P6/Z, [X1, Z30.D,LSL #3]    [6]

0x42c1b4 LD1D	{Z2.D}, P5/Z, [X1, Z31.D,LSL #3]    [6]

0x42c1b8 SEL	Z14.D, P14, Z24.D, Z23.D

0x42c1bc SEL	Z31.D, P14, Z23.D, Z24.D

0x42c1c0 MOVPRFX	Z30, Z15

0x42c1c4 MLA	Z30.D, P4/M, Z25.D, Z31.D

0x42c1c8 MAD	Z31.D, P4/M, Z19.D, Z15.D

0x42c1cc LD1D	{Z28.D}, P6/Z, [X1, Z30.D,LSL #3]    [6]

0x42c1d0 MLA	Z15.D, P4/M, Z25.D, Z14.D

0x42c1d4 MOVPRFX	Z30, Z28

0x42c1d8 FSUB	Z30.D, P6/M, Z30.D, Z5.D

0x42c1dc LD1D	{Z14.D}, P6/Z, [X1, Z15.D,LSL #3]    [6]

0x42c1e0 MOVPRFX	Z4, Z30

0x42c1e4 FABS	Z4.D, P4/M, Z30.D

0x42c1e8 FSUB	Z14.D, P6/M, Z14.D, Z28.D

0x42c1ec FMUL	Z30.D, P6/M, Z30.D, Z14.D

0x42c1f0 LD1D	{Z13.D}, P6/Z, [X6, Z31.D,LSL #3]    [2]

0x42c1f4 FCMGT	P7.D, P6/Z, Z30.D, #0.0000000

0x42c1f8 SEL	Z3.S, P13, Z7.S, Z20.S

0x42c1fc SUNPKLO	Z30.D, Z3

0x42c200 MOVPRFX	Z31, Z26

0x42c204 FABS	Z31.D, P4/M, Z26.D

0x42c208 LD1D	{Z15.D}, P7/Z, [X4, Z30.D,LSL #3]    [8]

0x42c20c FDIV	Z31.D, P6/M, Z31.D, Z13.D

0x42c210 MOVPRFX	Z13, Z31

0x42c214 FADD	Z13.D, P7/M, Z13.D, #0.0000000

0x42c218 MOVPRFX	Z30, Z4

0x42c21c FMUL	Z30.D, P7/M, Z30.D, Z13.D

0x42c220 MOVPRFX	Z5, Z14

0x42c224 FABS	Z5.D, P4/M, Z14.D

0x42c228 MOVPRFX	Z1, Z30

0x42c22c FDIV	Z1.D, P7/M, Z1.D, Z15.D

0x42c230 MOVPRFX	Z13, Z22

0x42c234 FSUB	Z13.D, P7/M, Z13.D, Z31.D

0x42c238 SEL	Z15.D, P6, Z31.D, Z16.D

0x42c23c MOVPRFX	Z30, Z5

0x42c240 FMUL	Z30.D, P7/M, Z30.D, Z13.D

0x42c244 LD1RD	{Z31.D}, P4/Z, [X8]    [4]

0x42c248 FSUBR	Z15.D, P6/M, Z15.D, #0.0000000

0x42c24c FCMLE	P14.D, P7/Z, Z14.D, #0.0000000

0x42c250 FDIV	Z30.D, P7/M, Z30.D, Z31.D

0x42c254 EOR	P14.B, P7/Z, P14.B, P7.B

0x42c258 FADD	Z30.D, P7/M, Z30.D, Z1.D

0x42c25c MOVPRFX	Z14, Z17

0x42c260 FCPY	Z14.D, P14/M, #1.0000000

0x42c264 MOVPRFX	Z0, Z31

0x42c268 FMUL	Z0.D, P7/M, Z0.D, Z30.D

0x42c26c FDIV	Z0.D, P7/M, Z0.D, Z18.D

0x42c270 FMINNM	Z4.D, P4/M, Z4.D, Z0.D

0x42c274 FMINNM	Z5.D, P4/M, Z5.D, Z4.D

0x42c278 MOVPRFX	Z5.D, P7/Z, Z5.D

0x42c27c FMUL	Z5.D, P7/M, Z5.D, Z14.D

0x42c280 FMLA	Z28.D, P6/M, Z5.D, Z15.D

0x42c284 SEL	Z1.D, P15, Z23.D, Z24.D

0x42c288 FMUL	Z26.D, P6/M, Z26.D, Z28.D

0x42c28c MOVPRFX	Z13, Z29

0x42c290 MLA	Z13.D, P4/M, Z25.D, Z1.D

0x42c294 SEL	Z15.D, P15, Z24.D, Z23.D

0x42c298 LD1D	{Z30.D}, P5/Z, [X1, Z13.D,LSL #3]    [6]

0x42c29c MAD	Z15.D, P4/M, Z25.D, Z29.D

0x42c2a0 MOVPRFX	Z4, Z30

0x42c2a4 FSUB	Z4.D, P5/M, Z4.D, Z2.D

0x42c2a8 LD1D	{Z28.D}, P5/Z, [X1, Z15.D,LSL #3]    [6]

0x42c2ac MOVPRFX	Z5, Z4

0x42c2b0 FABS	Z5.D, P4/M, Z4.D

0x42c2b4 FSUB	Z28.D, P5/M, Z28.D, Z30.D

0x42c2b8 FMUL	Z4.D, P5/M, Z4.D, Z28.D

0x42c2bc MAD	Z1.D, P4/M, Z19.D, Z29.D

0x42c2c0 FCMGT	P7.D, P5/Z, Z4.D, #0.0000000

0x42c2c4 LD1D	{Z0.D}, P5/Z, [X6, Z1.D,LSL #3]    [2]

0x42c2c8 MOVPRFX	Z29, Z27

0x42c2cc FABS	Z29.D, P4/M, Z27.D

0x42c2d0 SUNPKHI	Z3.D, Z3

0x42c2d4 FDIV	Z29.D, P5/M, Z29.D, Z0.D

0x42c2d8 LD1D	{Z4.D}, P7/Z, [X4, Z3.D,LSL #3]    [8]

0x42c2dc SEL	Z2.D, P5, Z29.D, Z16.D

0x42c2e0 MOVPRFX	Z14, Z28

0x42c2e4 FABS	Z14.D, P4/M, Z28.D

0x42c2e8 MOVPRFX	Z15, Z29

0x42c2ec FADD	Z15.D, P7/M, Z15.D, #0.0000000

0x42c2f0 FCMLE	P15.D, P7/Z, Z28.D, #0.0000000

0x42c2f4 MOVPRFX	Z28, Z5

0x42c2f8 FMUL	Z28.D, P7/M, Z28.D, Z15.D

0x42c2fc FDIV	Z28.D, P7/M, Z28.D, Z4.D

0x42c300 MOVPRFX	Z4, Z22

0x42c304 FSUB	Z4.D, P7/M, Z4.D, Z29.D

0x42c308 MOVPRFX	Z29, Z14

0x42c30c FMUL	Z29.D, P7/M, Z29.D, Z4.D

0x42c310 FDIV	Z29.D, P7/M, Z29.D, Z31.D

0x42c314 FADD	Z29.D, P7/M, Z29.D, Z28.D

0x42c318 FMUL	Z31.D, P7/M, Z31.D, Z29.D

0x42c31c FDIV	Z31.D, P7/M, Z31.D, Z18.D

0x42c320 FSUBR	Z2.D, P5/M, Z2.D, #0.0000000

0x42c324 EOR	P15.B, P7/Z, P15.B, P7.B

0x42c328 FMINNM	Z5.D, P4/M, Z5.D, Z31.D

0x42c32c MOVPRFX	Z15, Z17

0x42c330 FCPY	Z15.D, P15/M, #1.0000000

0x42c334 MOVPRFX	Z31, Z14

0x42c338 FMINNM	Z31.D, P4/M, Z31.D, Z5.D

0x42c33c MOVPRFX	Z31.D, P7/Z, Z31.D

0x42c340 FMUL	Z31.D, P7/M, Z31.D, Z15.D

0x42c344 FMLA	Z30.D, P5/M, Z31.D, Z2.D

0x42c348 FMUL	Z27.D, P5/M, Z27.D, Z30.D

0x42c34c ST1D	{Z26.D}, P6, [X3, X0,LSL #3]    [7]

0x42c350 ST1D	{Z27.D}, P5, [X5, X0,LSL #3]    [1]

0x42c354 ADD	X0, X0, X11

0x42c358 WHILELO	P5.D, X0, X10

0x42c35c INCW	Z21.S, ALL

0x42c360 WHILELO	P6.D, X0, X2

0x42c364 B.NE	42c180

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 186 - 211

--------------------------------------------------------------------------------

186:           if (node_flux(i, j) < 0.0) {

[...]

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

Coverage (%)	Name	Module
►98.42+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12 - 2.25
Bottlenecks	P6, P8,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source	context.h:69-69,advec_mom.cpp:186-186,advec_mom.cpp:197-211
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	55.94 - 112.68
CQA cycles if no scalar integer	55.94 - 112.68
CQA cycles if FP arith vectorized	55.94 - 112.68
CQA cycles if fully vectorized	55.94 - 112.68
Front-end cycles	15.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	5.00
P5 cycles	0.25
P6 cycles	50.00
P7 cycles	50.00
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	7.50
P11 cycles	7.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	55.94 - 112.68
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	122.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.57 - 1.28
Nb FLOP add-sub	48.00
Nb FLOP mul	48.00
Nb FLOP fma	8.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.98 - 8.01
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	3.00
Vectorization ratio all	72.03
Vectorization ratio load	92.31
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	46.67
Vector-efficiency ratio all	95.50
Vector-efficiency ratio load	94.23
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	92.40

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12 - 2.25
Bottlenecks	P6, P8,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source	context.h:69-69,advec_mom.cpp:186-186,advec_mom.cpp:197-211
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	55.94 - 112.68
CQA cycles if no scalar integer	55.94 - 112.68
CQA cycles if FP arith vectorized	55.94 - 112.68
CQA cycles if fully vectorized	55.94 - 112.68
Front-end cycles	15.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	5.00
P5 cycles	0.25
P6 cycles	50.00
P7 cycles	50.00
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	7.50
P11 cycles	7.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	55.94 - 112.68
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	122.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.57 - 1.28
Nb FLOP add-sub	48.00
Nb FLOP mul	48.00
Nb FLOP fma	8.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.98 - 8.01
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	4.00
Stride indirect	3.00
Vectorization ratio all	72.03
Vectorization ratio load	92.31
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	46.67
Vector-efficiency ratio all	95.50
Vector-efficiency ratio load	94.23
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	92.40

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:186,197-211

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

72% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU loads are used in vector version.
46% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 112.68 to 46.00 cycles (2.45x speedup).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
56: multiply (8 inside FMA instructions)
32: divide

The binary loop is loading 384 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.32 FP operations per loaded or stored byte.

General properties

nb instructions	122
nb uops	122
loop length	488
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	27
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.25 cycles
front end	15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	5.00	0.25	50.00	50.00	1.00	1.00	7.50	7.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	5.00	0.25	50.00	50.00	13.00	13.00	7.50	7.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	55.94-112.68
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.25
Dispatch	50.00
DIV/SQRT	55.94-112.68
Data deps.	2.00
Overall L1	55.94-112.68

Vectorization ratios

INT

all	53%
load	92%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
other	28%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	72%
load	92%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	46%

Vector efficiency ratios

INT

all	94%
load	94%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
other	93%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

INT+FP

all	95%
load	94%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	92%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 112.68 cycles. At this rate:

3% of peak load performance is reached (3.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42c180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z26.D}, P6/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P5/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUNPKHI Z29.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCMLT P14.D, P4/Z, Z26.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P15.D, P4/Z, Z27.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SUNPKLO Z15.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
UZP1 P13.S, P14.S, P15.S	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (12.5%)
SEL Z31.S, P13, Z6.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKLO Z30.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKHI Z31.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MAD Z30.D, P4/M, Z25.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MAD Z31.D, P4/M, Z25.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z5.D}, P6/Z, [X1, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P5/Z, [X1, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SEL Z14.D, P14, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z31.D, P14, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MLA Z30.D, P4/M, Z25.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MAD Z31.D, P4/M, Z19.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X1, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MLA Z15.D, P4/M, Z25.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z30, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z30.D, P6/M, Z30.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z14.D}, P6/Z, [X1, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z4, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z4.D, P4/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z14.D, P6/M, Z14.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z30.D, P6/M, Z30.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z13.D}, P6/Z, [X6, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P7.D, P6/Z, Z30.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SEL Z3.S, P13, Z7.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKLO Z30.D, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MOVPRFX Z31, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z31.D, P4/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z15.D}, P7/Z, [X4, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIV Z31.D, P6/M, Z31.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z13, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z13.D, P7/M, Z13.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z30.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z5, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z5.D, P4/M, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z1, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z1.D, P7/M, Z1.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z13, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z13.D, P7/M, Z13.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z15.D, P6, Z31.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z30.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1RD {Z31.D}, P4/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FSUBR Z15.D, P6/M, Z15.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLE P14.D, P7/Z, Z14.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z30.D, P7/M, Z30.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
EOR P14.B, P7/Z, P14.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FADD Z30.D, P7/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z14, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCPY Z14.D, P14/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
MOVPRFX Z0, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z0.D, P7/M, Z0.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMINNM Z4.D, P4/M, Z4.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z5.D, P4/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z5.D, P7/Z, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z28.D, P6/M, Z5.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
SEL Z1.D, P15, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z26.D, P6/M, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MLA Z13.D, P4/M, Z25.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
SEL Z15.D, P15, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z30.D}, P5/Z, [X1, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MAD Z15.D, P4/M, Z25.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z4, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z4.D, P5/M, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z28.D}, P5/Z, [X1, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z5.D, P4/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z28.D, P5/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z4.D, P5/M, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MAD Z1.D, P4/M, Z19.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
FCMGT P7.D, P5/Z, Z4.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z0.D}, P5/Z, [X6, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z29, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z29.D, P4/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKHI Z3.D, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z29.D, P5/M, Z29.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LD1D {Z4.D}, P7/Z, [X4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SEL Z2.D, P5, Z29.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z14, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z14.D, P4/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z15, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z15.D, P7/M, Z15.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLE P15.D, P7/Z, Z28.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z28, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z28.D, P7/M, Z28.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z4, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z4.D, P7/M, Z4.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z29.D, P7/M, Z29.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z29.D, P7/M, Z29.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z29.D, P7/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z31.D, P7/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z31.D, P7/M, Z31.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FSUBR Z2.D, P5/M, Z2.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
EOR P15.B, P7/Z, P15.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMINNM Z5.D, P4/M, Z5.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z15, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCPY Z15.D, P15/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
MOVPRFX Z31, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMINNM Z31.D, P4/M, Z31.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z31.D, P7/Z, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z31.D, P7/M, Z31.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z30.D, P5/M, Z31.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z27.D, P5/M, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z26.D}, P6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z27.D}, P5, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X0, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P5.D, X0, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
INCW Z21.S, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P6.D, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 42c180 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone ._omp_fn.10]
Source file and lines	context.h:69-69
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:186,197-211

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 95% of vector register length is used (average across all VPU instructions).

Details

72% of VPU instructions are used in vector version (process two or more data elements in vector registers):

92% of VPU loads are used in vector version.
46% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 112.68 to 46.00 cycles (2.45x speedup).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Irregular (variable stride) or indirect: 3 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 144 FP arithmetical operations:

56: addition or subtraction (8 inside FMA instructions)
56: multiply (8 inside FMA instructions)
32: divide

The binary loop is loading 384 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.32 FP operations per loaded or stored byte.

General properties

nb instructions	122
nb uops	122
loop length	488
used w registers	0
used x registers	12
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	27
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.25 cycles
front end	15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	5.00	0.25	50.00	50.00	1.00	1.00	7.50	7.50	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	5.00	0.25	50.00	50.00	13.00	13.00	7.50	7.50	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	55.94-112.68
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.25
Dispatch	50.00
DIV/SQRT	55.94-112.68
Data deps.	2.00
Overall L1	55.94-112.68

Vectorization ratios

INT

all	53%
load	92%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
other	28%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	88%

INT+FP

all	72%
load	92%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	46%

Vector efficiency ratios

INT

all	94%
load	94%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
other	93%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	89%

INT+FP

all	95%
load	94%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	92%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 112.68 cycles. At this rate:

3% of peak load performance is reached (3.41 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42c180

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z26.D}, P6/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P5/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SUNPKHI Z29.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCMLT P14.D, P4/Z, Z26.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P15.D, P4/Z, Z27.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SUNPKLO Z15.D, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
UZP1 P13.S, P14.S, P15.S	1	0	0	0	0	1	0	0	0	0	0	0	0	2	1	scal (12.5%)
SEL Z31.S, P13, Z6.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKLO Z30.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
SUNPKHI Z31.D, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MAD Z30.D, P4/M, Z25.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MAD Z31.D, P4/M, Z25.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z5.D}, P6/Z, [X1, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P5/Z, [X1, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SEL Z14.D, P14, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z31.D, P14, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z15	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MLA Z30.D, P4/M, Z25.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MAD Z31.D, P4/M, Z19.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z28.D}, P6/Z, [X1, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MLA Z15.D, P4/M, Z25.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z30, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z30.D, P6/M, Z30.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z14.D}, P6/Z, [X1, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z4, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z4.D, P4/M, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z14.D, P6/M, Z14.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z30.D, P6/M, Z30.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z13.D}, P6/Z, [X6, Z31.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FCMGT P7.D, P6/Z, Z30.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SEL Z3.S, P13, Z7.S, Z20.S	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKLO Z30.D, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MOVPRFX Z31, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z31.D, P4/M, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z15.D}, P7/Z, [X4, Z30.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FDIV Z31.D, P6/M, Z31.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z13, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z13.D, P7/M, Z13.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z30.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z5, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z5.D, P4/M, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z1, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z1.D, P7/M, Z1.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z13, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z13.D, P7/M, Z13.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SEL Z15.D, P6, Z31.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z30.D, P7/M, Z30.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1RD {Z31.D}, P4/Z, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	scal (25.0%)
FSUBR Z15.D, P6/M, Z15.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLE P14.D, P7/Z, Z14.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FDIV Z30.D, P7/M, Z30.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
EOR P14.B, P7/Z, P14.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FADD Z30.D, P7/M, Z30.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z14, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCPY Z14.D, P14/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
MOVPRFX Z0, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z0.D, P7/M, Z0.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z0.D, P7/M, Z0.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMINNM Z4.D, P4/M, Z4.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z5.D, P4/M, Z5.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z5.D, P7/Z, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z28.D, P6/M, Z5.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
SEL Z1.D, P15, Z23.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z26.D, P6/M, Z26.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
MLA Z13.D, P4/M, Z25.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
SEL Z15.D, P15, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z30.D}, P5/Z, [X1, Z13.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MAD Z15.D, P4/M, Z25.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z4, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z4.D, P5/M, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z28.D}, P5/Z, [X1, Z15.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z5, Z4	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z5.D, P4/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z28.D, P5/M, Z28.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z4.D, P5/M, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MAD Z1.D, P4/M, Z19.D, Z29.D	1	0	0	0	0	0	0	1	0	0	0	0	0	5	2	vect (100.0%)
FCMGT P7.D, P5/Z, Z4.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
LD1D {Z0.D}, P5/Z, [X6, Z1.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z29, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z29.D, P4/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
SUNPKHI Z3.D, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z29.D, P5/M, Z29.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LD1D {Z4.D}, P7/Z, [X4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
SEL Z2.D, P5, Z29.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z14, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FABS Z14.D, P4/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z15, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z15.D, P7/M, Z15.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FCMLE P15.D, P7/Z, Z28.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z28, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z28.D, P7/M, Z28.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z4, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FSUB Z4.D, P7/M, Z4.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z29.D, P7/M, Z29.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z29.D, P7/M, Z29.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z29.D, P7/M, Z29.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z31.D, P7/M, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z31.D, P7/M, Z31.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FSUBR Z2.D, P5/M, Z2.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
EOR P15.B, P7/Z, P15.B, P7.B	1	0	0	0	0	1	0	0	0	0	0	0	0	1	1	vect (12.5%)
FMINNM Z5.D, P4/M, Z5.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z15, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FCPY Z15.D, P15/M, #1.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (3.1%)
MOVPRFX Z31, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMINNM Z31.D, P4/M, Z31.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z31.D, P7/Z, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z31.D, P7/M, Z31.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z30.D, P5/M, Z31.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z27.D, P5/M, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z26.D}, P6, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ST1D {Z27.D}, P5, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
ADD X0, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
WHILELO P5.D, X0, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
INCW Z21.S, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
WHILELO P6.D, X0, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2	N/A
B.NE 42c180 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code