OV - exec - Loop 309

	Loop Id: 309	Module: exec	Source: PdV.cpp:50-63 [...]	Coverage: 0.01%

0x434fcc LDR	X4, [SP, #104]

0x434fd0 SBFM	X1, X1, #0, #31

0x434fd4 ORR	W2, WZR, W2

0x434fd8 WHILELO	P7.D, XZR, X2

0x434fdc LDR	X6, [X22]

0x434fe0 LDR	X5, [X23]

0x434fe4 LDR	X11, [X4]

0x434fe8 MUL	X9, X8, X6

0x434fec LDR	X7, [X26]

0x434ff0 MUL	X20, X8, X5

0x434ff4 LDR	X30, [X22, #16]

0x434ff8 ADD	X6, X6, X9

0x434ffc ADD	X9, X9, X1

0x435000 MADD	X11, X8, X11, X1

0x435004 ADD	X6, X6, X1

0x435008 ADD	X5, X5, X20

0x43500c ADD	X20, X20, X1

0x435010 LDR	X0, [SP, #184]

0x435014 MUL	X10, X8, X7

0x435018 ADD	X5, X5, X1

0x43501c STR	X11, [SP, #128]

0x435020 LDR	X11, [SP, #120]

0x435024 ADD	X18, X30, X6,LSL #3

0x435028 ADD	X17, X30, X9,LSL #3

0x43502c ADD	X7, X7, X10

0x435030 ADD	X10, X10, X1

0x435034 ADD	X6, X30, X6,LSL #3

0x435038 ADD	X7, X7, X1

0x43503c LDR	X14, [X0]

0x435040 ADD	X9, X30, X9,LSL #3

0x435044 ADD	X18, X18, #8

0x435048 ADD	X17, X17, #8

0x43504c LDR	X21, [X27]

0x435050 LDR	X16, [X11]

0x435054 MADD	X15, X8, X14, X1

0x435058 LDR	X11, [X23, #16]

0x43505c MADD	X21, X8, X21, X1

0x435060 LDR	X14, [X27, #16]

0x435064 LDR	X3, [X24]

0x435068 ADD	X30, X11, X20,LSL #3

0x43506c LDR	X20, [X26, #16]

0x435070 LDR	X0, [X0, #16]

0x435074 MADD	X4, X8, X3, X1

0x435078 LDR	X3, [SP, #112]

0x43507c ADD	X7, X20, X7,LSL #3

0x435080 ADD	X10, X20, X10,LSL #3

0x435084 LDR	X20, [SP, #104]

0x435088 LDR	X13, [X25]

0x43508c LDR	X12, [X28]

0x435090 LDR	X20, [X20, #16]

0x435094 MADD	X13, X8, X13, X1

0x435098 LDR	X3, [X3]

0x43509c MADD	X12, X8, X12, X1

0x4350a0 STR	X20, [SP, #136]

0x4350a4 ADD	X20, X14, X21,LSL #3

0x4350a8 LDR	X21, [SP, #112]

0x4350ac MADD	X3, X8, X3, X1

0x4350b0 ORR	X14, XZR, X20

0x4350b4 ADD	X20, X20, #8

0x4350b8 MADD	X1, X8, X16, X1

0x4350bc ADD	X16, X11, X5,LSL #3

0x4350c0 ORR	X11, XZR, X30

0x4350c4 ADD	X30, X30, #8

0x4350c8 LDR	X21, [X21, #16]

0x4350cc ORR	X5, XZR, X16

0x4350d0 ADD	X16, X16, #8

0x4350d4 STP	X0, X21, [SP, #144]

0x4350d8 LDR	X21, [X24, #16]

0x4350dc LDR	X0, [X25, #16]

0x4350e0 ADD	X4, X21, X4,LSL #3

0x4350e4 LDR	X21, [SP, #120]

0x4350e8 ADD	X13, X0, X13,LSL #3

0x4350ec LDR	X0, [X28, #16]

0x4350f0 LDR	X21, [X21, #16]

0x4350f4 ADD	X12, X0, X12,LSL #3

0x4350f8 LDR	X0, [SP, #136]

0x4350fc STR	X21, [SP, #160]

0x435100 LDR	X21, [SP, #128]

0x435104 ADD	X21, X0, X21,LSL #3

0x435108 LDR	X0, [SP, #144]

0x43510c ADD	X15, X0, X15,LSL #3

0x435110 LDR	X0, [SP, #152]

0x435114 ADD	X3, X0, X3,LSL #3

0x435118 LDR	X0, [SP, #160]

0x43511c ADD	X1, X0, X1,LSL #3

0x435120 MOVZ	X0, #0

  (308) 0x435124 LD1D	{Z26.D}, P7/Z, [X9, X0,LSL #3]

  (308) 0x435128 LD1D	{Z3.D}, P7/Z, [X6, X0,LSL #3]

  (308) 0x43512c LD1D	{Z21.D}, P7/Z, [X17, X0,LSL #3]

  (308) 0x435130 LD1D	{Z2.D}, P7/Z, [X18, X0,LSL #3]

  (308) 0x435134 LD1D	{Z19.D}, P7/Z, [X11, X0,LSL #3]

  (308) 0x435138 LD1D	{Z18.D}, P7/Z, [X30, X0,LSL #3]

  (308) 0x43513c LD1D	{Z27.D}, P7/Z, [X14, X0,LSL #3]

  (308) 0x435140 LD1D	{Z1.D}, P7/Z, [X20, X0,LSL #3]

  (308) 0x435144 MOVPRFX	Z16, Z26

  (308) 0x435148 FADD	Z16.D, P7/M, Z16.D, Z3.D

  (308) 0x43514c MOVPRFX	Z24, Z21

  (308) 0x435150 FADD	Z24.D, P7/M, Z24.D, Z2.D

  (308) 0x435154 FADD	Z26.D, P7/M, Z26.D, Z16.D

  (308) 0x435158 FADD	Z21.D, P7/M, Z21.D, Z24.D

  (308) 0x43515c FADD	Z3.D, P7/M, Z3.D, Z26.D

  (308) 0x435160 FADD	Z2.D, P7/M, Z2.D, Z21.D

  (308) 0x435164 MOVPRFX	Z0, Z19

  (308) 0x435168 FADD	Z0.D, P7/M, Z0.D, Z18.D

  (308) 0x43516c FMUL	Z27.D, P7/M, Z27.D, Z3.D

  (308) 0x435170 FMUL	Z1.D, P7/M, Z1.D, Z2.D

  (308) 0x435174 FMUL	Z27.D, P7/M, Z27.D, Z30.D

  (308) 0x435178 FMUL	Z1.D, P7/M, Z1.D, Z30.D

  (308) 0x43517c LD1D	{Z3.D}, P7/Z, [X13, X0,LSL #3]

  (308) 0x435180 LD1D	{Z7.D}, P7/Z, [X5, X0,LSL #3]

  (308) 0x435184 LD1D	{Z6.D}, P7/Z, [X16, X0,LSL #3]

  (308) 0x435188 LD1D	{Z24.D}, P7/Z, [X4, X0,LSL #3]

  (308) 0x43518c LD1D	{Z5.D}, P7/Z, [X7, X0,LSL #3]

  (308) 0x435190 LD1D	{Z17.D}, P7/Z, [X10, X0,LSL #3]

  (308) 0x435194 LD1D	{Z21.D}, P7/Z, [X21, X0,LSL #3]

  (308) 0x435198 MOVPRFX	Z23, Z31

  (308) 0x43519c FMUL	Z23.D, P7/M, Z23.D, Z27.D

  (308) 0x4351a0 MOVPRFX	Z4, Z31

  (308) 0x4351a4 FMUL	Z4.D, P7/M, Z4.D, Z1.D

  (308) 0x4351a8 MOVPRFX	Z16, Z7

  (308) 0x4351ac FADD	Z16.D, P7/M, Z16.D, Z6.D

  (308) 0x4351b0 LD1D	{Z1.D}, P7/Z, [X12, X0,LSL #3]

  (308) 0x4351b4 FADD	Z19.D, P7/M, Z19.D, Z0.D

  (308) 0x4351b8 FMUL	Z4.D, P7/M, Z4.D, #0.0000000

  (308) 0x4351bc LD1D	{Z0.D}, P7/Z, [X15, X0,LSL #3]

  (308) 0x4351c0 FMLS	Z4.D, P7/M, Z23.D, Z29.D

  (308) 0x4351c4 FADD	Z7.D, P7/M, Z7.D, Z16.D

  (308) 0x4351c8 FADD	Z18.D, P7/M, Z18.D, Z19.D

  (308) 0x4351cc FADD	Z6.D, P7/M, Z6.D, Z7.D

  (308) 0x4351d0 FMUL	Z17.D, P7/M, Z17.D, Z18.D

  (308) 0x4351d4 FMUL	Z5.D, P7/M, Z5.D, Z6.D

  (308) 0x4351d8 FMUL	Z17.D, P7/M, Z17.D, Z30.D

  (308) 0x4351dc FMUL	Z5.D, P7/M, Z5.D, Z30.D

  (308) 0x4351e0 MOVPRFX	Z20, Z31

  (308) 0x4351e4 FMUL	Z20.D, P7/M, Z20.D, Z17.D

  (308) 0x4351e8 MOVPRFX	Z25, Z31

  (308) 0x4351ec FMUL	Z25.D, P7/M, Z25.D, Z5.D

  (308) 0x4351f0 MOVPRFX	Z22, Z28

  (308) 0x4351f4 FDIV	Z22.D, P7/M, Z22.D, Z3.D

  (308) 0x4351f8 FMUL	Z25.D, P7/M, Z25.D, #0.0000000

  (308) 0x4351fc FDIV	Z1.D, P7/M, Z1.D, Z24.D

  (308) 0x435200 FADD	Z25.D, P7/M, Z25.D, Z4.D

  (308) 0x435204 FDIV	Z21.D, P7/M, Z21.D, Z24.D

  (308) 0x435208 FMLS	Z25.D, P7/M, Z20.D, Z29.D

  (308) 0x43520c FADD	Z1.D, P7/M, Z1.D, Z21.D

  (308) 0x435210 MOVPRFX	Z2, Z25

  (308) 0x435214 FADD	Z2.D, P7/M, Z2.D, Z3.D

  (308) 0x435218 FMUL	Z25.D, P7/M, Z25.D, Z1.D

  (308) 0x43521c MOVPRFX	Z27, Z3

  (308) 0x435220 FDIV	Z27.D, P7/M, Z27.D, Z2.D

  (308) 0x435224 FMLS	Z0.D, P7/M, Z25.D, Z22.D

  (308) 0x435228 ST1D	{Z0.D}, P7, [X3, X0,LSL #3]

  (308) 0x43522c LD1D	{Z26.D}, P7/Z, [X4, X0,LSL #3]

  (308) 0x435230 FMUL	Z27.D, P7/M, Z27.D, Z26.D

  (308) 0x435234 ST1D	{Z27.D}, P7, [X1, X0,LSL #3]

  (308) 0x435238 ADD	X0, X0, X19

  (308) 0x43523c WHILELO	P7.D, X0, X2

  (308) 0x435240 B.NE	435124

0x435244 LDR	W0, [SP, #168]

0x435248 ADD	X8, X8, #1

0x43524c CMP	W0, W8

0x435250 B.LE	435290

0x435254 LDR	W3, [SP, #100]

0x435258 LDR	W0, [SP, #180]

0x43525c LDP	W1, W2, [SP, #172]

0x435260 SUB	W4, W0, W3

0x435264 CMP	W4, W2

0x435268 CSEL	W2, W4, W2, #9

0x43526c ADD	W0, W3, W2

0x435270 STR	W0, [SP, #100]

0x435274 CMP	W3, W0

0x435278 B.CC	434fcc

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 50 - 63

--------------------------------------------------------------------------------

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►97.50+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.50+	GOMP_parallel		libgomp.so.1.0.0
○	PdV(global_variables&, bool)	PdV.cpp:48	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	PdV.cpp:50-50,PdV.cpp:63-63,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	14.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	10.67
Front-end cycles	12.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	13.75
P3 cycles	13.75
P4 cycles	13.75
P5 cycles	13.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	14.50
P11 cycles	14.17
P12 cycles	14.33
P13 cycles	2.50
P14 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	100.00
Nb loads	NA
Nb stores	5.00
Nb stack references	21.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.83
Bytes prefetched	0.00
Bytes loaded	9.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.71
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	27.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	28.57

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.01
Bottlenecks	P10,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source	PdV.cpp:50-50,PdV.cpp:63-63,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.50
CQA cycles if no scalar integer	14.50
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	10.67
Front-end cycles	12.50
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	13.75
P3 cycles	13.75
P4 cycles	13.75
P5 cycles	13.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	14.50
P11 cycles	14.17
P12 cycles	14.33
P13 cycles	2.50
P14 cycles	2.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	100.00
Nb uops	100.00
Nb loads	NA
Nb stores	5.00
Nb stack references	21.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.83
Bytes prefetched	0.00
Bytes loaded	9.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.71
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	27.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	28.57

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	PdV.cpp:50-63
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50-63
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 14.50 to 10.67 cycles (1.36x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 9 bytes. The binary loop is storing 3 bytes.

General properties

nb instructions	100
nb uops	100
loop length	400
used w registers	7
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	14.50	14.17	14.33	2.50	2.50
cycles	1.00	1.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	14.50	14.17	14.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.50
Dispatch	14.50
Overall L1	14.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	27%
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

0% of peak load performance is reached (0.62 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 435254

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X4, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X1, X1, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ORR W2, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P7.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
LDR X6, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X5, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X9, X8, X6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X7, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL X20, X8, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR X30, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X6, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X11, X8, X11, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X6, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X5, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X20, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X10, X8, X7	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X5, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X30, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X30, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X7, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X30, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X9, X30, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X21, [X27]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X15, X8, X14, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X11, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X21, X8, X21, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X14, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X11, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X20, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X4, X8, X3, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X20, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X20, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X28]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X20, [X20, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X13, X8, X13, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X12, X8, X12, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR X20, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X20, X14, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X3, X8, X3, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ORR X14, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X1, X8, X16, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X16, X11, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X11, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X21, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X5, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X0, X21, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X24, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X21, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X0, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X28, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X0, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X0, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X0, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X0, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X0, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W0, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 435290 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W3, [SP, #100]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W0, [SP, #180]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W1, W2, [SP, #172]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W4, W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W2, W4, W2, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W3, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #100]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 434fcc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]
Source file and lines	PdV.cpp:50-63
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50-63
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 9 bytes. The binary loop is storing 3 bytes.

General properties

nb instructions	100
nb uops	100
loop length	400
used w registers	7
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.50 cycles
front end	12.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	14.50	14.17	14.33	2.50	2.50
cycles	1.00	1.00	13.75	13.75	13.75	13.75	0.00	0.00	0.00	0.00	14.50	14.17	14.33	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.50
Dispatch	14.50
Overall L1	14.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	27%
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

0% of peak load performance is reached (0.62 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 435254

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X4, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X1, X1, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ORR W2, WZR, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
WHILELO P7.D, XZR, X2	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
LDR X6, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X5, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X4]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X9, X8, X6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X7, [X26]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL X20, X8, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR X30, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X6, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X9, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X11, X8, X11, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X6, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X5, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X20, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X10, X8, X7	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X5, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STR X11, [SP, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X11, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X30, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X30, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X7, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X30, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X7, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X9, X30, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X17, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X21, [X27]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X15, X8, X14, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X11, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X21, X8, X21, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X14, [X27, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X11, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X20, [X26, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X4, X8, X3, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X3, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X20, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X20, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X20, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X28]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X20, [X20, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X13, X8, X13, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X3, [X3]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X12, X8, X12, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
STR X20, [SP, #136]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X20, X14, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X3, X8, X3, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ORR X14, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X1, X8, X16, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
ADD X16, X11, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X11, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X30, X30, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X21, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X5, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X16, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
STP X0, X21, [SP, #144]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X21, [X24, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X25, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X21, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X13, X0, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [X28, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X21, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X0, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X21, [SP, #160]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X21, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X0, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X0, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X0, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, X0, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W0, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 435290 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x3d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W3, [SP, #100]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W0, [SP, #180]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W1, W2, [SP, #172]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W4, W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
CMP W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W2, W4, W2, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W3, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #100]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 434fcc <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code