OV - exec - Loop 311

	Loop Id: 311	Module: exec	Source: PdV.cpp:72-83	Coverage: 8.11%

0x435600 LD1D	{Z21.D}, P7/Z, [X25, X0,LSL #3]    [19]

0x435604 LD1D	{Z26.D}, P7/Z, [X20, X0,LSL #3]    [7]

0x435608 LD1D	{Z2.D}, P7/Z, [X23, X0,LSL #3]    [14]

0x43560c LD1D	{Z7.D}, P7/Z, [X6, X0,LSL #3]    [2]

0x435610 LD1D	{Z25.D}, P7/Z, [X9, X0,LSL #3]    [5]

0x435614 LD1D	{Z24.D}, P7/Z, [X5, X0,LSL #3]    [1]

0x435618 LD1D	{Z0.D}, P7/Z, [X19, X0,LSL #3]    [26]

0x43561c LD1D	{Z22.D}, P7/Z, [X24, X0,LSL #3]    [16]

0x435620 LD1D	{Z1.D}, P7/Z, [X26, X0,LSL #3]    [21]

0x435624 LD1D	{Z3.D}, P7/Z, [X10, X0,LSL #3]    [6]

0x435628 FADD	Z22.D, P7/M, Z22.D, Z21.D

0x43562c FADD	Z3.D, P7/M, Z3.D, Z7.D

0x435630 FADD	Z22.D, P7/M, Z22.D, Z26.D

0x435634 FADD	Z3.D, P7/M, Z3.D, Z25.D

0x435638 FADD	Z22.D, P7/M, Z22.D, Z2.D

0x43563c FADD	Z3.D, P7/M, Z3.D, Z24.D

0x435640 FMUL	Z1.D, P7/M, Z1.D, Z22.D

0x435644 FMUL	Z1.D, P7/M, Z1.D, Z30.D

0x435648 LD1D	{Z22.D}, P7/Z, [X2, X0,LSL #3]    [17]

0x43564c LD1D	{Z28.D}, P7/Z, [X13, X0,LSL #3]    [13]

0x435650 LD1D	{Z6.D}, P7/Z, [X4, X0,LSL #3]    [27]

0x435654 LD1D	{Z17.D}, P7/Z, [X22, X0,LSL #3]    [12]

0x435658 LD1D	{Z16.D}, P7/Z, [X3, X0,LSL #3]    [25]

0x43565c LD1D	{Z7.D}, P7/Z, [X21, X0,LSL #3]    [10]

0x435660 LD1D	{Z5.D}, P7/Z, [X7, X0,LSL #3]    [3]

0x435664 LD1D	{Z18.D}, P7/Z, [X8, X0,LSL #3]    [4]

0x435668 LD1D	{Z20.D}, P7/Z, [X12, X0,LSL #3]    [11]

0x43566c LD1D	{Z19.D}, P7/Z, [X18, X0,LSL #3]    [24]

0x435670 LD1D	{Z27.D}, P7/Z, [X11, X0,LSL #3]    [9]

0x435674 LD1D	{Z21.D}, P7/Z, [X15, X0,LSL #3]    [18]

0x435678 MOVPRFX	Z4, Z31

0x43567c FMUL	Z4.D, P7/M, Z4.D, Z1.D

0x435680 FMUL	Z28.D, P7/M, Z28.D, Z3.D

0x435684 LD1D	{Z1.D}, P7/Z, [X16, X0,LSL #3]    [20]

0x435688 LD1D	{Z3.D}, P7/Z, [X17, X0,LSL #3]    [22]

0x43568c FADD	Z18.D, P7/M, Z18.D, Z0.D

0x435690 FMUL	Z28.D, P7/M, Z28.D, Z30.D

0x435694 LD1D	{Z0.D}, P7/Z, [X14, X0,LSL #3]    [15]

0x435698 FADD	Z6.D, P7/M, Z6.D, Z17.D

0x43569c FMLS	Z4.D, P7/M, Z31.D, Z28.D

0x4356a0 FADD	Z6.D, P7/M, Z6.D, Z16.D

0x4356a4 FADD	Z18.D, P7/M, Z18.D, Z20.D

0x4356a8 FADD	Z6.D, P7/M, Z6.D, Z7.D

0x4356ac FADD	Z18.D, P7/M, Z18.D, Z19.D

0x4356b0 FMUL	Z5.D, P7/M, Z5.D, Z6.D

0x4356b4 FMUL	Z27.D, P7/M, Z27.D, Z18.D

0x4356b8 FMUL	Z5.D, P7/M, Z5.D, Z30.D

0x4356bc MOVPRFX	Z23, Z29

0x4356c0 FDIV	Z23.D, P7/M, Z23.D, Z3.D

0x4356c4 MOVPRFX	Z25, Z31

0x4356c8 FMUL	Z25.D, P7/M, Z25.D, Z5.D

0x4356cc FMUL	Z27.D, P7/M, Z27.D, Z30.D

0x4356d0 FADD	Z25.D, P7/M, Z25.D, Z4.D

0x4356d4 FDIV	Z1.D, P7/M, Z1.D, Z22.D

0x4356d8 FMLS	Z25.D, P7/M, Z27.D, Z31.D

0x4356dc FDIV	Z21.D, P7/M, Z21.D, Z22.D

0x4356e0 MOVPRFX	Z2, Z25

0x4356e4 FADD	Z2.D, P7/M, Z2.D, Z3.D

0x4356e8 FADD	Z1.D, P7/M, Z1.D, Z21.D

0x4356ec MOVPRFX	Z26, Z3

0x4356f0 FDIV	Z26.D, P7/M, Z26.D, Z2.D

0x4356f4 FMUL	Z25.D, P7/M, Z25.D, Z1.D

0x4356f8 FMLS	Z0.D, P7/M, Z25.D, Z23.D

0x4356fc ST1D	{Z0.D}, P7, [X27, X0,LSL #3]    [23]

0x435700 LD1D	{Z24.D}, P7/Z, [X2, X0,LSL #3]    [17]

0x435704 FMUL	Z26.D, P7/M, Z26.D, Z24.D

0x435708 ST1D	{Z26.D}, P7, [X30, X0,LSL #3]    [8]

0x43570c INCD	X0, ALL

0x435710 WHILELO	P7.D, X0, X1

0x435714 B.NE	435600

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 72 - 83

--------------------------------------------------------------------------------

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

Coverage (%)	Name	Source Location	Module
►98.42+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	GOMP_parallel		libgomp.so.1.0.0
○	PdV(global_variables&, bool)	PdV.cpp:69	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43 - 2.89
Bottlenecks	P6, P8,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source	PdV.cpp:72-83
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	8.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	19.50
P7 cycles	19.50
P8 cycles	15.00
P9 cycles	15.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	70.00
Nb uops	70.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.29 - 2.63
Nb FLOP add-sub	60.00
Nb FLOP mul	48.00
Nb FLOP fma	12.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.90 - 32.03
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	92.54
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43 - 2.89
Bottlenecks	P6, P8,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source	PdV.cpp:72-83
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.97 - 56.34
CQA cycles if no scalar integer	27.97 - 56.34
CQA cycles if FP arith vectorized	27.97 - 56.34
CQA cycles if fully vectorized	27.97 - 56.34
Front-end cycles	8.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	19.50
P7 cycles	19.50
P8 cycles	15.00
P9 cycles	15.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	27.97 - 56.34
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	70.00
Nb uops	70.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.29 - 2.63
Nb FLOP add-sub	60.00
Nb FLOP mul	48.00
Nb FLOP fma	12.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.90 - 32.03
Bytes prefetched	0.00
Bytes loaded	832.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	92.54
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source file and lines	PdV.cpp:72-83
Module	exec

The loop is defined in /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:72-83.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 17.50 cycles (3.22x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
60: multiply (12 inside FMA instructions)
16: divide

The binary loop is loading 832 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	70
nb uops	70
loop length	280
used w registers	0
used x registers	29
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	1.25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.75 cycles
front end	8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	19.50	19.50	1.00	1.00	14.00	14.00	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	19.50	19.50	15.00	15.00	14.00	14.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-56.34
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.75
Dispatch	19.50
DIV/SQRT	27.97-56.34
Data deps.	2.00
Overall L1	27.97-56.34

Vectorization ratios

INT

all	84%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

15% of peak load performance is reached (14.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 435600

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z21.D}, P7/Z, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P7/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P7/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z25.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z1.D, P7/M, Z1.D, Z22.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z1.D, P7/M, Z1.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P7/Z, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P7/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P7/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P7/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P7/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z4, Z31	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z4.D, P7/M, Z4.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z18.D, P7/M, Z18.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z17.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLS Z4.D, P7/M, Z31.D, Z28.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z18.D, P7/M, Z18.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z18.D, P7/M, Z18.D, Z19.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z27.D, P7/M, Z27.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z23, Z29	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z23.D, P7/M, Z23.D, Z3.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z25, Z31	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z25.D, P7/M, Z25.D, Z5.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z27.D, P7/M, Z27.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z25.D, P7/M, Z25.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z1.D, P7/M, Z1.D, Z22.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLS Z25.D, P7/M, Z27.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIV Z21.D, P7/M, Z21.D, Z22.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z2, Z25	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z2.D, P7/M, Z2.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z1.D, P7/M, Z1.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z26, Z3	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z26.D, P7/M, Z26.D, Z2.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z25.D, P7/M, Z25.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLS Z0.D, P7/M, Z25.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z0.D}, P7, [X27, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z26.D, P7/M, Z26.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z26.D}, P7, [X30, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
INCD X0, ALL	1	0	0	1	0	0	0	0	0	0	2	1	N/A
WHILELO P7.D, X0, X1	1	0	0	1	0	0	0	0	0	0	3	2	N/A
B.NE 435600 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source file and lines	PdV.cpp:72-83
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 17.50 cycles (3.22x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

72: addition or subtraction (12 inside FMA instructions)
60: multiply (12 inside FMA instructions)
16: divide

The binary loop is loading 832 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	70
nb uops	70
loop length	280
used w registers	0
used x registers	29
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	0
used z registers	24
nb stack references	0
ADD-SUB / MUL ratio	1.25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.75 cycles
front end	8.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.00	0.00	2.00	0.00	19.50	19.50	1.00	1.00	14.00	14.00	0.00	0.00	0.00
cycles	0.50	0.50	0.00	0.00	2.00	0.00	19.50	19.50	15.00	15.00	14.00	14.00	0.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	27.97-56.34
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.75
Dispatch	19.50
DIV/SQRT	27.97-56.34
Data deps.	2.00
Overall L1	27.97-56.34

Vectorization ratios

INT

all	84%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

Vector efficiency ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.34 cycles. At this rate:

15% of peak load performance is reached (14.77 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 435600

Instruction	Nb FU	P0	P1	P4	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
LD1D {Z21.D}, P7/Z, [X25, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z26.D}, P7/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z2.D}, P7/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P7/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z25.D}, P7/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X26, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z26.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z25.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z22.D, P7/M, Z22.D, Z2.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, P7/M, Z3.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z1.D, P7/M, Z1.D, Z22.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z1.D, P7/M, Z1.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z22.D}, P7/Z, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z28.D}, P7/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z6.D}, P7/Z, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z17.D}, P7/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z16.D}, P7/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z7.D}, P7/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z5.D}, P7/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z18.D}, P7/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z20.D}, P7/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z19.D}, P7/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z27.D}, P7/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z21.D}, P7/Z, [X15, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
MOVPRFX Z4, Z31	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z4.D, P7/M, Z4.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z1.D}, P7/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
LD1D {Z3.D}, P7/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z18.D, P7/M, Z18.D, Z0.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z28.D, P7/M, Z28.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z0.D}, P7/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z17.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMLS Z4.D, P7/M, Z31.D, Z28.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z16.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z18.D, P7/M, Z18.D, Z20.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z6.D, P7/M, Z6.D, Z7.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z18.D, P7/M, Z18.D, Z19.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z6.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z27.D, P7/M, Z27.D, Z18.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z5.D, P7/M, Z5.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z23, Z29	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z23.D, P7/M, Z23.D, Z3.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z25, Z31	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FMUL Z25.D, P7/M, Z25.D, Z5.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z27.D, P7/M, Z27.D, Z30.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FADD Z25.D, P7/M, Z25.D, Z4.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z1.D, P7/M, Z1.D, Z22.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMLS Z25.D, P7/M, Z27.D, Z31.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
FDIV Z21.D, P7/M, Z21.D, Z22.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z2, Z25	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FADD Z2.D, P7/M, Z2.D, Z3.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
FADD Z1.D, P7/M, Z1.D, Z21.D	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z26, Z3	1	0	0	0	0.50	0.50	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z26.D, P7/M, Z26.D, Z2.D	1	0	0	0	1	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z25.D, P7/M, Z25.D, Z1.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLS Z0.D, P7/M, Z25.D, Z23.D	1	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z0.D}, P7, [X27, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
LD1D {Z24.D}, P7/Z, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0.50	0.50	6	0.50	vect (100.0%)
FMUL Z26.D, P7/M, Z26.D, Z24.D	1	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z26.D}, P7, [X30, X0,LSL #3]	1	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50	vect (100.0%)
INCD X0, ALL	1	0	0	1	0	0	0	0	0	0	2	1	N/A
WHILELO P7.D, X0, X1	1	0	0	1	0	0	0	0	0	0	3	2	N/A
B.NE 435600 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x334>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code