OV - exec - Loop 312

	Loop Id: 312	Module: exec	Source: PdV.cpp:71-83 [...]	Coverage: 0.02%

0x435410 LDR	X0, [SP, #280]

0x435414 SBFM	X12, X12, #0, #31

0x435418 ORR	W1, WZR, W1

0x43541c LDP	X18, X20, [SP, #144]

0x435420 WHILELO	P7.D, XZR, X1

0x435424 LDP	X15, X16, [SP, #128]

0x435428 LDP	X24, X25, [SP, #160]

0x43542c LDP	X11, X2, [SP, #112]

0x435430 LDP	X19, X21, [SP, #248]

0x435434 LDP	X22, X23, [SP, #264]

0x435438 LDR	X13, [X0]

0x43543c LDR	X7, [X2]

0x435440 LDR	X14, [X15]

0x435444 MADD	X17, X28, X13, X12

0x435448 LDR	X13, [X18]

0x43544c LDR	X2, [X11]

0x435450 MUL	X11, X28, X7

0x435454 LDR	X6, [X19]

0x435458 MADD	X15, X28, X13, X12

0x43545c ADD	X7, X7, X11

0x435460 ADD	X11, X11, X12

0x435464 LDR	X13, [X25]

0x435468 ADD	X7, X7, X12

0x43546c MADD	X27, X28, X2, X12

0x435470 LDR	X5, [X21]

0x435474 MUL	X10, X28, X6

0x435478 LDR	X4, [X22]

0x43547c MADD	X30, X28, X13, X12

0x435480 LDR	X3, [X23]

0x435484 ADD	X6, X6, X10

0x435488 ADD	X10, X10, X12

0x43548c MUL	X9, X28, X5

0x435490 ADD	X6, X6, X12

0x435494 LDR	X18, [X24]

0x435498 MUL	X8, X28, X4

0x43549c LDR	X2, [X16]

0x4354a0 MADD	X16, X28, X14, X12

0x4354a4 ADD	X5, X5, X9

0x4354a8 MUL	X26, X28, X3

0x4354ac ADD	X9, X9, X12

0x4354b0 ADD	X5, X5, X12

0x4354b4 LDR	X14, [X20]

0x4354b8 ADD	X4, X4, X8

0x4354bc ADD	X8, X8, X12

0x4354c0 ADD	X4, X4, X12

0x4354c4 LDR	X13, [SP, #112]

0x4354c8 ADD	X3, X3, X26

0x4354cc ADD	X26, X26, X12

0x4354d0 ADD	X3, X3, X12

0x4354d4 MADD	X2, X28, X2, X12

0x4354d8 LDR	X20, [X19, #16]

0x4354dc MADD	X19, X28, X18, X12

0x4354e0 MADD	X14, X28, X14, X12

0x4354e4 LDR	X18, [X22, #16]

0x4354e8 STR	X19, [SP, #224]

0x4354ec LDR	X12, [X23, #16]

0x4354f0 ADD	X24, X20, X10,LSL #3

0x4354f4 LDR	X19, [X21, #16]

0x4354f8 ADD	X25, X20, X6,LSL #3

0x4354fc ADD	X10, X20, X10,LSL #3

0x435500 ADD	X24, X24, #8

0x435504 LDR	X13, [X13, #16]

0x435508 ADD	X6, X20, X6,LSL #3

0x43550c ADD	X25, X25, #8

0x435510 ADD	X22, X18, X4,LSL #3

0x435514 LDR	X21, [SP, #120]

0x435518 ADD	X4, X18, X4,LSL #3

0x43551c ADD	X23, X19, X5,LSL #3

0x435520 ADD	X22, X22, #8

0x435524 LDR	X0, [X0, #16]

0x435528 ADD	X20, X19, X9,LSL #3

0x43552c ADD	X5, X19, X5,LSL #3

0x435530 ADD	X23, X23, #8

0x435534 ORR	X9, XZR, X20

0x435538 ADD	X20, X20, #8

0x43553c LDR	X21, [X21, #16]

0x435540 STP	X21, X0, [SP, #176]

0x435544 ADD	X21, X12, X3,LSL #3

0x435548 ORR	X3, XZR, X21

0x43554c ADD	X21, X21, #8

0x435550 LDR	X0, [SP, #128]

0x435554 LDR	X0, [X0, #16]

0x435558 STR	X0, [SP, #192]

0x43555c LDR	X0, [SP, #136]

0x435560 LDR	X19, [X0, #16]

0x435564 LDR	X0, [SP, #152]

0x435568 STR	X19, [SP, #200]

0x43556c ADD	X19, X18, X8,LSL #3

0x435570 LDR	X18, [SP, #144]

0x435574 ORR	X8, XZR, X19

0x435578 ADD	X19, X19, #8

0x43557c LDR	X18, [X18, #16]

0x435580 STR	X18, [SP, #208]

0x435584 ADD	X18, X12, X26,LSL #3

0x435588 LDR	X26, [X0, #16]

0x43558c ORR	X12, XZR, X18

0x435590 ADD	X18, X18, #8

0x435594 LDR	X0, [SP, #160]

0x435598 STR	X26, [SP, #216]

0x43559c LDR	X26, [SP, #176]

0x4355a0 ADD	X7, X26, X7,LSL #3

0x4355a4 ADD	X11, X26, X11,LSL #3

0x4355a8 ADD	X26, X13, X27,LSL #3

0x4355ac LDR	X27, [X0, #16]

0x4355b0 LDR	X0, [SP, #184]

0x4355b4 ORR	X13, XZR, X26

0x4355b8 ADD	X26, X26, #8

0x4355bc ADD	X17, X0, X17,LSL #3

0x4355c0 LDR	X0, [SP, #192]

0x4355c4 ADD	X16, X0, X16,LSL #3

0x4355c8 LDR	X0, [SP, #168]

0x4355cc LDR	X0, [X0, #16]

0x4355d0 STR	X0, [SP, #176]

0x4355d4 LDR	X0, [SP, #200]

0x4355d8 ADD	X2, X0, X2,LSL #3

0x4355dc LDR	X0, [SP, #208]

0x4355e0 ADD	X15, X0, X15,LSL #3

0x4355e4 LDR	X0, [SP, #216]

0x4355e8 ADD	X14, X0, X14,LSL #3

0x4355ec LDR	X0, [SP, #224]

0x4355f0 ADD	X27, X27, X0,LSL #3

0x4355f4 LDR	X0, [SP, #176]

0x4355f8 ADD	X30, X0, X30,LSL #3

0x4355fc MOVZ	X0, #0

  (311) 0x435600 LD1D	{Z21.D}, P7/Z, [X25, X0,LSL #3]

  (311) 0x435604 LD1D	{Z26.D}, P7/Z, [X20, X0,LSL #3]

  (311) 0x435608 LD1D	{Z2.D}, P7/Z, [X23, X0,LSL #3]

  (311) 0x43560c LD1D	{Z7.D}, P7/Z, [X6, X0,LSL #3]

  (311) 0x435610 LD1D	{Z25.D}, P7/Z, [X9, X0,LSL #3]

  (311) 0x435614 LD1D	{Z24.D}, P7/Z, [X5, X0,LSL #3]

  (311) 0x435618 LD1D	{Z0.D}, P7/Z, [X19, X0,LSL #3]

  (311) 0x43561c LD1D	{Z22.D}, P7/Z, [X24, X0,LSL #3]

  (311) 0x435620 LD1D	{Z1.D}, P7/Z, [X26, X0,LSL #3]

  (311) 0x435624 LD1D	{Z3.D}, P7/Z, [X10, X0,LSL #3]

  (311) 0x435628 FADD	Z22.D, P7/M, Z22.D, Z21.D

  (311) 0x43562c FADD	Z3.D, P7/M, Z3.D, Z7.D

  (311) 0x435630 FADD	Z22.D, P7/M, Z22.D, Z26.D

  (311) 0x435634 FADD	Z3.D, P7/M, Z3.D, Z25.D

  (311) 0x435638 FADD	Z22.D, P7/M, Z22.D, Z2.D

  (311) 0x43563c FADD	Z3.D, P7/M, Z3.D, Z24.D

  (311) 0x435640 FMUL	Z1.D, P7/M, Z1.D, Z22.D

  (311) 0x435644 FMUL	Z1.D, P7/M, Z1.D, Z30.D

  (311) 0x435648 LD1D	{Z22.D}, P7/Z, [X2, X0,LSL #3]

  (311) 0x43564c LD1D	{Z28.D}, P7/Z, [X13, X0,LSL #3]

  (311) 0x435650 LD1D	{Z6.D}, P7/Z, [X4, X0,LSL #3]

  (311) 0x435654 LD1D	{Z17.D}, P7/Z, [X22, X0,LSL #3]

  (311) 0x435658 LD1D	{Z16.D}, P7/Z, [X3, X0,LSL #3]

  (311) 0x43565c LD1D	{Z7.D}, P7/Z, [X21, X0,LSL #3]

  (311) 0x435660 LD1D	{Z5.D}, P7/Z, [X7, X0,LSL #3]

  (311) 0x435664 LD1D	{Z18.D}, P7/Z, [X8, X0,LSL #3]

  (311) 0x435668 LD1D	{Z20.D}, P7/Z, [X12, X0,LSL #3]

  (311) 0x43566c LD1D	{Z19.D}, P7/Z, [X18, X0,LSL #3]

  (311) 0x435670 LD1D	{Z27.D}, P7/Z, [X11, X0,LSL #3]

  (311) 0x435674 LD1D	{Z21.D}, P7/Z, [X15, X0,LSL #3]

  (311) 0x435678 MOVPRFX	Z4, Z31

  (311) 0x43567c FMUL	Z4.D, P7/M, Z4.D, Z1.D

  (311) 0x435680 FMUL	Z28.D, P7/M, Z28.D, Z3.D

  (311) 0x435684 LD1D	{Z1.D}, P7/Z, [X16, X0,LSL #3]

  (311) 0x435688 LD1D	{Z3.D}, P7/Z, [X17, X0,LSL #3]

  (311) 0x43568c FADD	Z18.D, P7/M, Z18.D, Z0.D

  (311) 0x435690 FMUL	Z28.D, P7/M, Z28.D, Z30.D

  (311) 0x435694 LD1D	{Z0.D}, P7/Z, [X14, X0,LSL #3]

  (311) 0x435698 FADD	Z6.D, P7/M, Z6.D, Z17.D

  (311) 0x43569c FMLS	Z4.D, P7/M, Z31.D, Z28.D

  (311) 0x4356a0 FADD	Z6.D, P7/M, Z6.D, Z16.D

  (311) 0x4356a4 FADD	Z18.D, P7/M, Z18.D, Z20.D

  (311) 0x4356a8 FADD	Z6.D, P7/M, Z6.D, Z7.D

  (311) 0x4356ac FADD	Z18.D, P7/M, Z18.D, Z19.D

  (311) 0x4356b0 FMUL	Z5.D, P7/M, Z5.D, Z6.D

  (311) 0x4356b4 FMUL	Z27.D, P7/M, Z27.D, Z18.D

  (311) 0x4356b8 FMUL	Z5.D, P7/M, Z5.D, Z30.D

  (311) 0x4356bc MOVPRFX	Z23, Z29

  (311) 0x4356c0 FDIV	Z23.D, P7/M, Z23.D, Z3.D

  (311) 0x4356c4 MOVPRFX	Z25, Z31

  (311) 0x4356c8 FMUL	Z25.D, P7/M, Z25.D, Z5.D

  (311) 0x4356cc FMUL	Z27.D, P7/M, Z27.D, Z30.D

  (311) 0x4356d0 FADD	Z25.D, P7/M, Z25.D, Z4.D

  (311) 0x4356d4 FDIV	Z1.D, P7/M, Z1.D, Z22.D

  (311) 0x4356d8 FMLS	Z25.D, P7/M, Z27.D, Z31.D

  (311) 0x4356dc FDIV	Z21.D, P7/M, Z21.D, Z22.D

  (311) 0x4356e0 MOVPRFX	Z2, Z25

  (311) 0x4356e4 FADD	Z2.D, P7/M, Z2.D, Z3.D

  (311) 0x4356e8 FADD	Z1.D, P7/M, Z1.D, Z21.D

  (311) 0x4356ec MOVPRFX	Z26, Z3

  (311) 0x4356f0 FDIV	Z26.D, P7/M, Z26.D, Z2.D

  (311) 0x4356f4 FMUL	Z25.D, P7/M, Z25.D, Z1.D

  (311) 0x4356f8 FMLS	Z0.D, P7/M, Z25.D, Z23.D

  (311) 0x4356fc ST1D	{Z0.D}, P7, [X27, X0,LSL #3]

  (311) 0x435700 LD1D	{Z24.D}, P7/Z, [X2, X0,LSL #3]

  (311) 0x435704 FMUL	Z26.D, P7/M, Z26.D, Z24.D

  (311) 0x435708 ST1D	{Z26.D}, P7, [X30, X0,LSL #3]

  (311) 0x43570c INCD	X0, ALL

  (311) 0x435710 WHILELO	P7.D, X0, X1

  (311) 0x435714 B.NE	435600

0x435718 LDR	W0, [SP, #232]

0x43571c ADD	X28, X28, #1

0x435720 CMP	W0, W28

0x435724 B.LE	435764

0x435728 LDR	W3, [SP, #108]

0x43572c LDR	W0, [SP, #244]

0x435730 LDP	W12, W2, [SP, #236]

0x435734 SUB	W4, W0, W3

0x435738 CMP	W4, W2

0x43573c CSEL	W1, W4, W2, #9

0x435740 ADD	W0, W3, W1

0x435744 STR	W0, [SP, #108]

0x435748 CMP	W3, W0

0x43574c B.CC	435410

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 71 - 83

--------------------------------------------------------------------------------

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Module
►100.00+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.28
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P10, P11, P12,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source	PdV.cpp:71-71,PdV.cpp:83-83,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.33
CQA cycles if no scalar integer	20.33
CQA cycles if FP arith vectorized	20.33
CQA cycles if fully vectorized	15.90
Front-end cycles	17.25
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	18.75
P3 cycles	18.75
P4 cycles	18.75
P5 cycles	18.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	20.33
P11 cycles	20.33
P12 cycles	20.33
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	138.00
Nb uops	138.00
Nb loads	NA
Nb stores	8.00
Nb stack references	35.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.59
Bytes prefetched	0.00
Bytes loaded	9.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.42
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	26.56
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	24.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	28.13

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.28
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P10, P11, P12,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source	PdV.cpp:71-71,PdV.cpp:83-83,context.h:69-69
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.33
CQA cycles if no scalar integer	20.33
CQA cycles if FP arith vectorized	20.33
CQA cycles if fully vectorized	15.90
Front-end cycles	17.25
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	18.75
P3 cycles	18.75
P4 cycles	18.75
P5 cycles	18.75
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	20.33
P11 cycles	20.33
P12 cycles	20.33
P13 cycles	4.00
P14 cycles	4.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	138.00
Nb uops	138.00
Nb loads	NA
Nb stores	8.00
Nb stack references	35.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.59
Bytes prefetched	0.00
Bytes loaded	9.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	25.42
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	26.56
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	24.50
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	28.13

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source file and lines	PdV.cpp:71-83
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71-83
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 20.33 to 15.90 cycles (1.28x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 9 bytes. The binary loop is storing 3 bytes.

General properties

nb instructions	138
nb uops	138
loop length	552
used w registers	8
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	35

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.25 cycles
front end	17.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	18.75	18.75	18.75	18.75	0.00	0.00	0.00	0.00	20.33	20.33	20.33	4.00	4.00
cycles	1.00	1.00	18.75	18.75	18.75	18.75	0.00	0.00	0.00	0.00	20.33	20.33	20.33	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.25
Dispatch	20.33
Overall L1	20.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	26%
mul	25%
add-sub	24%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.33 cycles. At this rate:

0% of peak load performance is reached (0.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.15 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 435728

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X0, [SP, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X12, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ORR W1, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X18, X20, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
WHILELO P7.D, XZR, X1	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
LDP X15, X16, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X25, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X2, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X21, [SP, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X23, [SP, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X13, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X17, X28, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X13, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X11, X28, X7	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR X6, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X15, X28, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X7, X7, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X27, X28, X2, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X5, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL X10, X28, X6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X4, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X30, X28, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X3, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X6, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X9, X28, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X18, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X8, X28, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X16, X28, X14, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X5, X5, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X26, X28, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X5, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X13, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X26, X26, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X3, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X2, X28, X2, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X20, [X19, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X19, X28, X18, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X14, X28, X14, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X18, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X24, X20, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X19, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X25, X20, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X10, X20, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X24, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X13, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X20, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X25, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X22, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X19, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X22, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X19, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X19, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X21, X0, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X21, X12, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X3, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X21, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #200]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X19, X18, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X18, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X18, X12, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X26, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X12, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X26, [SP, #216]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X7, X26, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X26, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X26, X13, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X27, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X13, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X26, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X0, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X0, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X0, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X0, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X27, X27, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X0, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W0, [SP, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W0, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 435764 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W3, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W0, [SP, #244]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W12, W2, [SP, #236]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W4, W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W1, W4, W2, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W3, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 435410 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.1]
Source file and lines	PdV.cpp:71-83
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71-83
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 9 bytes. The binary loop is storing 3 bytes.

General properties

nb instructions	138
nb uops	138
loop length	552
used w registers	8
used x registers	31
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	35

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.25 cycles
front end	17.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	18.75	18.75	18.75	18.75	0.00	0.00	0.00	0.00	20.33	20.33	20.33	4.00	4.00
cycles	1.00	1.00	18.75	18.75	18.75	18.75	0.00	0.00	0.00	0.00	20.33	20.33	20.33	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.25
Dispatch	20.33
Overall L1	20.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	26%
mul	25%
add-sub	24%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.33 cycles. At this rate:

0% of peak load performance is reached (0.44 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.15 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 435728

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X0, [SP, #280]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X12, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (100.0%)
ORR W1, WZR, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X18, X20, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
WHILELO P7.D, XZR, X1	1	0	0	0	0	1	0	0	0	0	0	0	3	2	N/A
LDP X15, X16, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X25, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X2, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X19, X21, [SP, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X23, [SP, #264]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X13, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X2]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X15]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X17, X28, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X13, [X18]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X11]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X11, X28, X7	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	N/A
LDR X6, [X19]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X15, X28, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X7, X7, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X11, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X25]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X7, X7, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MADD X27, X28, X2, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X5, [X21]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MUL X10, X28, X6	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X4, [X22]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X30, X28, X13, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X3, [X23]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X6, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X10, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X9, X28, X5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X6, X6, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X18, [X24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MUL X8, X28, X4	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X16, X28, X14, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
ADD X5, X5, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MUL X26, X28, X3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD X9, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X5, X5, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X14, [X20]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X4, X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X8, X8, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X4, X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X13, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X3, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X26, X26, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X3, X3, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
MADD X2, X28, X2, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
LDR X20, [X19, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X19, X28, X18, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	N/A
MADD X14, X28, X14, X12	1	0	0	0	0	1	0	0	0	0	0	0	2	1	scal (25.0%)
LDR X18, [X22, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X12, [X23, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X24, X20, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X19, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X25, X20, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X10, X20, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X24, X24, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X13, [X13, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X6, X20, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X25, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X22, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X4, X18, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X19, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X22, X22, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X20, X19, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X5, X19, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X23, X23, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X9, XZR, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X20, X20, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X21, [X21, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X21, X0, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X21, X12, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ORR X3, XZR, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X21, X21, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X19, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X19, [SP, #200]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X19, X18, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X8, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X19, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X18, [X18, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X18, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADD X18, X12, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X26, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X12, XZR, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X18, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X26, [SP, #216]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X26, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X7, X26, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X11, X26, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X26, X13, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X27, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X13, XZR, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
ADD X26, X26, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X17, X0, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X16, X0, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X0, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, X0, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X0, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X14, X0, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X27, X27, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X0, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X30, X0, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
LDR W0, [SP, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X28, X28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (25.0%)
CMP W0, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
B.LE 435764 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x498>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W3, [SP, #108]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W0, [SP, #244]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP W12, W2, [SP, #236]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W4, W0, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	scal (12.5%)
CSEL W1, W4, W2, #9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W0, W3, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25	N/A
STR W0, [SP, #108]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33	N/A
B.CC 435410 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code