OV - exec - Function calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, double&, int&, double&, double&, int&, int&, int&) [clone .omp

	Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ...	Module: exec	Source: calc_dt.cpp:49-75 [...]	Coverage (incl. loops): 4.33% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 49 - 75

--------------------------------------------------------------------------------

49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42c6d0 STP	D15, D14, [SP, #864]!

0x42c6d4 STP	D13, D12, [SP, #16]

0x42c6d8 STP	D11, D10, [SP, #32]

0x42c6dc STP	D9, D8, [SP, #48]

0x42c6e0 STP	X29, X30, [SP, #64]

0x42c6e4 STP	X28, X27, [SP, #80]

0x42c6e8 STP	X26, X25, [SP, #96]

0x42c6ec STP	X24, X23, [SP, #112]

0x42c6f0 STP	X22, X21, [SP, #128]

0x42c6f4 STP	X20, X19, [SP, #144]

0x42c6f8 ADD	X29, SP, #64

0x42c6fc SUB	SP, SP, #112

0x42c700 ADDVL	SP, SP, #47

0x42c704 LDR	W8, [X2]

0x42c708 LDR	W9, [X4]

0x42c70c ADD	W10, W8, #1

0x42c710 LDR	W8, [X3]

0x42c714 ADD	W26, W9, #1

0x42c718 STP	X9, X10, [SP, #48]

0x42c71c LDR	W9, [X5]

0x42c720 ADD	W8, W8, #2

0x42c724 ADD	W9, W9, #2

0x42c728 SUBS	W8, W8, W10

0x42c72c CCMP	W9, W26, #4, #12

0x42c730 B.LE	42c91c

0x42c734 LDR	X10, [X29, #192]

0x42c738 LDR	W1, [X0]

0x42c73c SUB	W11, W9, W26

0x42c740 MOVN	X9, #0

0x42c744 ORR	X20, XZR, X7

0x42c748 ORR	X21, XZR, X6

0x42c74c ADRP	X0,

0x42c750 ADD	X0, X0, #968

0x42c754 UMADDL	X27, W11, W8, X9

0x42c758 MOVN	X8, #32784

0x42c75c ADD	X3, SP, #84

0x42c760 ADD	X4, SP, #104

0x42c764 STP	X10, X11, [SP, #32]

0x42c768 STR	WZR, [SP, #84]

0x42c76c ADD	X5, SP, #96

0x42c770 ADD	X6, SP, #88

0x42c774 MOVZ	W2, #34

0x42c778 MOVZ	W7, #1

0x42c77c STR	X8, [SP, #72]

0x42c780 STP	X27, XZR, [SP, #96]

0x42c784 MOVZ	W10, #1

0x42c788 STR	W1, [SP, #28]

0x42c78c STR	X10, [SP, #88]

0x42c790 STR	X10, [SP]

0x42c794 BL	410680

0x42c798 LDR	X8, [SP, #96]

0x42c79c CMP	X8, X27

0x42c7a0 CSEL	X6, X8, X27, #11

0x42c7a4 LDR	X27, [SP, #104]

0x42c7a8 STR	X6, [SP, #96]

0x42c7ac CMP	X27, X6

0x42c7b0 B.LE	42c83c

0x42c7b4 LDR	W19, [SP, #28]

0x42c7b8 ADRP	X0,

0x42c7bc ADD	X0, X0, #992

0x42c7c0 ORR	W1, WZR, W19

0x42c7c4 BL	4105b0

0x42c7c8 ADD	X8, SP, #72

0x42c7cc ADRP	X6,

0x42c7d0 ADRP	X0,

0x42c7d4 ADD	X0, X0, #1016

0x42c7d8 ORR	W1, WZR, W19

0x42c7dc STR	X8, [SP, #64]

0x42c7e0 ADRP	X5, 42c7e0

0x42c7e4 ADD	X5, X5, #3728

0x42c7e8 ADD	X4, SP, #64

0x42c7ec MOVZ	W2, #1

0x42c7f0 LDR	X6, [X6, #3944]

0x42c7f4 MOVZ	W3, #8

0x42c7f8 BL	410520

0x42c7fc CMP	W0, #2

0x42c800 B.EQ	42c8ec

0x42c804 LDR	X8, [SP, #32]

0x42c808 CMP	W0, #1

0x42c80c B.NE	42c91c

0x42c810 LDR	D0, [X8]

0x42c814 LDR	D1, [SP, #72]

0x42c818 ADRP	X2,

0x42c81c ADRP	X0,

0x42c820 ADD	X0, X0, #1016

0x42c824 ORR	W1, WZR, W19

0x42c828 FMINNM	D0, D0, D1

0x42c82c STR	D0, [X8]

0x42c830 LDR	X2, [X2, #3944]

0x42c834 BL	410360

0x42c838 B	42c91c

0x42c83c LDP	X1, X2, [X29, #144]

0x42c840 LDP	X28, X7, [X29, #176]

0x42c844 ADD	X6, X6, #1

0x42c848 CNTD	X30, ALL

0x42c84c ADRP	X24,

0x42c850 LDR	X8, [X21, #8]

0x42c854 LDP	X15, X16, [X29, #112]

0x42c858 MOVN	X21, #32784

0x42c85c LDR	X9, [X20, #8]

0x42c860 LDR	D0, [X1]

0x42c864 LDP	X4, X19, [X29, #160]

0x42c868 LDR	D23, [X16]

0x42c86c LDP	X17, X0, [X29, #128]

0x42c870 LDP	X11, X13, [X29, #96]

0x42c874 FADD	D24, D0, D0

0x42c878 LDR	D0, [X28]

0x42c87c LDR	X22, [X11, #16]

0x42c880 LDR	X25, [X11]

0x42c884 LDR	X12, [X13, #16]

0x42c888 LDR	X13, [X13]

0x42c88c LDR	X14, [X15, #16]

0x42c890 LDR	X15, [X15]

0x42c894 LDR	X16, [X17, #16]

0x42c898 LDR	X17, [X17]

0x42c89c LDR	X18, [X0, #16]

0x42c8a0 LDR	X11, [X0]

0x42c8a4 LDR	X1, [X2, #16]

0x42c8a8 LDR	X10, [X2]

0x42c8ac LDR	X3, [X4, #16]

0x42c8b0 LDR	X4, [X4]

0x42c8b4 LDR	X5, [X19, #16]

0x42c8b8 SUB	X28, X6, X27

0x42c8bc ADRP	X2,

0x42c8c0 ADRP	X0,

0x42c8c4 CMP	X28, X30

0x42c8c8 FADD	D25, D0, D0

0x42c8cc LDR	D0, [X7]

0x42c8d0 LDR	X7, [X19]

0x42c8d4 FNEG	D26, D0

0x42c8d8 B.CS	42c950

0x42c8dc ORR	X23, XZR, X10

0x42c8e0 FMOV	D4, X21

0x42c8e4 ORR	X20, XZR, X27

0x42c8e8 B	42cca4

0x42c8ec LDR	X11, [SP, #32]

0x42c8f0 LDR	X8, [X11]

0x42c8f4 LDR	D0, [SP, #72]

0x42c8f8 ORR	X9, XZR, X8

0x42c8fc HINT	#0

(181) 0x42c900 FMOV	D1, X8

(181) 0x42c904 FMINNM	D1, D0, D1

(181) 0x42c908 FMOV	X10, D1

(181) 0x42c90c CAS	X9, X10, [X11]

(181) 0x42c910 CMP	X9, X8

(181) 0x42c914 ORR	X8, XZR, X9

(181) 0x42c918 B.NE	42c900

0x42c91c ADDVL	SP, SP, #17

0x42c920 ADD	SP, SP, #112

0x42c924 LDP	D9, D8, [SP, #48]

0x42c928 LDP	D11, D10, [SP, #32]

0x42c92c LDP	D13, D12, [SP, #16]

0x42c930 LDP	X20, X19, [SP, #144]

0x42c934 LDP	X22, X21, [SP, #128]

0x42c938 LDP	X24, X23, [SP, #112]

0x42c93c LDP	X26, X25, [SP, #96]

0x42c940 LDP	X28, X27, [SP, #80]

0x42c944 LDP	X29, X30, [SP, #64]

0x42c948 LDP	D15, D14, [SP], #160

0x42c94c RET

0x42c950 ORR	X24, XZR, X2

0x42c954 ORR	X2, XZR, X0

0x42c958 LDR	X0, [SP, #56]

0x42c95c SUB	X23, X29, #64

0x42c960 SUB	X19, XZR, X30

0x42c964 DUP	Z17.D, X17

0x42c968 STR	Z23, [X23, #498, MUL VL]

0x42c96c AND	X19, X28, X19

0x42c970 INDEX	Z14.D, X27, #1

0x42c974 ADD	W20, W0, #1

0x42c978 DUP	Z21.D, X4

0x42c97c DUP	Z22.D, X7

0x42c980 DUP	Z29.D, X21

0x42c984 DUP	Z31.D, X22

0x42c988 DUP	Z8.D, X12

0x42c98c DUP	Z9.D, X14

0x42c990 DUP	Z11.D, X16

0x42c994 PTRUE	P0.D, ALL

0x42c998 DUP	Z0.D, X20

0x42c99c SUB	X20, X29, #64

0x42c9a0 STR	Z0, [X20, #511, MUL VL]

0x42c9a4 ADD	X20, X27, X19

0x42c9a8 DUP	Z0.D, X25

0x42c9ac STR	Z0, [X23, #510, MUL VL]

0x42c9b0 DUP	Z0.D, X13

0x42c9b4 STR	Z0, [X23, #509, MUL VL]

0x42c9b8 DUP	Z0.D, X15

0x42c9bc STR	Z0, [X23, #508, MUL VL]

0x42c9c0 DUP	Z0.D, Z23.D[0]

0x42c9c4 STR	Z0, [X23, #507, MUL VL]

0x42c9c8 DUP	Z0.D, X11

0x42c9cc STR	Z0, [X23, #506, MUL VL]

0x42c9d0 DUP	Z0.D, X10

0x42c9d4 ORR	X23, XZR, X10

0x42c9d8 SUB	X10, X29, #64

0x42c9dc STR	Z24, [X10, #497, MUL VL]

0x42c9e0 STR	Z25, [X10, #496, MUL VL]

0x42c9e4 STR	Z26, [X10, #495, MUL VL]

0x42c9e8 STR	Z0, [X10, #505, MUL VL]

0x42c9ec DUP	Z0.D, Z24.D[0]

0x42c9f0 STR	Z0, [X10, #504, MUL VL]

0x42c9f4 DUP	Z0.D, Z25.D[0]

0x42c9f8 STR	Z0, [X10, #503, MUL VL]

0x42c9fc DUP	Z0.D, Z26.D[0]

0x42ca00 STR	Z0, [X10, #502, MUL VL]

0x42ca04 LDR	X10, [SP, #40]

0x42ca08 DUP	Z0.D, X0

0x42ca0c ORR	X0, XZR, X2

0x42ca10 ORR	X2, XZR, X24

0x42ca14 ADRP	X24,

0x42ca18 DUP	Z1.D, X10

0x42ca1c ORR	X10, XZR, X19

0x42ca20 SUB	X19, X29, #64

0x42ca24 STR	Z0, [X19, #501, MUL VL]

0x42ca28 DUP	Z0.D, X26

0x42ca2c STR	Z0, [X19, #500, MUL VL]

0x42ca30 DUP	Z0.D, X30

0x42ca34 STR	Z0, [X19, #499, MUL VL]

0x42ca38 LDR	D0, [X2, #2744]

0x42ca3c ADD	W19, W26, #1

0x42ca40 ORR	X26, XZR, X10

0x42ca44 DUP	Z30.D, X19

0x42ca48 DUP	Z10.D, Z0.D[0]

0x42ca4c LDR	D0, [X0, #2840]

0x42ca50 DUP	Z12.D, Z0.D[0]

0x42ca54 LDR	D0, [X24, #2848]

0x42ca58 DUP	Z13.D, Z0.D[0]

0x42ca5c HINT	#0

(183) 0x42ca60 MOVPRFX	Z0, Z14

(183) 0x42ca64 SDIV	Z0.D, P0/M, Z0.D, Z1.D

(183) 0x42ca68 SUB	X19, X29, #64

(183) 0x42ca6c DUP	Z24.D, X18

(183) 0x42ca70 SUBS	X26, X26, X30

(183) 0x42ca74 LDR	Z2, [X19, #501, MUL VL]

(183) 0x42ca78 LDR	Z6, [X19, #509, MUL VL]

(183) 0x42ca7c LDR	Z20, [X19, #511, MUL VL]

(183) 0x42ca80 LDR	Z23, [X19, #506, MUL VL]

(183) 0x42ca84 ADD	Z15.D, Z2.D, Z0.D

(183) 0x42ca88 LDR	Z2, [X19, #500, MUL VL]

(183) 0x42ca8c MOVPRFX	Z25, Z14

(183) 0x42ca90 MLS	Z25.D, P0/M, Z0.D, Z1.D

(183) 0x42ca94 ADD	Z0.D, Z0.D, Z20.D

(183) 0x42ca98 LDR	Z5, [X19, #510, MUL VL]

(183) 0x42ca9c MOVPRFX	Z20, Z0

(183) 0x42caa0 SXTW	Z20.D, P0/M, Z0.D

(183) 0x42caa4 MOVPRFX	Z0, Z17

(183) 0x42caa8 MUL	Z0.D, P0/M, Z0.D, Z20.D

(183) 0x42caac ADD	Z3.D, Z2.D, Z25.D

(183) 0x42cab0 LD1D	{Z2.D}, P0/Z, [X9, Z15.D,SXTW #3]

(183) 0x42cab4 SXTW	Z15.D, P0/M, Z15.D

(183) 0x42cab8 ADD	Z25.D, Z25.D, Z30.D

(183) 0x42cabc MUL	Z6.D, P0/M, Z6.D, Z15.D

(183) 0x42cac0 ADR	Z7.D, [Z8, Z3.D,SXTW #3]

(183) 0x42cac4 ADR	Z16.D, [Z9, Z3.D,SXTW #3]

(183) 0x42cac8 ADR	Z18.D, [Z11, Z3.D,SXTW #3]

(183) 0x42cacc LD1D	{Z4.D}, P0/Z, [X8, Z3.D,SXTW #3]

(183) 0x42cad0 ADR	Z28.D, [Z11, Z25.D,SXTW #3]

(183) 0x42cad4 MUL	Z23.D, P0/M, Z23.D, Z15.D

(183) 0x42cad8 MUL	Z5.D, P0/M, Z5.D, Z15.D

(183) 0x42cadc ADR	Z26.D, [Z24, Z3.D,SXTW #3]

(183) 0x42cae0 ADR	Z27.D, [Z31, Z3.D,SXTW #3]

(183) 0x42cae4 ADR	Z6.D, [Z7, Z6.D,LSL #3]

(183) 0x42cae8 LDR	Z7, [X19, #508, MUL VL]

(183) 0x42caec ADR	Z26.D, [Z26, Z23.D,LSL #3]

(183) 0x42caf0 ADR	Z5.D, [Z27, Z5.D,LSL #3]

(183) 0x42caf4 LD1D	{Z6.D}, P0/Z, [V6.D]

(183) 0x42caf8 FMINNM	Z2.D, P0/M, Z2.D, Z4.D

(183) 0x42cafc FADD	Z4.D, Z6.D, Z6.D

(183) 0x42cb00 MUL	Z7.D, P0/M, Z7.D, Z15.D

(183) 0x42cb04 ADR	Z7.D, [Z16, Z7.D,LSL #3]

(183) 0x42cb08 MOVPRFX	Z16, Z17

(183) 0x42cb0c MUL	Z16.D, P0/M, Z16.D, Z15.D

(183) 0x42cb10 LD1D	{Z26.D}, P0/Z, [V26.D]

(183) 0x42cb14 LD1D	{Z5.D}, P0/Z, [V5.D]

(183) 0x42cb18 LD1D	{Z7.D}, P0/Z, [V7.D]

(183) 0x42cb1c ADR	Z19.D, [Z18, Z16.D,LSL #3]

(183) 0x42cb20 ADR	Z18.D, [Z18, Z0.D,LSL #3]

(183) 0x42cb24 ADR	Z16.D, [Z28, Z16.D,LSL #3]

(183) 0x42cb28 ADR	Z0.D, [Z28, Z0.D,LSL #3]

(183) 0x42cb2c LD1D	{Z19.D}, P0/Z, [V19.D]

(183) 0x42cb30 LD1D	{Z18.D}, P0/Z, [V18.D]

(183) 0x42cb34 LD1D	{Z16.D}, P0/Z, [V16.D]

(183) 0x42cb38 LD1D	{Z0.D}, P0/Z, [V0.D]

(183) 0x42cb3c FDIV	Z4.D, P0/M, Z4.D, Z7.D

(183) 0x42cb40 LDR	Z7, [X19, #505, MUL VL]

(183) 0x42cb44 FADD	Z6.D, Z18.D, Z19.D

(183) 0x42cb48 ADR	Z18.D, [Z24, Z25.D,SXTW #3]

(183) 0x42cb4c FADD	Z0.D, Z0.D, Z16.D

(183) 0x42cb50 DUP	Z16.D, X1

(183) 0x42cb54 MUL	Z7.D, P0/M, Z7.D, Z15.D

(183) 0x42cb58 ADR	Z18.D, [Z18, Z23.D,LSL #3]

(183) 0x42cb5c FMUL	Z6.D, Z26.D, Z6.D

(183) 0x42cb60 DUP	Z23.D, X3

(183) 0x42cb64 ADR	Z16.D, [Z16, Z3.D,SXTW #3]

(183) 0x42cb68 LD1D	{Z18.D}, P0/Z, [V18.D]

(183) 0x42cb6c ADR	Z24.D, [Z23, Z3.D,SXTW #3]

(183) 0x42cb70 ADR	Z23.D, [Z23, Z25.D,SXTW #3]

(183) 0x42cb74 ADR	Z7.D, [Z16, Z7.D,LSL #3]

(183) 0x42cb78 MOVPRFX	Z16, Z6

(183) 0x42cb7c FABS	Z16.D, P0/M, Z6.D

(183) 0x42cb80 LD1D	{Z7.D}, P0/Z, [V7.D]

(183) 0x42cb84 FMLA	Z4.D, P0/M, Z5.D, Z5.D

(183) 0x42cb88 DUP	Z5.D, X5

(183) 0x42cb8c FMUL	Z0.D, Z0.D, Z18.D

(183) 0x42cb90 MOVPRFX	Z18, Z21

(183) 0x42cb94 MUL	Z18.D, P0/M, Z18.D, Z15.D

(183) 0x42cb98 ADR	Z3.D, [Z5, Z3.D,SXTW #3]

(183) 0x42cb9c MOVPRFX	Z5, Z21

(183) 0x42cba0 MUL	Z5.D, P0/M, Z5.D, Z20.D

(183) 0x42cba4 MUL	Z15.D, P0/M, Z15.D, Z22.D

(183) 0x42cba8 MUL	Z20.D, P0/M, Z20.D, Z22.D

(183) 0x42cbac FSQRT	Z4.D, P0/M, Z4.D

(183) 0x42cbb0 MOVPRFX	Z19, Z0

(183) 0x42cbb4 FABS	Z19.D, P0/M, Z0.D

(183) 0x42cbb8 FMUL	Z25.D, Z7.D, Z10.D

(183) 0x42cbbc FMAXNM	Z16.D, P0/M, Z16.D, Z19.D

(183) 0x42cbc0 LDR	Z19, [X19, #504, MUL VL]

(183) 0x42cbc4 ADR	Z26.D, [Z24, Z18.D,LSL #3]

(183) 0x42cbc8 ADR	Z18.D, [Z23, Z18.D,LSL #3]

(183) 0x42cbcc FMAXNM	Z16.D, P0/M, Z16.D, Z25.D

(183) 0x42cbd0 FMUL	Z19.D, Z7.D, Z19.D

(183) 0x42cbd4 FDIVR	Z16.D, P0/M, Z16.D, Z19.D

(183) 0x42cbd8 ADR	Z19.D, [Z24, Z5.D,LSL #3]

(183) 0x42cbdc ADR	Z5.D, [Z23, Z5.D,LSL #3]

(183) 0x42cbe0 ADR	Z23.D, [Z3, Z15.D,LSL #3]

(183) 0x42cbe4 ADR	Z3.D, [Z3, Z20.D,LSL #3]

(183) 0x42cbe8 LDR	Z20, [X19, #507, MUL VL]

(183) 0x42cbec FMAXNM	Z4.D, P0/M, Z4.D, Z10.D

(183) 0x42cbf0 FMUL	Z2.D, Z20.D, Z2.D

(183) 0x42cbf4 FDIV	Z2.D, P0/M, Z2.D, Z4.D

(183) 0x42cbf8 LD1D	{Z26.D}, P0/Z, [V26.D]

(183) 0x42cbfc LD1D	{Z18.D}, P0/Z, [V18.D]

(183) 0x42cc00 LD1D	{Z4.D}, P0/Z, [V23.D]

(183) 0x42cc04 LD1D	{Z19.D}, P0/Z, [V19.D]

(183) 0x42cc08 LD1D	{Z5.D}, P0/Z, [V5.D]

(183) 0x42cc0c LD1D	{Z3.D}, P0/Z, [V3.D]

(183) 0x42cc10 FADD	Z18.D, Z18.D, Z26.D

(183) 0x42cc14 FADD	Z5.D, Z5.D, Z19.D

(183) 0x42cc18 FMUL	Z3.D, Z5.D, Z3.D

(183) 0x42cc1c FMUL	Z4.D, Z4.D, Z18.D

(183) 0x42cc20 FADD	Z5.D, Z6.D, Z4.D

(183) 0x42cc24 FABS	Z4.D, P0/M, Z4.D

(183) 0x42cc28 FSUB	Z0.D, Z0.D, Z5.D

(183) 0x42cc2c FADD	Z0.D, Z0.D, Z3.D

(183) 0x42cc30 FABS	Z3.D, P0/M, Z3.D

(183) 0x42cc34 FMAXNM	Z3.D, P0/M, Z3.D, Z4.D

(183) 0x42cc38 LDR	Z4, [X19, #503, MUL VL]

(183) 0x42cc3c FMAXNM	Z3.D, P0/M, Z3.D, Z25.D

(183) 0x42cc40 FMUL	Z4.D, Z7.D, Z4.D

(183) 0x42cc44 FDIVR	Z3.D, P0/M, Z3.D, Z4.D

(183) 0x42cc48 FADD	Z4.D, Z7.D, Z7.D

(183) 0x42cc4c FDIV	Z0.D, P0/M, Z0.D, Z4.D

(183) 0x42cc50 LDR	Z4, [X19, #502, MUL VL]

(183) 0x42cc54 FDIV	Z4.D, P0/M, Z4.D, Z0.D

(183) 0x42cc58 FCMGT	P1.D, P0/Z, Z12.D, Z0.D

(183) 0x42cc5c ORR	Z0.D, Z13.D, Z13.D

(183) 0x42cc60 FMINNM	Z0.D, P1/M, Z0.D, Z4.D

(183) 0x42cc64 FMINNM	Z0.D, P0/M, Z0.D, Z3.D

(183) 0x42cc68 FMINNM	Z0.D, P0/M, Z0.D, Z16.D

(183) 0x42cc6c FMINNM	Z0.D, P0/M, Z0.D, Z2.D

(183) 0x42cc70 FMINNM	Z29.D, P0/M, Z29.D, Z0.D

(183) 0x42cc74 LDR	Z0, [X19, #499, MUL VL]

(183) 0x42cc78 ADD	Z14.D, Z14.D, Z0.D

(183) 0x42cc7c B.NE	42ca60

0x42cc80 FMINNMV	D4, P0, Z29.D

0x42cc84 CMP	X28, X10

0x42cc88 SUB	X10, X29, #64

0x42cc8c LDR	Z23, [X10, #498, MUL VL]

0x42cc90 LDR	Z24, [X10, #497, MUL VL]

0x42cc94 LDR	Z25, [X10, #496, MUL VL]

0x42cc98 LDR	Z26, [X10, #495, MUL VL]

0x42cc9c STR	D4, [SP, #72]

0x42cca0 B.EQ	42c7b4

0x42cca4 LDR	D5, [X2, #2744]

0x42cca8 LDR	D6, [X24, #2848]

0x42ccac LDR	D7, [X0, #2840]

0x42ccb0 LDR	X10, [SP, #40]

0x42ccb4 SUB	W21, WZR, W10

0x42ccb8 B	42cd7c

0x42ccbc HINT	#0

(182) 0x42ccc0 MUL	X10, X13, X28

(182) 0x42ccc4 ADD	X11, X12, X26

(182) 0x42ccc8 LDR	D1, [X8, X26]

(182) 0x42cccc LDR	D2, [X9, W27,SXTW #3]

(182) 0x42ccd0 FABS	D0, D0

(182) 0x42ccd4 FABS	D16, D16

(182) 0x42ccd8 ADD	X20, X20, #1

(182) 0x42ccdc ORR	X25, XZR, X13

(182) 0x42cce0 CMP	X6, X20

(182) 0x42cce4 ORR	X22, XZR, X12

(182) 0x42cce8 ORR	X13, XZR, X15

(182) 0x42ccec ORR	X12, XZR, X14

(182) 0x42ccf0 LDR	D20, [X11, X10,LSL #3]

(182) 0x42ccf4 MUL	X10, X15, X28

(182) 0x42ccf8 ADD	X11, X14, X26

(182) 0x42ccfc FMAXNM	D0, D0, D16

(182) 0x42cd00 FMUL	D16, D3, D5

(182) 0x42cd04 ORR	X15, XZR, X2

(182) 0x42cd08 ORR	X14, XZR, X0

(182) 0x42cd0c LDR	D21, [X11, X10,LSL #3]

(182) 0x42cd10 MUL	X10, X2, X28

(182) 0x42cd14 ADD	X11, X0, X26

(182) 0x42cd18 FMAXNM	D0, D0, D16

(182) 0x42cd1c LDR	D22, [X11, X10,LSL #3]

(182) 0x42cd20 FMINNM	D1, D1, D2

(182) 0x42cd24 FMUL	D2, D3, D24

(182) 0x42cd28 ORR	X11, XZR, X24

(182) 0x42cd2c FMUL	D1, D23, D1

(182) 0x42cd30 FDIV	D0, D2, D0

(182) 0x42cd34 FMUL	D2, D3, D25

(182) 0x42cd38 FABS	D3, D17

(182) 0x42cd3c FABS	D17, D18

(182) 0x42cd40 FADD	D21, D21, D21

(182) 0x42cd44 FMAXNM	D3, D3, D17

(182) 0x42cd48 FDIV	D21, D21, D22

(182) 0x42cd4c FMAXNM	D3, D3, D16

(182) 0x42cd50 FDIV	D2, D2, D3

(182) 0x42cd54 FMADD	D20, D20, D20, D21

(182) 0x42cd58 FMINNM	D2, D2, D19

(182) 0x42cd5c FSQRT	D20, D20

(182) 0x42cd60 FMINNM	D0, D0, D2

(182) 0x42cd64 FMAXNM	D20, D20, D5

(182) 0x42cd68 FDIV	D1, D1, D20

(182) 0x42cd6c FMINNM	D0, D1, D0

(182) 0x42cd70 FMINNM	D4, D0, D4

(182) 0x42cd74 STR	D4, [SP, #72]

(182) 0x42cd78 B.EQ	42c7b4

(182) 0x42cd7c LDR	X10, [SP, #40]

(182) 0x42cd80 ORR	X2, XZR, X15

(182) 0x42cd84 ORR	X15, XZR, X13

(182) 0x42cd88 ORR	X13, XZR, X25

(182) 0x42cd8c ORR	X0, XZR, X14

(182) 0x42cd90 ORR	X14, XZR, X12

(182) 0x42cd94 ORR	X12, XZR, X22

(182) 0x42cd98 ORR	X24, XZR, X11

(182) 0x42cd9c FMOV	D19, D6

(182) 0x42cda0 SDIV	X19, X20, X10

(182) 0x42cda4 LDR	X10, [SP, #56]

(182) 0x42cda8 ADD	W27, W10, W19

(182) 0x42cdac LDR	X10, [SP, #48]

(182) 0x42cdb0 ADD	W25, W27, #1

(182) 0x42cdb4 SBFM	X28, X27, #0, #31

(182) 0x42cdb8 SBFM	X25, X25, #0, #31

(182) 0x42cdbc MUL	X30, X17, X28

(182) 0x42cdc0 ADD	W26, W10, W20

(182) 0x42cdc4 MUL	X10, X17, X25

(182) 0x42cdc8 MADD	W19, W21, W19, W26

(182) 0x42cdcc ADD	W26, W19, #1

(182) 0x42cdd0 SBFM	X26, X26, #61, #31

(182) 0x42cdd4 ADD	X22, X16, X26

(182) 0x42cdd8 LDR	D0, [X22, X30,LSL #3]

(182) 0x42cddc LDR	D1, [X22, X10,LSL #3]

(182) 0x42cde0 MUL	X22, X11, X28

(182) 0x42cde4 ADD	X11, X18, X26

(182) 0x42cde8 FADD	D0, D1, D0

(182) 0x42cdec LDR	D1, [X11, X22,LSL #3]

(182) 0x42cdf0 ADD	W11, W19, #2

(182) 0x42cdf4 SBFM	X11, X11, #61, #31

(182) 0x42cdf8 ADD	X19, X16, X11

(182) 0x42cdfc LDR	D2, [X19, X10,LSL #3]

(182) 0x42ce00 ADD	X10, X18, X11

(182) 0x42ce04 ADD	X11, X3, X11

(182) 0x42ce08 FMUL	D0, D1, D0

(182) 0x42ce0c LDR	D1, [X19, X30,LSL #3]

(182) 0x42ce10 ADD	X19, X1, X26

(182) 0x42ce14 FADD	D1, D2, D1

(182) 0x42ce18 LDR	D2, [X10, X22,LSL #3]

(182) 0x42ce1c MUL	X10, X23, X28

(182) 0x42ce20 ADD	X22, X5, X26

(182) 0x42ce24 LDR	D3, [X19, X10,LSL #3]

(182) 0x42ce28 MUL	X10, X4, X28

(182) 0x42ce2c ADD	X19, X3, X26

(182) 0x42ce30 FMUL	D16, D1, D2

(182) 0x42ce34 LDR	D1, [X19, X10,LSL #3]

(182) 0x42ce38 LDR	D2, [X11, X10,LSL #3]

(182) 0x42ce3c MUL	X10, X7, X28

(182) 0x42ce40 FADD	D1, D2, D1

(182) 0x42ce44 LDR	D2, [X22, X10,LSL #3]

(182) 0x42ce48 MUL	X10, X4, X25

(182) 0x42ce4c FMUL	D17, D2, D1

(182) 0x42ce50 LDR	D1, [X19, X10,LSL #3]

(182) 0x42ce54 LDR	D2, [X11, X10,LSL #3]

(182) 0x42ce58 MUL	X10, X7, X25

(182) 0x42ce5c FADD	D1, D2, D1

(182) 0x42ce60 LDR	D2, [X22, X10,LSL #3]

(182) 0x42ce64 FMUL	D18, D1, D2

(182) 0x42ce68 FADD	D1, D0, D17

(182) 0x42ce6c FADD	D2, D3, D3

(182) 0x42ce70 FSUB	D1, D16, S1

(182) 0x42ce74 FADD	D1, D1, D18

(182) 0x42ce78 FDIV	D20, D1, D2

(182) 0x42ce7c FCMP	D20, D7

(182) 0x42ce80 B.GE	42ccc0

(182) 0x42ce84 FDIV	D1, D26, D20

(182) 0x42ce88 FMINNM	D19, D1, D6

(182) 0x42ce8c B	42ccc0

Coverage (%)	Name	Source Location	Module
►98.39+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.61+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	calc_dt_kernel(int, int, int, [...]	calc_dt.cpp:82	exec
○	calc_dt(global_variables&, int[...]	calc_dt.cpp:131	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:80	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.83 to 20.00 cycles (1.79x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 47% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 35.83 to 24.75 cycles (1.45x speedup).

Details

31% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
53% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
19% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 146 bytes. The binary function is storing 550 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	237
nb uops	234
loop length	948
used w registers	14
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	18
used q registers	0
used v registers	0
used z registers	19
nb stack references	41

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	29.25 cycles
front end	29.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.00	7.00	26.25	26.25	26.25	26.25	9.50	9.50	9.50	9.50	35.83	35.50	35.67	8.00	8.00
cycles	7.00	7.00	26.25	26.25	26.25	26.25	9.50	9.50	9.50	9.50	35.83	35.50	35.67	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	29.25
Dispatch	35.83
Overall L1	35.83

Vectorization ratios

INT

all	32%
load	25%
store	53%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	18%

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	31%
load	25%
store	53%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Vector efficiency ratios

INT

all	47%
load	37%
store	65%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	25%
other	39%

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

INT+FP

all	47%
load	37%
store	65%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.83 cycles. At this rate:

4% of peak load performance is reached (4.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.35 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42c6d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #47	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W26, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X9, X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W9, W26, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 42c91c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W9, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d74c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #968	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UMADDL X27, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVN X8, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X10, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X27, XZR, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X6, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X6, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X27, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 42c83c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <47d7b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #992	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X6, <47f7cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d7d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X5, 42c7e0 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x110>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #3728	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X6, #3944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410520 <@plt_start@+0x500>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42c8ec <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 42c91c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X2, <47f818>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d81c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMINNM D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #3944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410360 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42c91c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X2, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X7, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X30, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X24, <45184c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X16, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVN X21, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D0, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X4, X19, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D23, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X17, X0, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X13, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FADD D24, D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X22, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X25, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X28, X6, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X2, <4518bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4518c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X28, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FADD D25, D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D0, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X7, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FNEG D26, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B.CS 42c950 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D4, X21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X20, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42cca4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D0, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X9, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
ADDVL SP, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X23, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X19, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z17.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z23, [X23, #498, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
AND X19, X28, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INDEX Z14.D, X27, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
ADD W20, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z21.D, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z22.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z29.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z31.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z8.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z9.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z11.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
DUP Z0.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X20, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X20, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X20, X27, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z0.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X23, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X23, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X23, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, Z23.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X23, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X23, #506, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ORR X23, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z24, [X10, #497, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z25, [X10, #496, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z26, [X10, #495, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X10, #505, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, Z24.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X10, #504, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, Z25.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X10, #503, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, Z26.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X10, #502, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z0.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ORR X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X24, <451a14>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ORR X10, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X19, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X19, #501, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X19, #500, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X19, #499, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X2, #2744]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W19, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z30.D, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z10.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #2840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
DUP Z12.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X24, #2848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
DUP Z13.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
HINT #0																			N/A
FMINNMV D4, P0, Z29.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
CMP X28, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X10, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z23, [X10, #498, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z24, [X10, #497, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z25, [X10, #496, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z26, [X10, #495, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
STR D4, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B.EQ 42c7b4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X2, #2744]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D6, [X24, #2848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D7, [X0, #2840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W21, WZR, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42cd7c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x6ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

31% of VPU instructions are used in vector version (process two or more data elements in vector registers):

25% of VPU loads are used in vector version.
53% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
19% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 146 bytes. The binary function is storing 550 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	237
nb uops	234
loop length	948
used w registers	14
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	18
used q registers	0
used v registers	0
used z registers	19
nb stack references	41

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	29.25 cycles
front end	29.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	7.00	7.00	26.25	26.25	26.25	26.25	9.50	9.50	9.50	9.50	35.83	35.50	35.67	8.00	8.00
cycles	7.00	7.00	26.25	26.25	26.25	26.25	9.50	9.50	9.50	9.50	35.83	35.50	35.67	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	29.25
Dispatch	35.83
Overall L1	35.83

Vectorization ratios

INT

all	32%
load	25%
store	53%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	18%

all	16%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	31%
load	25%
store	53%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Vector efficiency ratios

INT

all	47%
load	37%
store	65%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	25%
other	39%

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

INT+FP

all	47%
load	37%
store	65%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.83 cycles. At this rate:

4% of peak load performance is reached (4.07 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (15.35 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42c6d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #47	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W10, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W26, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X9, X10, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W8, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W9, W26, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 42c91c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X29, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W11, W9, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d74c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #968	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
UMADDL X27, W11, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVN X8, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #84	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #104	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X10, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR WZR, [SP, #84]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD X5, SP, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X27, XZR, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVZ W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR W1, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X10, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X10, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X6, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X27, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X6, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP X27, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 42c83c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [SP, #28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <47d7b8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #992	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, SP, #72	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X6, <47f7cc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d7d0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR X8, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ADRP X5, 42c7e0 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x110>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, X5, #3728	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X6, [X6, #3944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 410520 <@plt_start@+0x500>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42c8ec <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x21c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 42c91c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D1, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADRP X2, <47f818>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d81c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1016	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMINNM D0, D0, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR D0, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X2, [X2, #3944]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 410360 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 42c91c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x24c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X1, X2, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X28, X7, [X29, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD X6, X6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X30, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
ADRP X24, <45184c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X8, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X16, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
MOVN X21, #32784	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D0, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X4, X19, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR D23, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X17, X0, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X13, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
FADD D24, D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D0, [X28]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X22, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X25, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X12, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X18, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X11, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X1, [X2, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X3, [X4, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X4, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X28, X6, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X2, <4518bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4518c0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X28, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FADD D25, D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR D0, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X7, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FNEG D26, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B.CS 42c950 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x280>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X23, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
FMOV D4, X21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X20, XZR, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42cca4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x5d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR D0, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ORR X9, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
HINT #0																			N/A
ADDVL SP, SP, #17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X24, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X0, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X23, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X19, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z17.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z23, [X23, #498, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
AND X19, X28, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
INDEX Z14.D, X27, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
ADD W20, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z21.D, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z22.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z29.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z31.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z8.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z9.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z11.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
DUP Z0.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X20, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X20, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD X20, X27, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z0.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X23, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X23, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X23, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, Z23.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X23, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X23, #506, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ORR X23, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X10, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z24, [X10, #497, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z25, [X10, #496, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z26, [X10, #495, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X10, #505, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, Z24.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X10, #504, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, Z25.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X10, #503, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, Z26.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z0, [X10, #502, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z0.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ORR X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X2, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X24, <451a14>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z1.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ORR X10, XZR, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X19, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X19, #501, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X19, #500, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X19, #499, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X2, #2744]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
ADD W19, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X26, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z30.D, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z10.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #2840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
DUP Z12.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X24, #2848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
DUP Z13.D, Z0.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
HINT #0																			N/A
FMINNMV D4, P0, Z29.D	1	0	0	0	0	0	0	0.75	0.75	0.25	0.25	0	0	0	0	0	9	2	vect (100.0%)
CMP X28, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB X10, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z23, [X10, #498, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z24, [X10, #497, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z25, [X10, #496, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
LDR Z26, [X10, #495, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	vect (100.0%)
STR D4, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
B.EQ 42c7b4 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D5, [X2, #2744]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D6, [X24, #2848]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR D7, [X0, #2840]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X10, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB W21, WZR, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
B 42cd7c <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x6ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D–	4.33	6.02
○Loop 183 - calc_dt.cpp:50-75 - exec	4.33	5.88
○Loop 181 - calc_dt.cpp:49-49 - exec	0.00	0.00
○Loop 182 - calc_dt.cpp:50-75 - exec	0.00	0.00

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