OV - exec - Function generate_chunk(int, global_variables&) [clone .omp

	Function: generate_chunk(int, global_variables&) [clone .omp_outlined.1]	Module: exec	Source: generate_chunk.cpp:85-123 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 85 - 123

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:     for (int j = (0); j < (yrange); j++) {

87:       for (int i = (0); i < (xrange); i++) {

88:         double x_cent = state_xmin[state];

89:         double y_cent = state_ymin[state];

90:         if (state_geometry[state] == g_rect) {

91:           if (field.vertexx[i + 1] >= state_xmin[state] && field.vertexx[i] < state_xmax[state]) {

92:             if (field.vertexy[j + 1] >= state_ymin[state] && field.vertexy[j] < state_ymax[state]) {

93:               field.energy0(i, j) = state_energy[state];

94:               field.density0(i, j) = state_density[state];

95:               for (int kt = j; kt <= j + 1; ++kt) {

96:                 for (int jt = i; jt <= i + 1; ++jt) {

97:                   field.xvel0(jt, kt) = state_xvel[state];

98:                   field.yvel0(jt, kt) = state_yvel[state];

[...]

105:               std::sqrt((field.cellx[i] - x_cent) * (field.cellx[i] - x_cent) + (field.celly[j] - y_cent) * (field.celly[j] - y_cent));

106:           if (radius <= state_radius[state]) {

107:             field.energy0(i, j) = state_energy[state];

108:             field.density0(i, j) = state_density[state];

109:             for (int kt = j; kt <= j + 1; ++kt) {

110:               for (int jt = i; jt <= i + 1; ++jt) {

111:                 field.xvel0(jt, kt) = state_xvel[state];

112:                 field.yvel0(jt, kt) = state_yvel[state];

113:               }

114:             }

115:           }

116:         } else if (state_geometry[state] == g_point) {

117:           if (field.vertexx[i] == x_cent && field.vertexy[j] == y_cent) {

118:             field.energy0(i, j) = state_energy[state];

119:             field.density0(i, j) = state_density[state];

120:             for (int kt = j; kt <= j + 1; ++kt) {

121:               for (int jt = i; jt <= i + 1; ++jt) {

122:                 field.xvel0(jt, kt) = state_xvel[state];

123:                 field.yvel0(jt, kt) = state_yvel[state];

0x42f040 LDR	W8, [X2]

0x42f044 LDR	W9, [X3]

0x42f048 CMP	W8, #1

0x42f04c CCMP	W9, #1, #8, #10

0x42f050 B.LT	42f114

0x42f054 SUB	SP, SP, #112

0x42f058 STP	X29, X30, [SP, #32]

0x42f05c STR	X25, [SP, #48]

0x42f060 STP	X24, X23, [SP, #64]

0x42f064 STP	X22, X21, [SP, #80]

0x42f068 STP	X20, X19, [SP, #96]

0x42f06c ADD	X29, SP, #32

0x42f070 LDR	W19, [X0]

0x42f074 SBFM	X24, X9, #0, #31

0x42f078 MOVN	X9, #0

0x42f07c ORR	X20, XZR, X7

0x42f080 ORR	X21, XZR, X6

0x42f084 ORR	X23, XZR, X5

0x42f088 ORR	X22, XZR, X4

0x42f08c ADRP	X0,

0x42f090 ADD	X0, X0, #1304

0x42f094 MADD	X25, X24, X8, X9

0x42f098 MOVZ	W8, #1

0x42f09c ADD	X3, SP, #12

0x42f0a0 ADD	X4, X29, #24

0x42f0a4 STR	XZR, [X29, #24]

0x42f0a8 ORR	W1, WZR, W19

0x42f0ac SUB	X5, X29, #8

0x42f0b0 ADD	X6, SP, #16

0x42f0b4 MOVZ	W2, #34

0x42f0b8 MOVZ	W7, #1

0x42f0bc STUR	X25, [X29, #504]

0x42f0c0 STR	X8, [SP, #16]

0x42f0c4 STR	WZR, [SP, #12]

0x42f0c8 STR	X8, [SP]

0x42f0cc BL	410680

0x42f0d0 LDUR	X8, [X29, #504]

0x42f0d4 LDR	X5, [X29, #24]

0x42f0d8 CMP	X8, X25

0x42f0dc CSEL	X4, X8, X25, #11

0x42f0e0 CMP	X5, X4

0x42f0e4 STUR	X4, [X29, #504]

0x42f0e8 B.LE	42f118

0x42f0ec ADRP	X0,

0x42f0f0 ADD	X0, X0, #1328

0x42f0f4 ORR	W1, WZR, W19

0x42f0f8 BL	4105b0

0x42f0fc LDP	X20, X19, [SP, #96]

0x42f100 LDP	X22, X21, [SP, #80]

0x42f104 LDR	X25, [SP, #48]

0x42f108 LDP	X24, X23, [SP, #64]

0x42f10c LDP	X29, X30, [SP, #32]

0x42f110 ADD	SP, SP, #112

0x42f114 RET

0x42f118 LDP	X13, X14, [X29, #120]

0x42f11c LDP	X11, X12, [X29, #104]

0x42f120 LDRSW	X8, [X23]

0x42f124 LDR	X15, [X20, #8]

0x42f128 LDR	X17, [X29, #80]

0x42f12c LDR	X10, [X21, #8]

0x42f130 ADD	X10, X10, X8,LSL #3

0x42f134 LDR	W1, [X15, X8,LSL #2]

0x42f138 LDR	X11, [X11, #8]

0x42f13c LDR	X12, [X12, #8]

0x42f140 LDR	X13, [X13, #8]

0x42f144 LDR	X14, [X14, #8]

0x42f148 LDR	X9, [X22, #8]

0x42f14c LDR	X15, [X17, #600]

0x42f150 ADD	X11, X11, X8,LSL #3

0x42f154 LDR	X16, [X17, #632]

0x42f158 LDR	X18, [X17, #64]

0x42f15c LDR	X21, [X17, #48]

0x42f160 LDR	X0, [X17, #16]

0x42f164 LDR	X6, [X17]

0x42f168 LDR	X2, [X17, #184]

0x42f16c LDR	X7, [X17, #168]

0x42f170 LDR	X3, [X17, #232]

0x42f174 LDR	X20, [X17, #216]

0x42f178 ADD	X12, X12, X8,LSL #3

0x42f17c ADD	X13, X13, X8,LSL #3

0x42f180 ADD	X14, X14, X8,LSL #3

0x42f184 CMP	W1, #1

0x42f188 B.EQ	42f4ec

0x42f18c CMP	W1, #2

0x42f190 B.EQ	42f334

0x42f194 CMP	W1, #3

0x42f198 B.NE	42f0ec

0x42f19c INDEX	Z2.D, X5, #1

0x42f1a0 SUB	X17, X4, X5

0x42f1a4 DUP	Z7.D, #1

0x42f1a8 DUP	Z16.D, #8

0x42f1ac MOVI	V17.2D, #0

0x42f1b0 ADD	X22, X17, #1

0x42f1b4 ORR	Z22.D, Z2.D, Z2.D

0x42f1b8 CNTD	X17, ALL

0x42f1bc SUBS	X1, X22, X17

0x42f1c0 CSEL	X1, XZR, X1, #3

0x42f1c4 DUP	Z0.D, X24

0x42f1c8 DUP	Z1.D, X21

0x42f1cc DUP	Z3.D, X6

0x42f1d0 DUP	Z4.D, X7

0x42f1d4 DUP	Z5.D, X20

0x42f1d8 DUP	Z6.D, X17

0x42f1dc SUB	X4, XZR, X17

0x42f1e0 DUP	Z18.D, X18

0x42f1e4 DUP	Z19.D, X0

0x42f1e8 DUP	Z20.D, X2

0x42f1ec DUP	Z21.D, X3

0x42f1f0 PTRUE	P0.D, ALL

0x42f1f4 WHILELO	P1.D, XZR, X22

0x42f1f8 HINT	#0

0x42f1fc HINT	#0

(208) 0x42f200 SEL	Z23.D, P1, Z0.D, Z7.D

(208) 0x42f204 LDR	D26, [X9, X8,LSL #3]

(208) 0x42f208 ADD	X4, X4, X17

(208) 0x42f20c SDIVR	Z23.D, P0/M, Z23.D, Z22.D

(208) 0x42f210 DUP	Z26.D, Z26.D[0]

(208) 0x42f214 MOVPRFX	Z24, Z23

(208) 0x42f218 MUL	Z24.D, P0/M, Z24.D, Z0.D

(208) 0x42f21c SUB	Z24.D, Z22.D, Z24.D

(208) 0x42f220 ADD	Z22.D, Z22.D, Z6.D

(208) 0x42f224 LD1D	{Z25.D}, P1/Z, [X15, Z24.D,SXTW #3]

(208) 0x42f228 ADR	Z28.D, [Z18, Z24.D,SXTW #3]

(208) 0x42f22c FCMEQ	P2.D, P0/Z, Z25.D, Z26.D

(208) 0x42f230 AND	P1.B, P1/Z, P1.B, P2.B

(208) 0x42f234 LD1D	{Z25.D}, P1/Z, [X10, Z17.D,LSL #3]

(208) 0x42f238 LD1D	{Z26.D}, P1/Z, [X16, Z23.D,SXTW #3]

(208) 0x42f23c FCMEQ	P2.D, P0/Z, Z26.D, Z25.D

(208) 0x42f240 MOVPRFX	Z25, Z23

(208) 0x42f244 SXTW	Z25.D, P0/M, Z23.D

(208) 0x42f248 MUL	Z23.D, P0/M, Z23.D, Z0.D

(208) 0x42f24c AND	P1.B, P1/Z, P1.B, P2.B

(208) 0x42f250 MOVPRFX	Z27, Z1

(208) 0x42f254 MUL	Z27.D, P0/M, Z27.D, Z25.D

(208) 0x42f258 SUB	Z23.D, Z2.D, Z23.D

(208) 0x42f25c ADD	Z2.D, Z2.D, Z6.D

(208) 0x42f260 LD1D	{Z26.D}, P1/Z, [X11, Z17.D,LSL #3]

(208) 0x42f264 ADR	Z27.D, [Z28, Z27.D,LSL #3]

(208) 0x42f268 ADR	Z28.D, [Z19, Z24.D,SXTW #3]

(208) 0x42f26c SXTW	Z24.D, P0/M, Z24.D

(208) 0x42f270 ST1D	{Z26.D}, P1, [V27.D]

(208) 0x42f274 MOVPRFX	Z27, Z3

(208) 0x42f278 MUL	Z27.D, P0/M, Z27.D, Z25.D

(208) 0x42f27c LD1D	{Z26.D}, P1/Z, [X12, Z17.D,LSL #3]

(208) 0x42f280 ADR	Z27.D, [Z28, Z27.D,LSL #3]

(208) 0x42f284 MOVPRFX	Z28, Z23

(208) 0x42f288 SXTW	Z28.D, P0/M, Z23.D

(208) 0x42f28c CMPGE	P2.D, P1/Z, Z24.D, Z28.D

(208) 0x42f290 ST1D	{Z26.D}, P1, [V27.D]

(208) 0x42f294 MOVPRFX	Z26, Z4

(208) 0x42f298 MUL	Z26.D, P0/M, Z26.D, Z25.D

(208) 0x42f29c ADR	Z26.D, [Z20, Z26.D,LSL #3]

(208) 0x42f2a0 ADR	Z29.D, [Z26, Z23.D,SXTW #3]

(208) 0x42f2a4 LD1D	{Z27.D}, P1/Z, [X13, Z17.D,LSL #3]

(208) 0x42f2a8 ST1D	{Z27.D}, P1, [V29.D]

(208) 0x42f2ac MOVPRFX	Z29, Z5

(208) 0x42f2b0 MUL	Z29.D, P0/M, Z29.D, Z25.D

(208) 0x42f2b4 ADD	Z25.D, Z25.D, #1

(208) 0x42f2b8 LD1D	{Z27.D}, P1/Z, [X14, Z17.D,LSL #3]

(208) 0x42f2bc ADR	Z29.D, [Z21, Z29.D,LSL #3]

(208) 0x42f2c0 ADR	Z30.D, [Z29, Z23.D,SXTW #3]

(208) 0x42f2c4 ST1D	{Z27.D}, P1, [V30.D]

(208) 0x42f2c8 ADR	Z27.D, [Z16, Z23.D,SXTW #3]

(208) 0x42f2cc LD1D	{Z24.D}, P2/Z, [X13, Z17.D,LSL #3]

(208) 0x42f2d0 ADD	Z26.D, Z26.D, Z27.D

(208) 0x42f2d4 ST1D	{Z24.D}, P2, [V26.D]

(208) 0x42f2d8 ADD	Z26.D, Z29.D, Z27.D

(208) 0x42f2dc LD1D	{Z24.D}, P2/Z, [X14, Z17.D,LSL #3]

(208) 0x42f2e0 ST1D	{Z24.D}, P2, [V26.D]

(208) 0x42f2e4 MOVPRFX	Z24, Z4

(208) 0x42f2e8 MUL	Z24.D, P0/M, Z24.D, Z25.D

(208) 0x42f2ec MUL	Z25.D, P0/M, Z25.D, Z5.D

(208) 0x42f2f0 LD1D	{Z26.D}, P1/Z, [X13, Z17.D,LSL #3]

(208) 0x42f2f4 ADR	Z24.D, [Z20, Z24.D,LSL #3]

(208) 0x42f2f8 ADR	Z25.D, [Z21, Z25.D,LSL #3]

(208) 0x42f2fc ADR	Z28.D, [Z24, Z23.D,SXTW #3]

(208) 0x42f300 ADR	Z23.D, [Z25, Z23.D,SXTW #3]

(208) 0x42f304 ADD	Z24.D, Z24.D, Z27.D

(208) 0x42f308 ST1D	{Z26.D}, P1, [V28.D]

(208) 0x42f30c LD1D	{Z26.D}, P1/Z, [X14, Z17.D,LSL #3]

(208) 0x42f310 ST1D	{Z26.D}, P1, [V23.D]

(208) 0x42f314 WHILELO	P1.D, X4, X1

(208) 0x42f318 LD1D	{Z23.D}, P2/Z, [X13, Z17.D,LSL #3]

(208) 0x42f31c ST1D	{Z23.D}, P2, [V24.D]

(208) 0x42f320 ADD	Z24.D, Z25.D, Z27.D

(208) 0x42f324 LD1D	{Z23.D}, P2/Z, [X14, Z17.D,LSL #3]

(208) 0x42f328 ST1D	{Z23.D}, P2, [V24.D]

(208) 0x42f32c B.MI	42f200

0x42f330 B	42f0ec

0x42f334 INDEX	Z2.D, X5, #1

0x42f338 LDR	X1, [X29, #136]

0x42f33c SUB	X4, X4, X5

0x42f340 LDR	X15, [X17, #536]

0x42f344 LDR	X17, [X17, #568]

0x42f348 ADD	X22, X4, #1

0x42f34c DUP	Z7.D, #1

0x42f350 DUP	Z16.D, #8

0x42f354 MOVI	V17.2D, #0

0x42f358 LDR	X1, [X1, #8]

0x42f35c CNTD	X16, ALL

0x42f360 SUBS	X4, X22, X16

0x42f364 CSEL	X4, XZR, X4, #3

0x42f368 DUP	Z0.D, X24

0x42f36c DUP	Z1.D, X21

0x42f370 SUB	X5, XZR, X16

0x42f374 ORR	Z22.D, Z2.D, Z2.D

0x42f378 DUP	Z3.D, X6

0x42f37c DUP	Z4.D, X7

0x42f380 DUP	Z5.D, X20

0x42f384 DUP	Z6.D, X16

0x42f388 DUP	Z18.D, X18

0x42f38c DUP	Z19.D, X0

0x42f390 DUP	Z20.D, X2

0x42f394 DUP	Z21.D, X3

0x42f398 PTRUE	P0.D, ALL

0x42f39c WHILELO	P1.D, XZR, X22

(207) 0x42f3a0 SEL	Z23.D, P1, Z0.D, Z7.D

(207) 0x42f3a4 LDR	D25, [X9, X8,LSL #3]

(207) 0x42f3a8 LDR	D27, [X10]

(207) 0x42f3ac ADD	X5, X5, X16

(207) 0x42f3b0 SDIVR	Z23.D, P0/M, Z23.D, Z22.D

(207) 0x42f3b4 DUP	Z25.D, Z25.D[0]

(207) 0x42f3b8 DUP	Z27.D, Z27.D[0]

(207) 0x42f3bc MOVPRFX	Z24, Z23

(207) 0x42f3c0 MUL	Z24.D, P0/M, Z24.D, Z0.D

(207) 0x42f3c4 SUB	Z24.D, Z22.D, Z24.D

(207) 0x42f3c8 ADD	Z22.D, Z22.D, Z6.D

(207) 0x42f3cc LD1D	{Z26.D}, P1/Z, [X15, Z24.D,SXTW #3]

(207) 0x42f3d0 ADR	Z28.D, [Z18, Z24.D,SXTW #3]

(207) 0x42f3d4 FSUB	Z25.D, Z26.D, Z25.D

(207) 0x42f3d8 LD1D	{Z26.D}, P1/Z, [X17, Z23.D,SXTW #3]

(207) 0x42f3dc FMUL	Z25.D, Z25.D, Z25.D

(207) 0x42f3e0 FSUB	Z26.D, Z26.D, Z27.D

(207) 0x42f3e4 FMLA	Z25.D, P0/M, Z26.D, Z26.D

(207) 0x42f3e8 LDR	D26, [X1, X8,LSL #3]

(207) 0x42f3ec FSQRT	Z25.D, P0/M, Z25.D

(207) 0x42f3f0 DUP	Z26.D, Z26.D[0]

(207) 0x42f3f4 FCMGE	P2.D, P0/Z, Z26.D, Z25.D

(207) 0x42f3f8 MOVPRFX	Z25, Z23

(207) 0x42f3fc SXTW	Z25.D, P0/M, Z23.D

(207) 0x42f400 MUL	Z23.D, P0/M, Z23.D, Z0.D

(207) 0x42f404 AND	P1.B, P1/Z, P1.B, P2.B

(207) 0x42f408 MOVPRFX	Z27, Z1

(207) 0x42f40c MUL	Z27.D, P0/M, Z27.D, Z25.D

(207) 0x42f410 LD1D	{Z26.D}, P1/Z, [X11, Z17.D,LSL #3]

(207) 0x42f414 SUB	Z23.D, Z2.D, Z23.D

(207) 0x42f418 ADD	Z2.D, Z2.D, Z6.D

(207) 0x42f41c ADR	Z27.D, [Z28, Z27.D,LSL #3]

(207) 0x42f420 ADR	Z28.D, [Z19, Z24.D,SXTW #3]

(207) 0x42f424 SXTW	Z24.D, P0/M, Z24.D

(207) 0x42f428 ST1D	{Z26.D}, P1, [V27.D]

(207) 0x42f42c MOVPRFX	Z27, Z3

(207) 0x42f430 MUL	Z27.D, P0/M, Z27.D, Z25.D

(207) 0x42f434 LD1D	{Z26.D}, P1/Z, [X12, Z17.D,LSL #3]

(207) 0x42f438 ADR	Z27.D, [Z28, Z27.D,LSL #3]

(207) 0x42f43c MOVPRFX	Z28, Z23

(207) 0x42f440 SXTW	Z28.D, P0/M, Z23.D

(207) 0x42f444 CMPGE	P2.D, P1/Z, Z24.D, Z28.D

(207) 0x42f448 ST1D	{Z26.D}, P1, [V27.D]

(207) 0x42f44c MOVPRFX	Z26, Z4

(207) 0x42f450 MUL	Z26.D, P0/M, Z26.D, Z25.D

(207) 0x42f454 ADR	Z26.D, [Z20, Z26.D,LSL #3]

(207) 0x42f458 LD1D	{Z27.D}, P1/Z, [X13, Z17.D,LSL #3]

(207) 0x42f45c ADR	Z29.D, [Z26, Z23.D,SXTW #3]

(207) 0x42f460 ST1D	{Z27.D}, P1, [V29.D]

(207) 0x42f464 MOVPRFX	Z29, Z5

(207) 0x42f468 MUL	Z29.D, P0/M, Z29.D, Z25.D

(207) 0x42f46c ADD	Z25.D, Z25.D, #1

(207) 0x42f470 LD1D	{Z27.D}, P1/Z, [X14, Z17.D,LSL #3]

(207) 0x42f474 ADR	Z29.D, [Z21, Z29.D,LSL #3]

(207) 0x42f478 ADR	Z30.D, [Z29, Z23.D,SXTW #3]

(207) 0x42f47c ST1D	{Z27.D}, P1, [V30.D]

(207) 0x42f480 ADR	Z27.D, [Z16, Z23.D,SXTW #3]

(207) 0x42f484 LD1D	{Z24.D}, P2/Z, [X13, Z17.D,LSL #3]

(207) 0x42f488 ADD	Z26.D, Z26.D, Z27.D

(207) 0x42f48c ST1D	{Z24.D}, P2, [V26.D]

(207) 0x42f490 ADD	Z26.D, Z29.D, Z27.D

(207) 0x42f494 LD1D	{Z24.D}, P2/Z, [X14, Z17.D,LSL #3]

(207) 0x42f498 ST1D	{Z24.D}, P2, [V26.D]

(207) 0x42f49c MOVPRFX	Z24, Z4

(207) 0x42f4a0 MUL	Z24.D, P0/M, Z24.D, Z25.D

(207) 0x42f4a4 MUL	Z25.D, P0/M, Z25.D, Z5.D

(207) 0x42f4a8 ADR	Z24.D, [Z20, Z24.D,LSL #3]

(207) 0x42f4ac ADR	Z25.D, [Z21, Z25.D,LSL #3]

(207) 0x42f4b0 ADR	Z28.D, [Z24, Z23.D,SXTW #3]

(207) 0x42f4b4 LD1D	{Z26.D}, P1/Z, [X13, Z17.D,LSL #3]

(207) 0x42f4b8 ADR	Z23.D, [Z25, Z23.D,SXTW #3]

(207) 0x42f4bc ADD	Z24.D, Z24.D, Z27.D

(207) 0x42f4c0 ST1D	{Z26.D}, P1, [V28.D]

(207) 0x42f4c4 LD1D	{Z26.D}, P1/Z, [X14, Z17.D,LSL #3]

(207) 0x42f4c8 ST1D	{Z26.D}, P1, [V23.D]

(207) 0x42f4cc WHILELO	P1.D, X5, X4

(207) 0x42f4d0 LD1D	{Z23.D}, P2/Z, [X13, Z17.D,LSL #3]

(207) 0x42f4d4 ST1D	{Z23.D}, P2, [V24.D]

(207) 0x42f4d8 ADD	Z24.D, Z25.D, Z27.D

(207) 0x42f4dc LD1D	{Z23.D}, P2/Z, [X14, Z17.D,LSL #3]

(207) 0x42f4e0 ST1D	{Z23.D}, P2, [V24.D]

(207) 0x42f4e4 B.MI	42f3a0

0x42f4e8 B	42f0ec

0x42f4ec INDEX	Z0.D, X5, #1

0x42f4f0 LDP	X22, X1, [X29, #88]

0x42f4f4 SUB	X4, X4, X5

0x42f4f8 DUP	Z6.D, #1

0x42f4fc ADD	X23, X4, #1

0x42f500 DUPM	Z16.D, #0x100000000

0x42f504 DUP	Z17.D, #8

0x42f508 CNTD	X17, ALL

0x42f50c MOVI	V18.2D, #0

0x42f510 SUBS	X4, X23, X17

0x42f514 CSEL	X4, XZR, X4, #3

0x42f518 DUP	Z1.D, X24

0x42f51c LDR	X5, [X1, #8]

0x42f520 LDR	X22, [X22, #8]

0x42f524 DUP	Z2.D, X21

0x42f528 SUB	X1, XZR, X17

0x42f52c ORR	Z23.D, Z0.D, Z0.D

0x42f530 DUP	Z3.D, X6

0x42f534 DUP	Z4.D, X7

0x42f538 DUP	Z5.D, X20

0x42f53c DUP	Z7.D, X17

0x42f540 ADD	X5, X5, X8,LSL #3

0x42f544 ADD	X6, X22, X8,LSL #3

0x42f548 DUP	Z19.D, X18

0x42f54c DUP	Z20.D, X0

0x42f550 DUP	Z21.D, X2

0x42f554 DUP	Z22.D, X3

0x42f558 PTRUE	P0.D, ALL

0x42f55c WHILELO	P1.D, XZR, X23

(206) 0x42f560 SEL	Z24.D, P1, Z1.D, Z6.D

(206) 0x42f564 LDR	D27, [X9, X8,LSL #3]

(206) 0x42f568 ADD	X1, X1, X17

(206) 0x42f56c SDIVR	Z24.D, P0/M, Z24.D, Z23.D

(206) 0x42f570 DUP	Z27.D, Z27.D[0]

(206) 0x42f574 MOVPRFX	Z25, Z24

(206) 0x42f578 MUL	Z25.D, P0/M, Z25.D, Z1.D

(206) 0x42f57c SUB	Z25.D, Z23.D, Z25.D

(206) 0x42f580 ADD	Z23.D, Z23.D, Z7.D

(206) 0x42f584 LSL	Z26.D, Z25.D, #32

(206) 0x42f588 ADR	Z29.D, [Z19, Z25.D,SXTW #3]

(206) 0x42f58c ADD	Z26.D, Z26.D, Z16.D

(206) 0x42f590 ASR	Z26.D, Z26.D, #-31

(206) 0x42f594 LD1D	{Z26.D}, P1/Z, [X15, Z26.D]

(206) 0x42f598 FCMGE	P2.D, P0/Z, Z26.D, Z27.D

(206) 0x42f59c AND	P1.B, P1/Z, P1.B, P2.B

(206) 0x42f5a0 LD1D	{Z26.D}, P1/Z, [X15, Z25.D,SXTW #3]

(206) 0x42f5a4 LD1D	{Z27.D}, P1/Z, [X6, Z18.D,LSL #3]

(206) 0x42f5a8 FCMGT	P2.D, P0/Z, Z27.D, Z26.D

(206) 0x42f5ac LSL	Z26.D, Z24.D, #32

(206) 0x42f5b0 LDR	D27, [X10]

(206) 0x42f5b4 ADD	Z26.D, Z26.D, Z16.D

(206) 0x42f5b8 AND	P1.B, P1/Z, P1.B, P2.B

(206) 0x42f5bc ASR	Z26.D, Z26.D, #-31

(206) 0x42f5c0 LD1D	{Z26.D}, P1/Z, [X16, Z26.D]

(206) 0x42f5c4 DUP	Z27.D, Z27.D[0]

(206) 0x42f5c8 FCMGE	P2.D, P0/Z, Z26.D, Z27.D

(206) 0x42f5cc AND	P1.B, P1/Z, P1.B, P2.B

(206) 0x42f5d0 LD1D	{Z26.D}, P1/Z, [X16, Z24.D,SXTW #3]

(206) 0x42f5d4 LD1D	{Z27.D}, P1/Z, [X5, Z18.D,LSL #3]

(206) 0x42f5d8 FCMGT	P2.D, P0/Z, Z27.D, Z26.D

(206) 0x42f5dc MOVPRFX	Z26, Z24

(206) 0x42f5e0 SXTW	Z26.D, P0/M, Z24.D

(206) 0x42f5e4 MUL	Z24.D, P0/M, Z24.D, Z1.D

(206) 0x42f5e8 AND	P1.B, P1/Z, P1.B, P2.B

(206) 0x42f5ec MOVPRFX	Z28, Z2

(206) 0x42f5f0 MUL	Z28.D, P0/M, Z28.D, Z26.D

(206) 0x42f5f4 LD1D	{Z27.D}, P1/Z, [X11, Z18.D,LSL #3]

(206) 0x42f5f8 SUB	Z24.D, Z0.D, Z24.D

(206) 0x42f5fc ADD	Z0.D, Z0.D, Z7.D

(206) 0x42f600 ADR	Z28.D, [Z29, Z28.D,LSL #3]

(206) 0x42f604 ADR	Z29.D, [Z20, Z25.D,SXTW #3]

(206) 0x42f608 SXTW	Z25.D, P0/M, Z25.D

(206) 0x42f60c ST1D	{Z27.D}, P1, [V28.D]

(206) 0x42f610 MOVPRFX	Z28, Z3

(206) 0x42f614 MUL	Z28.D, P0/M, Z28.D, Z26.D

(206) 0x42f618 ADR	Z28.D, [Z29, Z28.D,LSL #3]

(206) 0x42f61c MOVPRFX	Z29, Z24

(206) 0x42f620 SXTW	Z29.D, P0/M, Z24.D

(206) 0x42f624 LD1D	{Z27.D}, P1/Z, [X12, Z18.D,LSL #3]

(206) 0x42f628 CMPGE	P2.D, P1/Z, Z25.D, Z29.D

(206) 0x42f62c ST1D	{Z27.D}, P1, [V28.D]

(206) 0x42f630 MOVPRFX	Z27, Z4

(206) 0x42f634 MUL	Z27.D, P0/M, Z27.D, Z26.D

(206) 0x42f638 LD1D	{Z28.D}, P1/Z, [X13, Z18.D,LSL #3]

(206) 0x42f63c ADR	Z27.D, [Z21, Z27.D,LSL #3]

(206) 0x42f640 ADR	Z30.D, [Z27, Z24.D,SXTW #3]

(206) 0x42f644 ST1D	{Z28.D}, P1, [V30.D]

(206) 0x42f648 MOVPRFX	Z30, Z5

(206) 0x42f64c MUL	Z30.D, P0/M, Z30.D, Z26.D

(206) 0x42f650 ADD	Z26.D, Z26.D, #1

(206) 0x42f654 LD1D	{Z28.D}, P1/Z, [X14, Z18.D,LSL #3]

(206) 0x42f658 ADR	Z30.D, [Z22, Z30.D,LSL #3]

(206) 0x42f65c ADR	Z31.D, [Z30, Z24.D,SXTW #3]

(206) 0x42f660 ST1D	{Z28.D}, P1, [V31.D]

(206) 0x42f664 ADR	Z28.D, [Z17, Z24.D,SXTW #3]

(206) 0x42f668 ADD	Z27.D, Z27.D, Z28.D

(206) 0x42f66c LD1D	{Z25.D}, P2/Z, [X13, Z18.D,LSL #3]

(206) 0x42f670 ST1D	{Z25.D}, P2, [V27.D]

(206) 0x42f674 ADD	Z27.D, Z30.D, Z28.D

(206) 0x42f678 LD1D	{Z25.D}, P2/Z, [X14, Z18.D,LSL #3]

(206) 0x42f67c ST1D	{Z25.D}, P2, [V27.D]

(206) 0x42f680 MOVPRFX	Z25, Z4

(206) 0x42f684 MUL	Z25.D, P0/M, Z25.D, Z26.D

(206) 0x42f688 ADR	Z25.D, [Z21, Z25.D,LSL #3]

(206) 0x42f68c LD1D	{Z27.D}, P1/Z, [X13, Z18.D,LSL #3]

(206) 0x42f690 MUL	Z26.D, P0/M, Z26.D, Z5.D

(206) 0x42f694 ADR	Z26.D, [Z22, Z26.D,LSL #3]

(206) 0x42f698 ADR	Z29.D, [Z25, Z24.D,SXTW #3]

(206) 0x42f69c ADR	Z24.D, [Z26, Z24.D,SXTW #3]

(206) 0x42f6a0 ADD	Z25.D, Z25.D, Z28.D

(206) 0x42f6a4 ST1D	{Z27.D}, P1, [V29.D]

(206) 0x42f6a8 LD1D	{Z27.D}, P1/Z, [X14, Z18.D,LSL #3]

(206) 0x42f6ac ST1D	{Z27.D}, P1, [V24.D]

(206) 0x42f6b0 WHILELO	P1.D, X1, X4

(206) 0x42f6b4 LD1D	{Z24.D}, P2/Z, [X13, Z18.D,LSL #3]

(206) 0x42f6b8 ST1D	{Z24.D}, P2, [V25.D]

(206) 0x42f6bc ADD	Z25.D, Z26.D, Z28.D

(206) 0x42f6c0 LD1D	{Z24.D}, P2/Z, [X14, Z18.D,LSL #3]

(206) 0x42f6c4 ST1D	{Z24.D}, P2, [V25.D]

(206) 0x42f6c8 B.MI	42f560

0x42f6cc B	42f0ec

0x42f6d0 HINT	#0

0x42f6d4 HINT	#0

0x42f6d8 HINT	#0

0x42f6dc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.43+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.57+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	stl_vector.h:735	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	generate_chunk.cpp:85-123
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98,105-123

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 40.00 to 36.00 cycles (1.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 29% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 40.00 to 16.00 cycles (2.50x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	175
nb uops	169
loop length	700
used w registers	7
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	2
used z registers	16
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.13 cycles
front end	21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	18.00	18.00	40.00	18.00	6.50	6.50	1.50	1.50	16.83	16.50	16.67	5.50	5.50
cycles	5.50	5.50	18.00	18.00	40.00	18.00	6.50	6.50	1.50	1.50	16.83	16.50	16.67	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.13
Dispatch	40.00
Overall L1	40.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

all	29%
load	22%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

0% of peak load performance is reached (0.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.07 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42f040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W9, #1, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LT 42f114 <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SBFM X24, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d08c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X25, X24, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR X25, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X4, X8, X25, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X4, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 42f118 <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <47d0ec>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X14, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDRSW X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X10, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W1, [X15, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X17, #600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X11, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, #632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X17, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X21, [X17, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X17, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X17, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X17, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X17, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X12, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X13, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X14, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42f4ec <_Z14generate_chunkiR16global_variables.omp_outlined.1+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42f334 <_Z14generate_chunkiR16global_variables.omp_outlined.1+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 42f0ec <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z2.D, X5, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
SUB X17, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z7.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
DUP Z16.D, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V17.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X22, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR Z22.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUBS X1, X22, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL X1, XZR, X1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z0.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z1.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z3.D, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z4.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z5.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X4, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z18.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z19.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z21.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P1.D, XZR, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
HINT #0																			N/A
HINT #0																			N/A
B 42f0ec <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z2.D, X5, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
LDR X1, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X4, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X15, [X17, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X17, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X22, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z7.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
DUP Z16.D, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V17.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X1, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUBS X4, X22, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X4, XZR, X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z0.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z1.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X5, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR Z22.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z4.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z5.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z18.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z19.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z21.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P1.D, XZR, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 42f0ec <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z0.D, X5, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
LDP X22, X1, [X29, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SUB X4, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z6.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
ADD X23, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUPM Z16.D, #0x100000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z17.D, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVI V18.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUBS X4, X23, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X4, XZR, X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z1.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDR X5, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X22, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z2.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X1, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR Z23.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z4.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z5.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z7.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X5, X5, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X22, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z19.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z21.D, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z22.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P1.D, XZR, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 42f0ec <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	generate_chunk.cpp:85-123
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85-98,105-123

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:85

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	175
nb uops	169
loop length	700
used w registers	7
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	2
used z registers	16
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.13 cycles
front end	21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	5.50	5.50	18.00	18.00	40.00	18.00	6.50	6.50	1.50	1.50	16.83	16.50	16.67	5.50	5.50
cycles	5.50	5.50	18.00	18.00	40.00	18.00	6.50	6.50	1.50	1.50	16.83	16.50	16.67	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.13
Dispatch	40.00
Overall L1	40.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Vector efficiency ratios

all	29%
load	22%
store	32%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	31%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 40.00 cycles. At this rate:

0% of peak load performance is reached (0.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.07 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42f040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W9, #1, #8, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LT 42f114 <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SBFM X24, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X23, XZR, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X22, XZR, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d08c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1304	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MADD X25, X24, X8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STR XZR, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X29, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, SP, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STUR X25, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDUR X8, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X5, [X29, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X4, X8, X25, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X5, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X4, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.LE 42f118 <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xd8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X0, <47d0ec>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #1328	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X20, X19, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X25, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X24, X23, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X14, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X11, X12, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDRSW X8, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X10, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X10, X10, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR W1, [X15, X8,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [X12, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X13, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X14, [X14, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X17, #600]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X11, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X16, [X17, #632]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X17, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X21, [X17, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X0, [X17, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X6, [X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X2, [X17, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X17, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X17, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X20, [X17, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X12, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X13, X13, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X14, X14, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42f4ec <_Z14generate_chunkiR16global_variables.omp_outlined.1+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 42f334 <_Z14generate_chunkiR16global_variables.omp_outlined.1+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.NE 42f0ec <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z2.D, X5, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
SUB X17, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z7.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
DUP Z16.D, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V17.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ADD X22, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR Z22.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUBS X1, X22, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CSEL X1, XZR, X1, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z0.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z1.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z3.D, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z4.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z5.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X4, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z18.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z19.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z21.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P1.D, XZR, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
HINT #0																			N/A
HINT #0																			N/A
B 42f0ec <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z2.D, X5, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
LDR X1, [X29, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X4, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X15, [X17, #536]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X17, [X17, #568]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X22, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z7.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
DUP Z16.D, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V17.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
LDR X1, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X16, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUBS X4, X22, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X4, XZR, X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z0.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z1.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X5, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR Z22.D, Z2.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z4.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z5.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z18.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z19.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z21.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P1.D, XZR, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 42f0ec <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
INDEX Z0.D, X5, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
LDP X22, X1, [X29, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
SUB X4, X4, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z6.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
ADD X23, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUPM Z16.D, #0x100000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z17.D, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
MOVI V18.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
SUBS X4, X23, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X4, XZR, X4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z1.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDR X5, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X22, [X22, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z2.D, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X1, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR Z23.D, Z0.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z4.D, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z5.D, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z7.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X5, X5, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X6, X22, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z19.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z21.D, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z22.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
WHILELO P1.D, XZR, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
B 42f0ec <_Z14generate_chunkiR16global_variables.omp_outlined.1+0xac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone .omp_outlined.1]–	0.03	0.05
○Loop 206 - generate_chunk.cpp:86-98 - exec	0.03	0.04
○Loop 208 - generate_chunk.cpp:86-123 - exec	0.00	0.00
○Loop 207 - generate_chunk.cpp:86-112 - exec	0.00	0.00

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ASM code

Code clean check

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Vectorization

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CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code