OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage (incl. loops): 7.82% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 69 - 83

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69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x433de0 STP	D15, D14, [SP, #880]!

0x433de4 STP	D13, D12, [SP, #16]

0x433de8 STP	D11, D10, [SP, #32]

0x433dec STP	D9, D8, [SP, #48]

0x433df0 STP	X29, X30, [SP, #64]

0x433df4 STP	X28, X25, [SP, #80]

0x433df8 STP	X24, X23, [SP, #96]

0x433dfc STP	X22, X21, [SP, #112]

0x433e00 STP	X20, X19, [SP, #128]

0x433e04 ADD	X29, SP, #64

0x433e08 SUB	SP, SP, #48

0x433e0c ADDVL	SP, SP, #51

0x433e10 LDR	W8, [X2]

0x433e14 LDR	W9, [X4]

0x433e18 ADD	W22, W8, #1

0x433e1c LDR	W8, [X3]

0x433e20 ADD	W23, W9, #1

0x433e24 LDR	W9, [X5]

0x433e28 ADD	W8, W8, #2

0x433e2c ADD	W9, W9, #2

0x433e30 SUBS	W8, W8, W22

0x433e34 CCMP	W9, W23, #4, #12

0x433e38 B.LE	43428c

0x433e3c LDR	W19, [X0]

0x433e40 SUB	W24, W9, W23

0x433e44 MOVN	X9, #0

0x433e48 ORR	X20, XZR, X7

0x433e4c ORR	X21, XZR, X6

0x433e50 ADRP	X0,

0x433e54 ADD	X0, X0, #2472

0x433e58 ORR	W1, WZR, W19

0x433e5c UMADDL	X25, W24, W8, X9

0x433e60 MOVZ	W8, #1

0x433e64 ADD	X3, SP, #20

0x433e68 ADD	X4, SP, #40

0x433e6c ADD	X5, SP, #32

0x433e70 ADD	X6, SP, #24

0x433e74 MOVZ	W2, #34

0x433e78 MOVZ	W7, #1

0x433e7c STP	X25, XZR, [SP, #32]

0x433e80 STR	X8, [SP, #24]

0x433e84 STR	WZR, [SP, #20]

0x433e88 STR	X8, [SP]

0x433e8c BL	410680

0x433e90 LDP	X8, X11, [SP, #32]

0x433e94 CMP	X8, X25

0x433e98 CSEL	X9, X8, X25, #11

0x433e9c CMP	X11, X9

0x433ea0 STR	X9, [SP, #32]

0x433ea4 B.GT	43427c

0x433ea8 DUP	Z0.D, X22

0x433eac SUB	X8, X29, #64

0x433eb0 ADD	W10, W23, #1

0x433eb4 LDR	X15, [X20, #16]

0x433eb8 SUB	X16, X29, #64

0x433ebc SUB	X9, X9, X11

0x433ec0 LDP	X12, X14, [X29, #160]

0x433ec4 PTRUE	P0.D, ALL

0x433ec8 LD1RD	{Z20.D}, P0/Z, [X20]

0x433ecc INDEX	Z29.D, X11, #1

0x433ed0 STR	Z0, [X8, #511, MUL VL]

0x433ed4 LD1RD	{Z10.D}, P0/Z, [X14]

0x433ed8 DUP	Z0.D, X23

0x433edc LDR	X14, [X14, #16]

0x433ee0 STR	Z0, [X8, #510, MUL VL]

0x433ee4 ADD	W8, W22, #1

0x433ee8 DUP	Z16.D, X15

0x433eec DUP	Z1.D, X24

0x433ef0 DUP	Z0.D, X8

0x433ef4 SUB	X8, X29, #64

0x433ef8 STR	Z0, [X8, #509, MUL VL]

0x433efc DUP	Z0.D, X10

0x433f00 LDP	X13, X10, [X29, #96]

0x433f04 LD1RD	{Z18.D}, P0/Z, [X13]

0x433f08 STR	Z0, [X8, #508, MUL VL]

0x433f0c LD1RD	{Z0.D}, P0/Z, [X21]

0x433f10 LDR	X13, [X13, #16]

0x433f14 LD1RD	{Z21.D}, P0/Z, [X10]

0x433f18 LDR	X10, [X10, #16]

0x433f1c DUP	Z23.D, X10

0x433f20 STR	Z0, [X8, #507, MUL VL]

0x433f24 LDR	X8, [X21, #16]

0x433f28 DUP	Z0.D, X13

0x433f2c SUB	X13, X29, #64

0x433f30 STR	Z0, [X13, #506, MUL VL]

0x433f34 DUP	Z7.D, X8

0x433f38 LDP	X15, X8, [X29, #80]

0x433f3c LD1RD	{Z28.D}, P0/Z, [X15]

0x433f40 LDR	X15, [X15, #16]

0x433f44 DUP	Z19.D, X15

0x433f48 LDP	X15, X13, [X29, #112]

0x433f4c LD1RD	{Z22.D}, P0/Z, [X15]

0x433f50 LDR	X15, [X15, #16]

0x433f54 LD1RD	{Z0.D}, P0/Z, [X13]

0x433f58 LDR	X13, [X13, #16]

0x433f5c DUP	Z24.D, X15

0x433f60 LDP	X10, X15, [X29, #128]

0x433f64 STR	Z0, [X16, #505, MUL VL]

0x433f68 LD1RD	{Z0.D}, P0/Z, [X10]

0x433f6c LDR	X10, [X10, #16]

0x433f70 STR	Z0, [X16, #504, MUL VL]

0x433f74 DUP	Z0.D, X13

0x433f78 ADD	X16, X9, #1

0x433f7c SUB	X9, X29, #64

0x433f80 LDP	X11, X13, [X29, #144]

0x433f84 STR	Z0, [X9, #503, MUL VL]

0x433f88 DUP	Z0.D, X10

0x433f8c SUB	X10, X29, #64

0x433f90 CNTD	X9, ALL

0x433f94 LD1RD	{Z9.D}, P0/Z, [X13]

0x433f98 LDR	X13, [X13, #16]

0x433f9c DUP	Z14.D, X9

0x433fa0 STR	Z0, [X10, #502, MUL VL]

0x433fa4 LD1RD	{Z0.D}, P0/Z, [X15]

0x433fa8 SUBS	X10, X16, X9

0x433fac LDR	X15, [X15, #16]

0x433fb0 CSEL	X10, XZR, X10, #3

0x433fb4 WHILELO	P1.D, XZR, X16

0x433fb8 SUB	X16, X29, #64

0x433fbc DUP	Z11.D, X15

0x433fc0 SUB	X15, XZR, X9

0x433fc4 STR	Z0, [X16, #501, MUL VL]

0x433fc8 LD1RD	{Z0.D}, P0/Z, [X11]

0x433fcc LDR	X11, [X11, #16]

0x433fd0 STR	Z0, [X16, #500, MUL VL]

0x433fd4 LD1RD	{Z0.D}, P0/Z, [X12]

0x433fd8 LDR	X12, [X12, #16]

0x433fdc STR	Z0, [X16, #499, MUL VL]

(254) 0x433fe0 DUP	Z0.D, #1

(254) 0x433fe4 SUB	X16, X29, #64

(254) 0x433fe8 ADD	X15, X15, X9

(254) 0x433fec LDR	Z2, [X16, #507, MUL VL]

(254) 0x433ff0 LDR	Z3, [X16, #509, MUL VL]

(254) 0x433ff4 LDR	Z30, [X16, #508, MUL VL]

(254) 0x433ff8 SEL	Z12.D, P1, Z1.D, Z0.D

(254) 0x433ffc LDR	Z0, [X16, #511, MUL VL]

(254) 0x434000 MOVPRFX	Z13, Z29

(254) 0x434004 SDIV	Z13.D, P0/M, Z13.D, Z12.D

(254) 0x434008 ADD	Z12.D, Z0.D, Z13.D

(254) 0x43400c MOVPRFX	Z0, Z29

(254) 0x434010 MLS	Z0.D, P0/M, Z13.D, Z1.D

(254) 0x434014 ADD	Z13.D, Z13.D, Z3.D

(254) 0x434018 ADD	Z29.D, Z29.D, Z14.D

(254) 0x43401c MOVPRFX	Z15, Z12

(254) 0x434020 SXTW	Z15.D, P0/M, Z12.D

(254) 0x434024 SXTW	Z13.D, P0/M, Z13.D

(254) 0x434028 MOVPRFX	Z5, Z2

(254) 0x43402c MUL	Z5.D, P0/M, Z5.D, Z15.D

(254) 0x434030 LDR	Z2, [X16, #510, MUL VL]

(254) 0x434034 MOVPRFX	Z6, Z20

(254) 0x434038 MUL	Z6.D, P0/M, Z6.D, Z15.D

(254) 0x43403c MOVPRFX	Z3, Z20

(254) 0x434040 MUL	Z3.D, P0/M, Z3.D, Z13.D

(254) 0x434044 MOVPRFX	Z17, Z28

(254) 0x434048 MUL	Z17.D, P0/M, Z17.D, Z15.D

(254) 0x43404c MOVPRFX	Z25, Z28

(254) 0x434050 MUL	Z25.D, P0/M, Z25.D, Z13.D

(254) 0x434054 ADD	Z12.D, Z2.D, Z0.D

(254) 0x434058 ADD	Z0.D, Z0.D, Z30.D

(254) 0x43405c ADR	Z4.D, [Z16, Z12.D,SXTW #3]

(254) 0x434060 ADR	Z26.D, [Z19, Z12.D,SXTW #3]

(254) 0x434064 ADR	Z31.D, [Z16, Z0.D,SXTW #3]

(254) 0x434068 ADR	Z30.D, [Z7, Z0.D,SXTW #3]

(254) 0x43406c ADR	Z8.D, [Z7, Z12.D,SXTW #3]

(254) 0x434070 ADR	Z2.D, [Z4, Z6.D,LSL #3]

(254) 0x434074 ADR	Z4.D, [Z4, Z3.D,LSL #3]

(254) 0x434078 ADR	Z27.D, [Z26, Z17.D,LSL #3]

(254) 0x43407c ADR	Z26.D, [Z26, Z25.D,LSL #3]

(254) 0x434080 ADR	Z6.D, [Z31, Z6.D,LSL #3]

(254) 0x434084 ADR	Z3.D, [Z31, Z3.D,LSL #3]

(254) 0x434088 ADR	Z30.D, [Z30, Z5.D,LSL #3]

(254) 0x43408c ADR	Z5.D, [Z8, Z5.D,LSL #3]

(254) 0x434090 LD1D	{Z2.D}, P1/Z, [V2.D]

(254) 0x434094 LD1D	{Z4.D}, P1/Z, [V4.D]

(254) 0x434098 LD1D	{Z27.D}, P1/Z, [V27.D]

(254) 0x43409c LD1D	{Z26.D}, P1/Z, [V26.D]

(254) 0x4340a0 LD1D	{Z6.D}, P1/Z, [V6.D]

(254) 0x4340a4 LD1D	{Z3.D}, P1/Z, [V3.D]

(254) 0x4340a8 LD1D	{Z30.D}, P1/Z, [V30.D]

(254) 0x4340ac LD1D	{Z5.D}, P1/Z, [V5.D]

(254) 0x4340b0 FADD	Z2.D, Z4.D, Z2.D

(254) 0x4340b4 FADD	Z4.D, Z27.D, Z26.D

(254) 0x4340b8 FADD	Z3.D, Z3.D, Z6.D

(254) 0x4340bc ADR	Z6.D, [Z23, Z12.D,SXTW #3]

(254) 0x4340c0 ADR	Z26.D, [Z24, Z12.D,SXTW #3]

(254) 0x4340c4 FADD	Z2.D, Z2.D, Z4.D

(254) 0x4340c8 ADR	Z4.D, [Z19, Z0.D,SXTW #3]

(254) 0x4340cc ADR	Z17.D, [Z4, Z17.D,LSL #3]

(254) 0x4340d0 ADR	Z4.D, [Z4, Z25.D,LSL #3]

(254) 0x4340d4 ADR	Z25.D, [Z23, Z0.D,SXTW #3]

(254) 0x4340d8 ADR	Z0.D, [Z24, Z0.D,SXTW #3]

(254) 0x4340dc FMUL	Z2.D, Z2.D, Z5.D

(254) 0x4340e0 LDR	D5, [X8]

(254) 0x4340e4 LD1D	{Z17.D}, P1/Z, [V17.D]

(254) 0x4340e8 LD1D	{Z4.D}, P1/Z, [V4.D]

(254) 0x4340ec FADD	Z4.D, Z17.D, Z4.D

(254) 0x4340f0 FADD	Z3.D, Z3.D, Z4.D

(254) 0x4340f4 MOVPRFX	Z4, Z21

(254) 0x4340f8 MUL	Z4.D, P0/M, Z4.D, Z15.D

(254) 0x4340fc FMUL	Z3.D, Z3.D, Z30.D

(254) 0x434100 MOVPRFX	Z30, Z18

(254) 0x434104 MUL	Z30.D, P0/M, Z30.D, Z15.D

(254) 0x434108 ADR	Z17.D, [Z6, Z4.D,LSL #3]

(254) 0x43410c ADR	Z4.D, [Z25, Z4.D,LSL #3]

(254) 0x434110 LD1D	{Z17.D}, P1/Z, [V17.D]

(254) 0x434114 LD1D	{Z4.D}, P1/Z, [V4.D]

(254) 0x434118 FADD	Z4.D, Z4.D, Z17.D

(254) 0x43411c MOVPRFX	Z17, Z22

(254) 0x434120 MUL	Z17.D, P0/M, Z17.D, Z15.D

(254) 0x434124 ADR	Z27.D, [Z26, Z17.D,LSL #3]

(254) 0x434128 ADR	Z17.D, [Z0, Z17.D,LSL #3]

(254) 0x43412c LD1D	{Z27.D}, P1/Z, [V27.D]

(254) 0x434130 LD1D	{Z17.D}, P1/Z, [V17.D]

(254) 0x434134 FADD	Z17.D, Z27.D, Z17.D

(254) 0x434138 MOVPRFX	Z27, Z21

(254) 0x43413c MUL	Z27.D, P0/M, Z27.D, Z13.D

(254) 0x434140 FADD	Z4.D, Z4.D, Z17.D

(254) 0x434144 LDR	Z17, [X16, #506, MUL VL]

(254) 0x434148 ADR	Z6.D, [Z6, Z27.D,LSL #3]

(254) 0x43414c ADR	Z25.D, [Z25, Z27.D,LSL #3]

(254) 0x434150 MOVPRFX	Z27, Z18

(254) 0x434154 MUL	Z27.D, P0/M, Z27.D, Z13.D

(254) 0x434158 ADR	Z17.D, [Z17, Z12.D,SXTW #3]

(254) 0x43415c LD1D	{Z6.D}, P1/Z, [V6.D]

(254) 0x434160 LD1D	{Z25.D}, P1/Z, [V25.D]

(254) 0x434164 MUL	Z13.D, P0/M, Z13.D, Z22.D

(254) 0x434168 ADR	Z0.D, [Z0, Z13.D,LSL #3]

(254) 0x43416c ADR	Z30.D, [Z17, Z30.D,LSL #3]

(254) 0x434170 ADR	Z17.D, [Z17, Z27.D,LSL #3]

(254) 0x434174 FADD	Z6.D, Z25.D, Z6.D

(254) 0x434178 ADR	Z25.D, [Z26, Z13.D,LSL #3]

(254) 0x43417c LD1D	{Z0.D}, P1/Z, [V0.D]

(254) 0x434180 LD1D	{Z17.D}, P1/Z, [V17.D]

(254) 0x434184 LD1D	{Z25.D}, P1/Z, [V25.D]

(254) 0x434188 FADD	Z0.D, Z25.D, Z0.D

(254) 0x43418c FADD	Z0.D, Z6.D, Z0.D

(254) 0x434190 FMAD	Z0.D, P0/M, Z17.D, Z3.D

(254) 0x434194 LDR	Z3, [X16, #503, MUL VL]

(254) 0x434198 LD1D	{Z6.D}, P1/Z, [V30.D]

(254) 0x43419c DUP	Z17.D, X11

(254) 0x4341a0 ADR	Z17.D, [Z17, Z12.D,SXTW #3]

(254) 0x4341a4 ADR	Z3.D, [Z3, Z12.D,SXTW #3]

(254) 0x4341a8 FMLA	Z2.D, P0/M, Z4.D, Z6.D

(254) 0x4341ac LDR	Z4, [X16, #502, MUL VL]

(254) 0x4341b0 LDR	Z6, [X16, #500, MUL VL]

(254) 0x4341b4 FSUB	Z0.D, Z0.D, Z2.D

(254) 0x4341b8 FMOV	D2, #0.2500000

(254) 0x4341bc FMUL	D2, D5, D2

(254) 0x4341c0 ADR	Z4.D, [Z4, Z12.D,SXTW #3]

(254) 0x4341c4 MUL	Z6.D, P0/M, Z6.D, Z15.D

(254) 0x4341c8 ADR	Z5.D, [Z11, Z12.D,SXTW #3]

(254) 0x4341cc DUP	Z2.D, Z2.D[0]

(254) 0x4341d0 FMUL	Z0.D, Z2.D, Z0.D

(254) 0x4341d4 LDR	Z2, [X16, #505, MUL VL]

(254) 0x4341d8 ADR	Z6.D, [Z17, Z6.D,LSL #3]

(254) 0x4341dc MUL	Z2.D, P0/M, Z2.D, Z15.D

(254) 0x4341e0 ADR	Z2.D, [Z3, Z2.D,LSL #3]

(254) 0x4341e4 LDR	Z3, [X16, #504, MUL VL]

(254) 0x4341e8 LD1D	{Z6.D}, P1/Z, [V6.D]

(254) 0x4341ec MUL	Z3.D, P0/M, Z3.D, Z15.D

(254) 0x4341f0 ADR	Z3.D, [Z4, Z3.D,LSL #3]

(254) 0x4341f4 LDR	Z4, [X16, #501, MUL VL]

(254) 0x4341f8 LD1D	{Z2.D}, P1/Z, [V2.D]

(254) 0x4341fc MUL	Z4.D, P0/M, Z4.D, Z15.D

(254) 0x434200 ADR	Z4.D, [Z5, Z4.D,LSL #3]

(254) 0x434204 LD1D	{Z3.D}, P1/Z, [V3.D]

(254) 0x434208 FADD	Z3.D, Z6.D, Z3.D

(254) 0x43420c DUP	Z6.D, X12

(254) 0x434210 FMUL	Z3.D, Z3.D, Z0.D

(254) 0x434214 FADD	Z0.D, Z0.D, Z2.D

(254) 0x434218 LD1D	{Z5.D}, P1/Z, [V4.D]

(254) 0x43421c ADR	Z6.D, [Z6, Z12.D,SXTW #3]

(254) 0x434220 FMUL	Z5.D, Z5.D, Z2.D

(254) 0x434224 FDIV	Z3.D, P0/M, Z3.D, Z5.D

(254) 0x434228 LDR	Z5, [X16, #499, MUL VL]

(254) 0x43422c MUL	Z5.D, P0/M, Z5.D, Z15.D

(254) 0x434230 ADR	Z5.D, [Z6, Z5.D,LSL #3]

(254) 0x434234 DUP	Z6.D, X13

(254) 0x434238 LD1D	{Z5.D}, P1/Z, [V5.D]

(254) 0x43423c ADR	Z6.D, [Z6, Z12.D,SXTW #3]

(254) 0x434240 FSUB	Z3.D, Z5.D, Z3.D

(254) 0x434244 MOVPRFX	Z5, Z9

(254) 0x434248 MUL	Z5.D, P0/M, Z5.D, Z15.D

(254) 0x43424c MUL	Z15.D, P0/M, Z15.D, Z10.D

(254) 0x434250 ADR	Z5.D, [Z6, Z5.D,LSL #3]

(254) 0x434254 ST1D	{Z3.D}, P1, [V5.D]

(254) 0x434258 LD1D	{Z3.D}, P1/Z, [V4.D]

(254) 0x43425c FMUL	Z2.D, Z3.D, Z2.D

(254) 0x434260 FDIVR	Z0.D, P0/M, Z0.D, Z2.D

(254) 0x434264 DUP	Z2.D, X14

(254) 0x434268 ADR	Z2.D, [Z2, Z12.D,SXTW #3]

(254) 0x43426c ADR	Z2.D, [Z2, Z15.D,LSL #3]

(254) 0x434270 ST1D	{Z0.D}, P1, [V2.D]

(254) 0x434274 WHILELO	P1.D, X15, X10

(254) 0x434278 B.MI	433fe0

0x43427c ADRP	X0,

0x434280 ADD	X0, X0, #2496

0x434284 ORR	W1, WZR, W19

0x434288 BL	4105b0

0x43428c ADDVL	SP, SP, #13

0x434290 ADD	SP, SP, #48

0x434294 LDP	D9, D8, [SP, #48]

0x434298 LDP	D11, D10, [SP, #32]

0x43429c LDP	D13, D12, [SP, #16]

0x4342a0 LDP	X20, X19, [SP, #128]

0x4342a4 LDP	X22, X21, [SP, #112]

0x4342a8 LDP	X24, X23, [SP, #96]

0x4342ac LDP	X28, X25, [SP, #80]

0x4342b0 LDP	X29, X30, [SP, #64]

0x4342b4 LDP	D15, D14, [SP], #144

0x4342b8 RET

0x4342bc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.56+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.44+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	PdV(global_variables&, bool)	PdV.cpp:99	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 24.67 to 18.00 cycles (1.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 43% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 24.67 to 17.46 cycles (1.41x speedup).

Details

28% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU loads are used in vector version.
62% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 419 bytes.

General properties

nb instructions	145
nb uops	144
loop length	580
used w registers	11
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	17
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	15.75	15.75	21.00	15.50	4.50	4.50	4.50	4.50	24.67	24.67	24.67	5.00	5.00
cycles	2.50	2.50	15.75	15.75	21.00	15.50	4.50	4.50	4.50	4.50	24.67	24.67	24.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.00
Dispatch	24.67
Overall L1	24.67

Vectorization ratios

all	28%
load	20%
store	62%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	43%
load	31%
store	69%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	15%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.67 cycles. At this rate:

0% of peak load performance is reached (0.61 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.99 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 433de0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #51	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W23, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 43428c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.1+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W24, W9, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47de50>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UMADDL X25, W24, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X25, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X8, X25, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 43427c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.1+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X12, X14, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1RD {Z20.D}, P0/Z, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
INDEX Z29.D, X11, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
STR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z10.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z0.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDR X14, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR Z0, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD W8, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z16.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z1.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z0.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDP X13, X10, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LD1RD {Z18.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
STR Z0, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P0/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X13, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LD1RD {Z21.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X10, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z23.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X8, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X8, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z0.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X13, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X13, #506, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDP X15, X8, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LD1RD {Z28.D}, P0/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X15, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z19.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDP X15, X13, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LD1RD {Z22.D}, P0/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X15, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LD1RD {Z0.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X13, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z24.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDP X10, X15, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR Z0, [X16, #505, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X10, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR Z0, [X16, #504, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X16, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X11, X13, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR Z0, [X9, #503, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X10, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1RD {Z9.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X13, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z14.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X10, #502, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P0/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUBS X10, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDR X15, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CSEL X10, XZR, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P1.D, XZR, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X16, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z11.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X15, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X16, #501, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P0/Z, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X11, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR Z0, [X16, #500, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X12, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR Z0, [X16, #499, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADRP X0, <47d27c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

28% of VPU instructions are used in vector version (process two or more data elements in vector registers):

20% of VPU loads are used in vector version.
62% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 419 bytes.

General properties

nb instructions	145
nb uops	144
loop length	580
used w registers	11
used x registers	27
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	17
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.00 cycles
front end	18.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	15.75	15.75	21.00	15.50	4.50	4.50	4.50	4.50	24.67	24.67	24.67	5.00	5.00
cycles	2.50	2.50	15.75	15.75	21.00	15.50	4.50	4.50	4.50	4.50	24.67	24.67	24.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	18.00
Dispatch	24.67
Overall L1	24.67

Vectorization ratios

all	28%
load	20%
store	62%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	43%
load	31%
store	69%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	15%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 24.67 cycles. At this rate:

0% of peak load performance is reached (0.61 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
35% of peak store performance is reached (16.99 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 433de0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #51	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W22, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W23, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 43428c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.1+0x4ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W24, W9, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47de50>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2472	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UMADDL X25, W24, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X25, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CMP X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X8, X25, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 43427c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.1+0x49c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP Z0.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD W10, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X15, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X16, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X12, X14, [X29, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LD1RD {Z20.D}, P0/Z, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
INDEX Z29.D, X11, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
STR Z0, [X8, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z10.D}, P0/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
DUP Z0.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDR X14, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR Z0, [X8, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD W8, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z16.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z1.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z0.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X8, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X8, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDP X13, X10, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LD1RD {Z18.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
STR Z0, [X8, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P0/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X13, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LD1RD {Z21.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X10, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z23.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X8, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X8, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z0.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X13, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X13, #506, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDP X15, X8, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LD1RD {Z28.D}, P0/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X15, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z19.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDP X15, X13, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LD1RD {Z22.D}, P0/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X15, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LD1RD {Z0.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X13, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z24.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDP X10, X15, [X29, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR Z0, [X16, #505, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X10, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR Z0, [X16, #504, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD X16, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X9, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP X11, X13, [X29, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
STR Z0, [X9, #503, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z0.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X10, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CNTD X9, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LD1RD {Z9.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X13, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP Z14.D, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z0, [X10, #502, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P0/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUBS X10, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
LDR X15, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CSEL X10, XZR, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
WHILELO P1.D, XZR, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X16, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z11.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X15, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR Z0, [X16, #501, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P0/Z, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X11, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR Z0, [X16, #500, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z0.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X12, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR Z0, [X16, #499, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADRP X0, <47d27c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2496	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	7.82	10.89
○Loop 254 - PdV.cpp:70-83 - exec	7.82	10.63

Report Configuration

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Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code