OV - exec - Function viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, ...	Module: exec	Source: viscosity.cpp:36-64 [...]	Coverage (incl. loops): 3.25% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp: 36 - 64

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

0x448080 STP	D15, D14, [SP, #864]!

0x448084 STP	D13, D12, [SP, #16]

0x448088 STP	D11, D10, [SP, #32]

0x44808c STP	D9, D8, [SP, #48]

0x448090 STP	X29, X30, [SP, #64]

0x448094 STP	X28, X27, [SP, #80]

0x448098 STP	X26, X25, [SP, #96]

0x44809c STP	X24, X23, [SP, #112]

0x4480a0 STP	X22, X21, [SP, #128]

0x4480a4 STP	X20, X19, [SP, #144]

0x4480a8 ADD	X29, SP, #64

0x4480ac SUB	SP, SP, #48

0x4480b0 ADDVL	SP, SP, #58

0x4480b4 LDR	W23, [X2]

0x4480b8 LDR	W8, [X3]

0x4480bc LDR	W25, [X4]

0x4480c0 ADD	W22, W23, #1

0x4480c4 LDR	W9, [X5]

0x4480c8 ADD	W8, W8, #2

0x4480cc ADD	W24, W25, #1

0x4480d0 ADD	W9, W9, #2

0x4480d4 SUBS	W8, W8, W22

0x4480d8 CCMP	W9, W24, #4, #12

0x4480dc B.LE	448494

0x4480e0 LDR	W19, [X0]

0x4480e4 SUB	W26, W9, W24

0x4480e8 MOVN	X9, #0

0x4480ec ORR	X20, XZR, X7

0x4480f0 ORR	X21, XZR, X6

0x4480f4 ADRP	X0,

0x4480f8 ADD	X0, X0, #3208

0x4480fc ORR	W1, WZR, W19

0x448100 UMADDL	X27, W26, W8, X9

0x448104 MOVZ	W8, #1

0x448108 ADD	X3, SP, #20

0x44810c ADD	X4, SP, #40

0x448110 ADD	X5, SP, #32

0x448114 ADD	X6, SP, #24

0x448118 MOVZ	W2, #34

0x44811c MOVZ	W7, #1

0x448120 STP	X27, XZR, [SP, #32]

0x448124 STR	X8, [SP, #24]

0x448128 STR	WZR, [SP, #20]

0x44812c STR	X8, [SP]

0x448130 BL	410680

0x448134 LDP	X8, X13, [SP, #32]

0x448138 CMP	X8, X27

0x44813c CSEL	X10, X8, X27, #11

0x448140 CMP	X13, X10

0x448144 STR	X10, [SP, #32]

0x448148 B.GT	448484

0x44814c LDP	X14, X12, [X29, #120]

0x448150 PTRUE	P1.D, ALL

0x448154 LDP	X11, X15, [X29, #104]

0x448158 CNTD	X8, ALL

0x44815c SUB	X10, X10, X13

0x448160 LDR	X9, [X29, #96]

0x448164 ADD	X18, X10, #1

0x448168 LDR	X16, [X21, #16]

0x44816c LDR	X17, [X20, #16]

0x448170 INDEX	Z29.D, X13, #1

0x448174 SUBS	X10, X18, X8

0x448178 LD1RD	{Z0.D}, P1/Z, [X21]

0x44817c LD1RD	{Z1.D}, P1/Z, [X20]

0x448180 CSEL	X10, XZR, X10, #3

0x448184 LD1RD	{Z4.D}, P1/Z, [X12]

0x448188 LDR	X0, [X12, #16]

0x44818c SUB	X12, X29, #64

0x448190 LDR	X1, [X14, #16]

0x448194 LD1RD	{Z3.D}, P1/Z, [X15]

0x448198 WHILELO	P0.D, XZR, X18

0x44819c LDR	X18, [X15, #16]

0x4481a0 LDR	X9, [X9, #8]

0x4481a4 LDR	X11, [X11, #8]

0x4481a8 STR	Z4, [X12, #511, MUL VL]

0x4481ac LD1RD	{Z4.D}, P1/Z, [X14]

0x4481b0 ADRP	X14,

0x4481b4 DUP	Z2.D, X26

0x4481b8 DUP	Z18.D, X8

0x4481bc DUP	Z22.D, X16

0x4481c0 DUP	Z23.D, X17

0x4481c4 DUP	Z24.D, X18

0x4481c8 LDR	D25, [X14, #2744]

0x4481cc DUP	Z27.D, X0

0x4481d0 STR	Z4, [X12, #510, MUL VL]

0x4481d4 DUP	Z4.D, X22

0x4481d8 DUP	Z28.D, X1

0x4481dc DUP	Z25.D, Z25.D[0]

0x4481e0 STR	Z4, [X12, #509, MUL VL]

0x4481e4 DUP	Z4.D, X24

0x4481e8 STR	Z4, [X12, #508, MUL VL]

0x4481ec DUP	Z4.D, X25

0x4481f0 STR	Z4, [X12, #507, MUL VL]

0x4481f4 DUP	Z4.D, X23

0x4481f8 STR	Z4, [X12, #506, MUL VL]

0x4481fc ADD	W12, W24, #1

0x448200 DUP	Z19.D, X12

0x448204 ADD	W12, W22, #1

0x448208 DUP	Z20.D, X12

0x44820c SUB	X12, XZR, X8

0x448210 HINT	#0

0x448214 HINT	#0

0x448218 HINT	#0

0x44821c HINT	#0

(700) 0x448220 DUP	Z4.D, #1

(700) 0x448224 SUB	X13, X29, #64

(700) 0x448228 ADD	X12, X12, X8

(700) 0x44822c SEL	Z30.D, P0, Z2.D, Z4.D

(700) 0x448230 LDR	Z4, [X13, #509, MUL VL]

(700) 0x448234 MOVPRFX	Z8, Z29

(700) 0x448238 SDIV	Z8.D, P1/M, Z8.D, Z30.D

(700) 0x44823c ADD	Z11.D, Z4.D, Z8.D

(700) 0x448240 MOVPRFX	Z15, Z29

(700) 0x448244 MLS	Z15.D, P1/M, Z8.D, Z2.D

(700) 0x448248 LDR	Z4, [X13, #508, MUL VL]

(700) 0x44824c ADD	Z29.D, Z29.D, Z18.D

(700) 0x448250 MOVPRFX	Z30, Z11

(700) 0x448254 SXTW	Z30.D, P1/M, Z11.D

(700) 0x448258 LD1D	{Z11.D}, P0/Z, [X11, Z11.D,SXTW #3]

(700) 0x44825c MOVPRFX	Z9, Z0

(700) 0x448260 MUL	Z9.D, P1/M, Z9.D, Z30.D

(700) 0x448264 ADD	Z10.D, Z15.D, Z19.D

(700) 0x448268 ADR	Z31.D, [Z22, Z10.D,SXTW #3]

(700) 0x44826c ADR	Z16.D, [Z23, Z10.D,SXTW #3]

(700) 0x448270 ADR	Z12.D, [Z31, Z9.D,LSL #3]

(700) 0x448274 LD1D	{Z21.D}, P0/Z, [V12.D]

(700) 0x448278 ADD	Z12.D, Z8.D, Z20.D

(700) 0x44827c MOVPRFX	Z14, Z12

(700) 0x448280 SXTW	Z14.D, P1/M, Z12.D

(700) 0x448284 MOVPRFX	Z12, Z0

(700) 0x448288 MUL	Z12.D, P1/M, Z12.D, Z14.D

(700) 0x44828c ADR	Z31.D, [Z31, Z12.D,LSL #3]

(700) 0x448290 LD1D	{Z26.D}, P0/Z, [V31.D]

(700) 0x448294 ADD	Z31.D, Z4.D, Z15.D

(700) 0x448298 ADR	Z13.D, [Z22, Z31.D,SXTW #3]

(700) 0x44829c ADR	Z5.D, [Z23, Z31.D,SXTW #3]

(700) 0x4482a0 ADR	Z9.D, [Z13, Z9.D,LSL #3]

(700) 0x4482a4 ADR	Z12.D, [Z13, Z12.D,LSL #3]

(700) 0x4482a8 LD1D	{Z9.D}, P0/Z, [V9.D]

(700) 0x4482ac LD1D	{Z4.D}, P0/Z, [V12.D]

(700) 0x4482b0 MOVPRFX	Z12, Z1

(700) 0x4482b4 MUL	Z12.D, P1/M, Z12.D, Z14.D

(700) 0x4482b8 MUL	Z14.D, P1/M, Z14.D, Z3.D

(700) 0x4482bc ADR	Z13.D, [Z5, Z12.D,LSL #3]

(700) 0x4482c0 ADR	Z12.D, [Z16, Z12.D,LSL #3]

(700) 0x4482c4 FADD	Z7.D, Z9.D, Z4.D

(700) 0x4482c8 LD1D	{Z6.D}, P0/Z, [V13.D]

(700) 0x4482cc FADD	Z13.D, Z26.D, Z21.D

(700) 0x4482d0 FSUB	Z13.D, Z13.D, Z7.D

(700) 0x4482d4 MOVPRFX	Z7, Z1

(700) 0x4482d8 MUL	Z7.D, P1/M, Z7.D, Z30.D

(700) 0x4482dc ADR	Z5.D, [Z5, Z7.D,LSL #3]

(700) 0x4482e0 ADR	Z7.D, [Z16, Z7.D,LSL #3]

(700) 0x4482e4 LD1D	{Z17.D}, P0/Z, [V12.D]

(700) 0x4482e8 FADD	Z16.D, Z17.D, Z6.D

(700) 0x4482ec LD1D	{Z5.D}, P0/Z, [V5.D]

(700) 0x4482f0 LD1D	{Z7.D}, P0/Z, [V7.D]

(700) 0x4482f4 FADD	Z12.D, Z5.D, Z7.D

(700) 0x4482f8 FADD	Z5.D, Z6.D, Z5.D

(700) 0x4482fc MOVPRFX	Z6, Z3

(700) 0x448300 MUL	Z6.D, P1/M, Z6.D, Z30.D

(700) 0x448304 FSUB	Z12.D, Z16.D, Z12.D

(700) 0x448308 FADD	Z16.D, Z21.D, Z9.D

(700) 0x44830c FSUB	Z5.D, Z17.D, Z5.D

(700) 0x448310 FSUB	Z16.D, Z26.D, Z16.D

(700) 0x448314 FADD	Z5.D, Z5.D, Z7.D

(700) 0x448318 LD1D	{Z9.D}, P0/Z, [X9, Z31.D,SXTW #3]

(700) 0x44831c ADR	Z7.D, [Z24, Z10.D,SXTW #3]

(700) 0x448320 FADD	Z4.D, Z16.D, Z4.D

(700) 0x448324 LDR	Z16, [X13, #507, MUL VL]

(700) 0x448328 FMUL	Z5.D, P1/M, Z5.D, #0.0000000

(700) 0x44832c ADR	Z7.D, [Z7, Z6.D,LSL #3]

(700) 0x448330 FMUL	Z4.D, P1/M, Z4.D, #0.0000000

(700) 0x448334 LD1D	{Z7.D}, P0/Z, [V7.D]

(700) 0x448338 FDIV	Z4.D, P1/M, Z4.D, Z11.D

(700) 0x44833c FDIV	Z5.D, P1/M, Z5.D, Z9.D

(700) 0x448340 ADD	Z16.D, Z16.D, Z15.D

(700) 0x448344 ADR	Z16.D, [Z24, Z16.D,SXTW #3]

(700) 0x448348 ADR	Z6.D, [Z16, Z6.D,LSL #3]

(700) 0x44834c LDR	Z16, [X13, #506, MUL VL]

(700) 0x448350 ADD	X13, X11, #16

(700) 0x448354 ADD	Z16.D, Z16.D, Z8.D

(700) 0x448358 SXTW	Z16.D, P1/M, Z16.D

(700) 0x44835c FADD	Z4.D, Z4.D, Z5.D

(700) 0x448360 LD1D	{Z6.D}, P0/Z, [V6.D]

(700) 0x448364 MUL	Z16.D, P1/M, Z16.D, Z3.D

(700) 0x448368 FSUB	Z5.D, Z7.D, Z6.D

(700) 0x44836c ADR	Z6.D, [Z24, Z31.D,SXTW #3]

(700) 0x448370 ADR	Z7.D, [Z6, Z14.D,LSL #3]

(700) 0x448374 ADR	Z6.D, [Z6, Z16.D,LSL #3]

(700) 0x448378 LD1D	{Z16.D}, P0/Z, [X9, Z10.D,SXTW #3]

(700) 0x44837c FADD	Z16.D, Z16.D, Z9.D

(700) 0x448380 FDIV	Z5.D, P1/M, Z5.D, Z16.D

(700) 0x448384 LSL	Z16.D, Z30.D, #3

(700) 0x448388 LD1D	{Z7.D}, P0/Z, [V7.D]

(700) 0x44838c FMUL	Z4.D, Z5.D, Z4.D

(700) 0x448390 FCMLT	P3.D, P1/Z, Z5.D, #0.0000000

(700) 0x448394 LD1D	{Z6.D}, P0/Z, [V6.D]

(700) 0x448398 LD1D	{Z16.D}, P0/Z, [X13, Z16.D]

(700) 0x44839c FSUB	Z6.D, Z7.D, Z6.D

(700) 0x4483a0 FADD	Z16.D, Z16.D, Z11.D

(700) 0x4483a4 FMUL	Z7.D, Z9.D, Z13.D

(700) 0x4483a8 FDIV	Z6.D, P1/M, Z6.D, Z16.D

(700) 0x4483ac FMUL	Z16.D, Z5.D, Z5.D

(700) 0x4483b0 FMUL	Z13.D, P1/M, Z13.D, #0.0000000

(700) 0x4483b4 FABS	Z5.D, P1/M, Z5.D

(700) 0x4483b8 FMLA	Z7.D, P1/M, Z11.D, Z12.D

(700) 0x4483bc FMUL	Z12.D, P1/M, Z12.D, #0.0000000

(700) 0x4483c0 FCMLT	P2.D, P1/Z, Z7.D, #0.0000000

(700) 0x4483c4 SUB	X13, X29, #64

(700) 0x4483c8 FMAXNM	Z5.D, P1/M, Z5.D, Z25.D

(700) 0x4483cc FMUL	Z17.D, Z13.D, Z16.D

(700) 0x4483d0 FNEG	Z5.D, P3/M, Z5.D

(700) 0x4483d4 FDIV	Z17.D, P1/M, Z17.D, Z9.D

(700) 0x4483d8 FCMLT	P3.D, P1/Z, Z5.D, #0.0000000

(700) 0x4483dc FMUL	Z7.D, Z5.D, Z5.D

(700) 0x4483e0 FMAD	Z4.D, P1/M, Z6.D, Z17.D

(700) 0x4483e4 FMUL	Z17.D, Z6.D, Z6.D

(700) 0x4483e8 FABS	Z6.D, P1/M, Z6.D

(700) 0x4483ec FMAXNM	Z6.D, P1/M, Z6.D, Z25.D

(700) 0x4483f0 FMUL	Z21.D, Z12.D, Z17.D

(700) 0x4483f4 FADD	Z16.D, Z17.D, Z16.D

(700) 0x4483f8 FNEG	Z6.D, P3/M, Z6.D

(700) 0x4483fc FMAXNM	Z16.D, P1/M, Z16.D, Z25.D

(700) 0x448400 FMLA	Z7.D, P1/M, Z6.D, Z6.D

(700) 0x448404 FDIV	Z21.D, P1/M, Z21.D, Z11.D

(700) 0x448408 FSQRT	Z7.D, P1/M, Z7.D

(700) 0x44840c FADD	Z4.D, Z4.D, Z21.D

(700) 0x448410 FDIV	Z4.D, P1/M, Z4.D, Z16.D

(700) 0x448414 FMUL	Z16.D, Z7.D, Z9.D

(700) 0x448418 FMUL	Z7.D, Z7.D, Z11.D

(700) 0x44841c FDIVR	Z5.D, P1/M, Z5.D, Z16.D

(700) 0x448420 FDIVR	Z6.D, P1/M, Z6.D, Z7.D

(700) 0x448424 LDR	Z7, [X13, #511, MUL VL]

(700) 0x448428 ADR	Z16.D, [Z27, Z31.D,SXTW #3]

(700) 0x44842c MUL	Z7.D, P1/M, Z7.D, Z30.D

(700) 0x448430 FCMLE	P3.D, P1/Z, Z4.D, #0.0000000

(700) 0x448434 ADR	Z7.D, [Z16, Z7.D,LSL #3]

(700) 0x448438 AND	P2.B, P3/Z, P3.B, P2.B

(700) 0x44843c AND	P3.B, P0/Z, P0.B, P2.B

(700) 0x448440 LD1D	{Z7.D}, P3/Z, [V7.D]

(700) 0x448444 FABS	Z5.D, P1/M, Z5.D

(700) 0x448448 FABS	Z6.D, P1/M, Z6.D

(700) 0x44844c FMINNM	Z5.D, P1/M, Z5.D, Z6.D

(700) 0x448450 MOVI	V6.2D, #0

(700) 0x448454 FMUL	Z4.D, Z5.D, Z4.D

(700) 0x448458 FMUL	Z4.D, Z4.D, Z4.D

(700) 0x44845c FADD	Z5.D, Z7.D, Z7.D

(700) 0x448460 FMUL	Z4.D, Z4.D, Z5.D

(700) 0x448464 LDR	Z5, [X13, #510, MUL VL]

(700) 0x448468 SEL	Z4.D, P2, Z4.D, Z6.D

(700) 0x44846c MUL	Z30.D, P1/M, Z30.D, Z5.D

(700) 0x448470 ADR	Z5.D, [Z28, Z31.D,SXTW #3]

(700) 0x448474 ADR	Z5.D, [Z5, Z30.D,LSL #3]

(700) 0x448478 ST1D	{Z4.D}, P0, [V5.D]

(700) 0x44847c WHILELO	P0.D, X12, X10

(700) 0x448480 B.MI	448220

0x448484 ADRP	X0,

0x448488 ADD	X0, X0, #3232

0x44848c ORR	W1, WZR, W19

0x448490 BL	4105b0

0x448494 ADDVL	SP, SP, #6

0x448498 ADD	SP, SP, #48

0x44849c LDP	D9, D8, [SP, #48]

0x4484a0 LDP	D11, D10, [SP, #32]

0x4484a4 LDP	D13, D12, [SP, #16]

0x4484a8 LDP	X20, X19, [SP, #144]

0x4484ac LDP	X22, X21, [SP, #128]

0x4484b0 LDP	X24, X23, [SP, #112]

0x4484b4 LDP	X26, X25, [SP, #96]

0x4484b8 LDP	X28, X27, [SP, #80]

0x4484bc LDP	X29, X30, [SP, #64]

0x4484c0 LDP	D15, D14, [SP], #160

0x4484c4 RET

0x4484c8 HINT	#0

0x4484cc HINT	#0

Coverage (%)	Name	Source Location	Module
►98.41+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.59+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	viscosity(global_variables&)	viscosity.cpp:76	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:64	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.00 to 16.00 cycles (1.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 36% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 19.00 to 9.81 cycles (1.94x speedup).

Details

19% of VPU instructions are used in vector version (process two or more data elements in vector registers):

18% of VPU loads are used in vector version.
47% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 195 bytes.

General properties

nb instructions	123
nb uops	117
loop length	492
used w registers	13
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	9
used q registers	0
used v registers	0
used z registers	15
nb stack references	26

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.63 cycles
front end	14.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	14.00	14.00	19.00	14.00	3.00	3.00	3.00	3.00	17.67	17.67	17.67	5.50	5.50
cycles	2.50	2.50	14.00	14.00	19.00	14.00	3.00	3.00	3.00	3.00	17.67	17.67	17.67	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.63
Dispatch	19.00
Overall L1	19.00

Vectorization ratios

all	19%
load	18%
store	47%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

all	36%
load	31%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.00 cycles. At this rate:

0% of peak load performance is reached (0.79 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.26 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 448080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #58	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W25, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W22, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W24, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W9, W24, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 448494 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W26, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47f0f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UMADDL X27, W26, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X27, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X10, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X13, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 448484 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x404>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X12, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDP X11, X15, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X10, X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
INDEX Z29.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
SUBS X10, X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LD1RD {Z0.D}, P1/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z1.D}, P1/Z, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CSEL X10, XZR, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LD1RD {Z4.D}, P1/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X0, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LD1RD {Z3.D}, P1/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
WHILELO P0.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LDR X18, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR Z4, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z4.D}, P1/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
ADRP X14, <4511b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z2.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z18.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z22.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z23.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z24.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDR D25, [X14, #2744]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
DUP Z27.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z4, [X12, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z28.D, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z25.D, Z25.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z4, [X12, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z4, [X12, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z4, [X12, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z4, [X12, #506, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD W12, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z19.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD W12, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z20.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X12, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <47f484>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

19% of VPU instructions are used in vector version (process two or more data elements in vector registers):

18% of VPU loads are used in vector version.
47% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 195 bytes.

General properties

nb instructions	123
nb uops	117
loop length	492
used w registers	13
used x registers	32
used b registers	0
used h registers	0
used s registers	1
used d registers	9
used q registers	0
used v registers	0
used z registers	15
nb stack references	26

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	14.63 cycles
front end	14.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	14.00	14.00	19.00	14.00	3.00	3.00	3.00	3.00	17.67	17.67	17.67	5.50	5.50
cycles	2.50	2.50	14.00	14.00	19.00	14.00	3.00	3.00	3.00	3.00	17.67	17.67	17.67	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	14.63
Dispatch	19.00
Overall L1	19.00

Vectorization ratios

all	19%
load	18%
store	47%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

all	36%
load	31%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	28%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 19.00 cycles. At this rate:

0% of peak load performance is reached (0.79 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.26 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 448080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP D15, D14, [SP, #864]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADDVL SP, SP, #58	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W25, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W22, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W24, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUBS W8, W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W9, W24, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 448494 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W26, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47f0f4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3208	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UMADDL X27, W26, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X27, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X13, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X10, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X13, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 448484 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_.omp_outlined+0x404>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X14, X12, [X29, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
PTRUE P1.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDP X11, X15, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X10, X10, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X9, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X18, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X16, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
INDEX Z29.D, X13, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
SUBS X10, X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LD1RD {Z0.D}, P1/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z1.D}, P1/Z, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CSEL X10, XZR, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LD1RD {Z4.D}, P1/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X0, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X1, [X14, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LD1RD {Z3.D}, P1/Z, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
WHILELO P0.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LDR X18, [X15, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X9, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X11, [X11, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR Z4, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LD1RD {Z4.D}, P1/Z, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
ADRP X14, <4511b0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z2.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z18.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z22.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z23.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z24.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LDR D25, [X14, #2744]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
DUP Z27.D, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z4, [X12, #510, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z28.D, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z25.D, Z25.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
STR Z4, [X12, #509, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z4, [X12, #508, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z4, [X12, #507, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
STR Z4, [X12, #506, MUL VL]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ADD W12, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z19.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADD W12, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z20.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X12, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <47f484>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3232	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADDVL SP, SP, #6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD SP, SP, #48	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X28, X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP D15, D14, [SP], #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]–	3.25	4.52
○Loop 700 - viscosity.cpp:37-64 - exec	3.25	4.41

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Matching between your function (in the source code) and the binary function

General properties

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Front-end bottlenecks

ASM code