OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:44-48 [...]	Coverage (incl. loops): 2.66% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:         post_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

48:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

0x4293d0 SUB	SP, SP, #144

0x4293d4 STR	D8, [SP, #48]

0x4293d8 STP	X29, X30, [SP, #56]

0x4293dc STR	X27, [SP, #72]

0x4293e0 STP	X26, X25, [SP, #80]

0x4293e4 STP	X24, X23, [SP, #96]

0x4293e8 STP	X22, X21, [SP, #112]

0x4293ec STP	X20, X19, [SP, #128]

0x4293f0 ADD	X29, SP, #56

0x4293f4 LDR	W8, [X3]

0x4293f8 LDR	W22, [X2]

0x4293fc LDR	W9, [X5]

0x429400 ADD	W8, W8, #4

0x429404 LDR	W23, [X4]

0x429408 ADD	W9, W9, #4

0x42940c CMP	W22, W8

0x429410 CCMP	W23, W9, #0, #13

0x429414 B.GT	4295f0

0x429418 SUB	W25, W22, #1

0x42941c SUB	W24, W23, #1

0x429420 LDR	W19, [X0]

0x429424 ORR	X21, XZR, X7

0x429428 ORR	X20, XZR, X6

0x42942c ADRP	X0,

0x429430 ADD	X0, X0, #3624

0x429434 ORR	W1, WZR, W19

0x429438 SUB	W26, W9, W24

0x42943c SUB	W8, W8, W25

0x429440 MOVN	X9, #0

0x429444 UMADDL	X27, W26, W8, X9

0x429448 MOVZ	W8, #1

0x42944c ADD	X3, SP, #20

0x429450 SUB	X4, X29, #16

0x429454 SUB	X5, X29, #24

0x429458 ADD	X6, SP, #24

0x42945c MOVZ	W2, #34

0x429460 MOVZ	W7, #1

0x429464 STP	X27, XZR, [X29, #1000]

0x429468 STR	X8, [SP, #24]

0x42946c STR	WZR, [SP, #20]

0x429470 STR	X8, [SP]

0x429474 BL	410680

0x429478 LDP	X8, X11, [X29, #1000]

0x42947c CMP	X8, X27

0x429480 CSEL	X9, X8, X27, #11

0x429484 CMP	X11, X9

0x429488 STUR	X9, [X29, #488]

0x42948c B.GT	4295e0

0x429490 LDP	X12, X10, [X29, #96]

0x429494 LDR	X13, [X29, #88]

0x429498 CNTD	X8, ALL

0x42949c SUB	X9, X9, X11

0x4294a0 PTRUE	P0.D, ALL

0x4294a4 LDR	X14, [X21, #16]

0x4294a8 LDR	X16, [X20, #16]

0x4294ac ADD	X18, X9, #1

0x4294b0 DUP	Z19.D, #1

0x4294b4 SUBS	X9, X18, X8

0x4294b8 INDEX	Z25.D, X11, #1

0x4294bc LD1RD	{Z0.D}, P0/Z, [X21]

0x4294c0 LD1RD	{Z2.D}, P0/Z, [X20]

0x4294c4 CSEL	X9, XZR, X9, #3

0x4294c8 LDR	X15, [X13, #16]

0x4294cc LDR	X17, [X10, #16]

0x4294d0 WHILELO	P1.D, XZR, X18

0x4294d4 LDR	X18, [X12, #16]

0x4294d8 LD1RD	{Z1.D}, P0/Z, [X13]

0x4294dc LD1RD	{Z3.D}, P0/Z, [X10]

0x4294e0 LD1RD	{Z4.D}, P0/Z, [X12]

0x4294e4 SUB	X10, XZR, X8

0x4294e8 DUP	Z5.D, X26

0x4294ec DUP	Z6.D, X25

0x4294f0 DUP	Z7.D, X24

0x4294f4 DUP	Z16.D, X22

0x4294f8 DUP	Z17.D, X23

0x4294fc DUP	Z18.D, X8

0x429500 DUP	Z20.D, X14

0x429504 DUP	Z22.D, X16

0x429508 DUP	Z21.D, X15

0x42950c DUP	Z23.D, X17

0x429510 DUP	Z24.D, X18

0x429514 HINT	#0

0x429518 HINT	#0

0x42951c HINT	#0

(156) 0x429520 SEL	Z26.D, P1, Z5.D, Z19.D

(156) 0x429524 ADD	X10, X10, X8

(156) 0x429528 SDIVR	Z26.D, P0/M, Z26.D, Z25.D

(156) 0x42952c ADD	Z27.D, Z6.D, Z26.D

(156) 0x429530 MOVPRFX	Z28, Z25

(156) 0x429534 MLS	Z28.D, P0/M, Z26.D, Z5.D

(156) 0x429538 ADD	Z26.D, Z16.D, Z26.D

(156) 0x42953c ADD	Z25.D, Z25.D, Z18.D

(156) 0x429540 SXTW	Z27.D, P0/M, Z27.D

(156) 0x429544 SXTW	Z26.D, P0/M, Z26.D

(156) 0x429548 MOVPRFX	Z30, Z0

(156) 0x42954c MUL	Z30.D, P0/M, Z30.D, Z27.D

(156) 0x429550 MUL	Z26.D, P0/M, Z26.D, Z1.D

(156) 0x429554 MOVPRFX	Z8, Z1

(156) 0x429558 MUL	Z8.D, P0/M, Z8.D, Z27.D

(156) 0x42955c ADD	Z29.D, Z7.D, Z28.D

(156) 0x429560 ADD	Z28.D, Z17.D, Z28.D

(156) 0x429564 ADR	Z31.D, [Z20, Z29.D,SXTW #3]

(156) 0x429568 ADR	Z28.D, [Z23, Z28.D,SXTW #3]

(156) 0x42956c ADR	Z30.D, [Z31, Z30.D,LSL #3]

(156) 0x429570 ADR	Z31.D, [Z21, Z29.D,SXTW #3]

(156) 0x429574 ADR	Z26.D, [Z31, Z26.D,LSL #3]

(156) 0x429578 LD1D	{Z30.D}, P1/Z, [V30.D]

(156) 0x42957c LD1D	{Z26.D}, P1/Z, [V26.D]

(156) 0x429580 FADD	Z26.D, Z26.D, Z30.D

(156) 0x429584 ADR	Z30.D, [Z31, Z8.D,LSL #3]

(156) 0x429588 MOVPRFX	Z31, Z2

(156) 0x42958c MUL	Z31.D, P0/M, Z31.D, Z27.D

(156) 0x429590 LD1D	{Z30.D}, P1/Z, [V30.D]

(156) 0x429594 FSUB	Z26.D, Z26.D, Z30.D

(156) 0x429598 ADR	Z30.D, [Z22, Z29.D,SXTW #3]

(156) 0x42959c ADR	Z30.D, [Z30, Z31.D,LSL #3]

(156) 0x4295a0 ST1D	{Z26.D}, P1, [V30.D]

(156) 0x4295a4 MOVPRFX	Z30, Z3

(156) 0x4295a8 MUL	Z30.D, P0/M, Z30.D, Z27.D

(156) 0x4295ac MUL	Z27.D, P0/M, Z27.D, Z4.D

(156) 0x4295b0 ADR	Z28.D, [Z28, Z30.D,LSL #3]

(156) 0x4295b4 LD1D	{Z28.D}, P1/Z, [V28.D]

(156) 0x4295b8 FADD	Z26.D, Z28.D, Z26.D

(156) 0x4295bc ADR	Z28.D, [Z23, Z29.D,SXTW #3]

(156) 0x4295c0 ADR	Z28.D, [Z28, Z30.D,LSL #3]

(156) 0x4295c4 LD1D	{Z28.D}, P1/Z, [V28.D]

(156) 0x4295c8 FSUB	Z26.D, Z26.D, Z28.D

(156) 0x4295cc ADR	Z28.D, [Z24, Z29.D,SXTW #3]

(156) 0x4295d0 ADR	Z27.D, [Z28, Z27.D,LSL #3]

(156) 0x4295d4 ST1D	{Z26.D}, P1, [V27.D]

(156) 0x4295d8 WHILELO	P1.D, X10, X9

(156) 0x4295dc B.MI	429520

0x4295e0 ADRP	X0,

0x4295e4 ADD	X0, X0, #3648

0x4295e8 ORR	W1, WZR, W19

0x4295ec BL	4105b0

0x4295f0 LDR	D8, [SP, #48]

0x4295f4 LDP	X20, X19, [SP, #128]

0x4295f8 LDR	X27, [SP, #72]

0x4295fc LDP	X22, X21, [SP, #112]

0x429600 LDP	X24, X23, [SP, #96]

0x429604 LDP	X26, X25, [SP, #80]

0x429608 LDP	X29, X30, [SP, #56]

0x42960c ADD	SP, SP, #144

0x429610 RET

0x429614 HINT	#0

0x429618 HINT	#0

0x42961c HINT	#0

Coverage (%)	Name	Module
►98.44+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 12.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 25% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 15.00 to 6.87 cycles (2.18x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	100
nb uops	94
loop length	400
used w registers	12
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	18
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	12.50	12.25	15.00	12.25	1.50	1.50	0.00	0.00	12.50	12.17	12.33	5.50	5.50
cycles	2.50	2.50	12.50	12.25	15.00	12.25	1.50	1.50	0.00	0.00	12.50	12.17	12.33	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.75
Dispatch	15.00
Overall L1	15.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	17%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

1% of peak load performance is reached (1.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4293d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP X29, X30, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X27, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W8, W8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W9, W9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W22, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W23, W9, #0, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.GT 4295f0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W25, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47c42c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W26, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UMADDL X27, W26, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X27, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 4295e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X10, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X13, [X29, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X14, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z19.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
SUBS X9, X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
INDEX Z25.D, X11, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
LD1RD {Z0.D}, P0/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z2.D}, P0/Z, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CSEL X9, XZR, X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X15, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
WHILELO P1.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LDR X18, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LD1RD {Z1.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z3.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z4.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X10, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z5.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z7.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z16.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z17.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z18.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z22.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z21.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z23.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z24.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <47c5e0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3648	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X27, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	100
nb uops	94
loop length	400
used w registers	12
used x registers	30
used b registers	0
used h registers	0
used s registers	1
used d registers	1
used q registers	0
used v registers	0
used z registers	18
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.75 cycles
front end	11.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	12.50	12.25	15.00	12.25	1.50	1.50	0.00	0.00	12.50	12.17	12.33	5.50	5.50
cycles	2.50	2.50	12.50	12.25	15.00	12.25	1.50	1.50	0.00	0.00	12.50	12.17	12.33	5.50	5.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.75
Dispatch	15.00
Overall L1	15.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	25%
load	25%
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	17%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	24%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

1% of peak load performance is reached (1.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4293d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D8, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP X29, X30, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X27, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #56	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W8, W8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W9, W9, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W22, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W23, W9, #0, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.GT 4295f0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined+0x220>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W25, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47c42c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3624	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W26, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W8, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
UMADDL X27, W26, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X4, X29, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB X5, X29, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X27, XZR, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [X29, #1000]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X8, X27, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STUR X9, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 4295e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined+0x210>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X10, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X13, [X29, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
SUB X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
LDR X14, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X18, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z19.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
SUBS X9, X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
INDEX Z25.D, X11, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
LD1RD {Z0.D}, P0/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z2.D}, P0/Z, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
CSEL X9, XZR, X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR X15, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X10, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
WHILELO P1.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
LDR X18, [X12, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LD1RD {Z1.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z3.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z4.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUB X10, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z5.D, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z7.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z16.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z17.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z18.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z22.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z21.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z23.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z24.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <47c5e0>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #3648	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X27, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #144	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.66	3.70
○Loop 156 - advec_mom.cpp:45-48 - exec	2.66	3.62

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