OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:167-172 [...]	Coverage (incl. loops): 2.86% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 167 - 172

--------------------------------------------------------------------------------

167: #pragma omp parallel for simd collapse(2)

168:       for (int j = (y_min - 1 + 1); j < (y_max + 2 + 2); j++) {

169:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

170:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

171:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

172:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i + 0, j - 1) + node_flux(i, j);

0x42a760 SUB	SP, SP, #192

0x42a764 STP	D15, D14, [SP, #48]

0x42a768 STP	D13, D12, [SP, #64]

0x42a76c STP	D11, D10, [SP, #80]

0x42a770 STP	D9, D8, [SP, #96]

0x42a774 STP	X29, X30, [SP, #112]

0x42a778 STP	X26, X25, [SP, #128]

0x42a77c STP	X24, X23, [SP, #144]

0x42a780 STP	X22, X21, [SP, #160]

0x42a784 STP	X20, X19, [SP, #176]

0x42a788 ADD	X29, SP, #112

0x42a78c LDR	W8, [X3]

0x42a790 LDR	W22, [X2]

0x42a794 LDR	W23, [X4]

0x42a798 ADD	W8, W8, #4

0x42a79c LDR	W9, [X5]

0x42a7a0 ADD	W24, W23, #1

0x42a7a4 ADD	W9, W9, #3

0x42a7a8 SUBS	W8, W8, W22

0x42a7ac CCMP	W9, W24, #4, #12

0x42a7b0 B.LE	42a9c4

0x42a7b4 LDR	W19, [X0]

0x42a7b8 SUB	W25, W9, W24

0x42a7bc MOVN	X9, #0

0x42a7c0 ORR	X21, XZR, X7

0x42a7c4 ORR	X20, XZR, X6

0x42a7c8 ADRP	X0,

0x42a7cc ADD	X0, X0, #176

0x42a7d0 ORR	W1, WZR, W19

0x42a7d4 UMADDL	X26, W25, W8, X9

0x42a7d8 MOVZ	W8, #1

0x42a7dc ADD	X3, SP, #20

0x42a7e0 ADD	X4, SP, #40

0x42a7e4 ADD	X5, SP, #32

0x42a7e8 ADD	X6, SP, #24

0x42a7ec MOVZ	W2, #34

0x42a7f0 MOVZ	W7, #1

0x42a7f4 STP	X26, XZR, [SP, #32]

0x42a7f8 STR	X8, [SP, #24]

0x42a7fc STR	WZR, [SP, #20]

0x42a800 STR	X8, [SP]

0x42a804 BL	410680

0x42a808 LDP	X8, X11, [SP, #32]

0x42a80c CMP	X8, X26

0x42a810 CSEL	X9, X8, X26, #11

0x42a814 CMP	X11, X9

0x42a818 STR	X9, [SP, #32]

0x42a81c B.GT	42a9b4

0x42a820 LDP	X12, X10, [X29, #88]

0x42a824 LDR	X13, [X29, #80]

0x42a828 PTRUE	P0.D, ALL

0x42a82c INDEX	Z26.D, X11, #1

0x42a830 LDR	X14, [X21, #16]

0x42a834 LDR	X16, [X20, #16]

0x42a838 SUB	X9, X9, X11

0x42a83c ADD	X0, X9, #1

0x42a840 DUP	Z19.D, #1

0x42a844 FDUP	Z22.D, #80

0x42a848 LD1RD	{Z0.D}, P0/Z, [X21]

0x42a84c LD1RD	{Z2.D}, P0/Z, [X20]

0x42a850 LDR	X15, [X13, #16]

0x42a854 LDR	X17, [X10, #16]

0x42a858 LDR	X18, [X12, #16]

0x42a85c CNTD	X8, ALL

0x42a860 LD1RD	{Z1.D}, P0/Z, [X13]

0x42a864 LD1RD	{Z3.D}, P0/Z, [X10]

0x42a868 LD1RD	{Z4.D}, P0/Z, [X12]

0x42a86c SUBS	X9, X0, X8

0x42a870 SUB	W10, W22, #1

0x42a874 CSEL	X9, XZR, X9, #3

0x42a878 WHILELO	P1.D, XZR, X0

0x42a87c DUP	Z5.D, X25

0x42a880 DUP	Z6.D, X22

0x42a884 DUP	Z7.D, X24

0x42a888 DUP	Z16.D, X23

0x42a88c DUP	Z17.D, X8

0x42a890 DUP	Z20.D, X14

0x42a894 DUP	Z23.D, X16

0x42a898 DUP	Z18.D, X10

0x42a89c SUB	X10, XZR, X8

0x42a8a0 DUP	Z21.D, X15

0x42a8a4 DUP	Z24.D, X17

0x42a8a8 DUP	Z25.D, X18

(165) 0x42a8ac SEL	Z27.D, P1, Z5.D, Z19.D

(165) 0x42a8b0 ADD	X10, X10, X8

(165) 0x42a8b4 SDIVR	Z27.D, P0/M, Z27.D, Z26.D

(165) 0x42a8b8 ADD	Z28.D, Z6.D, Z27.D

(165) 0x42a8bc MOVPRFX	Z29, Z26

(165) 0x42a8c0 MLS	Z29.D, P0/M, Z27.D, Z5.D

(165) 0x42a8c4 ADD	Z27.D, Z27.D, Z18.D

(165) 0x42a8c8 ADD	Z26.D, Z26.D, Z17.D

(165) 0x42a8cc SXTW	Z27.D, P0/M, Z27.D

(165) 0x42a8d0 SXTW	Z28.D, P0/M, Z28.D

(165) 0x42a8d4 MOVPRFX	Z31, Z0

(165) 0x42a8d8 MUL	Z31.D, P0/M, Z31.D, Z27.D

(165) 0x42a8dc MOVPRFX	Z10, Z1

(165) 0x42a8e0 MUL	Z10.D, P0/M, Z10.D, Z27.D

(165) 0x42a8e4 MOVPRFX	Z13, Z0

(165) 0x42a8e8 MUL	Z13.D, P0/M, Z13.D, Z28.D

(165) 0x42a8ec MOVPRFX	Z14, Z1

(165) 0x42a8f0 MUL	Z14.D, P0/M, Z14.D, Z28.D

(165) 0x42a8f4 MUL	Z27.D, P0/M, Z27.D, Z3.D

(165) 0x42a8f8 ADD	Z30.D, Z7.D, Z29.D

(165) 0x42a8fc ADD	Z29.D, Z16.D, Z29.D

(165) 0x42a900 ADR	Z8.D, [Z20, Z30.D,SXTW #3]

(165) 0x42a904 ADR	Z11.D, [Z21, Z30.D,SXTW #3]

(165) 0x42a908 ADR	Z15.D, [Z20, Z29.D,SXTW #3]

(165) 0x42a90c ADR	Z29.D, [Z21, Z29.D,SXTW #3]

(165) 0x42a910 ADR	Z9.D, [Z8, Z31.D,LSL #3]

(165) 0x42a914 ADR	Z12.D, [Z11, Z10.D,LSL #3]

(165) 0x42a918 ADR	Z8.D, [Z8, Z13.D,LSL #3]

(165) 0x42a91c ADR	Z11.D, [Z11, Z14.D,LSL #3]

(165) 0x42a920 ADR	Z31.D, [Z15, Z31.D,LSL #3]

(165) 0x42a924 ADR	Z10.D, [Z29, Z10.D,LSL #3]

(165) 0x42a928 ADR	Z29.D, [Z29, Z14.D,LSL #3]

(165) 0x42a92c LD1D	{Z9.D}, P1/Z, [V9.D]

(165) 0x42a930 LD1D	{Z12.D}, P1/Z, [V12.D]

(165) 0x42a934 LD1D	{Z8.D}, P1/Z, [V8.D]

(165) 0x42a938 LD1D	{Z11.D}, P1/Z, [V11.D]

(165) 0x42a93c LD1D	{Z31.D}, P1/Z, [V31.D]

(165) 0x42a940 LD1D	{Z10.D}, P1/Z, [V10.D]

(165) 0x42a944 LD1D	{Z29.D}, P1/Z, [V29.D]

(165) 0x42a948 FMUL	Z9.D, Z12.D, Z9.D

(165) 0x42a94c FMAD	Z8.D, P0/M, Z11.D, Z9.D

(165) 0x42a950 FMAD	Z31.D, P0/M, Z10.D, Z8.D

(165) 0x42a954 ADR	Z8.D, [Z15, Z13.D,LSL #3]

(165) 0x42a958 LD1D	{Z8.D}, P1/Z, [V8.D]

(165) 0x42a95c FMAD	Z29.D, P0/M, Z8.D, Z31.D

(165) 0x42a960 MOVPRFX	Z31, Z2

(165) 0x42a964 MUL	Z31.D, P0/M, Z31.D, Z28.D

(165) 0x42a968 ADR	Z8.D, [Z23, Z30.D,SXTW #3]

(165) 0x42a96c FMUL	Z29.D, Z29.D, Z22.D

(165) 0x42a970 ADR	Z31.D, [Z8, Z31.D,LSL #3]

(165) 0x42a974 ST1D	{Z29.D}, P1, [V31.D]

(165) 0x42a978 ADR	Z31.D, [Z24, Z30.D,SXTW #3]

(165) 0x42a97c ADR	Z27.D, [Z31, Z27.D,LSL #3]

(165) 0x42a980 LD1D	{Z27.D}, P1/Z, [V27.D]

(165) 0x42a984 FSUB	Z27.D, Z29.D, Z27.D

(165) 0x42a988 MOVPRFX	Z29, Z3

(165) 0x42a98c MUL	Z29.D, P0/M, Z29.D, Z28.D

(165) 0x42a990 ADR	Z29.D, [Z31, Z29.D,LSL #3]

(165) 0x42a994 MUL	Z28.D, P0/M, Z28.D, Z4.D

(165) 0x42a998 LD1D	{Z29.D}, P1/Z, [V29.D]

(165) 0x42a99c FADD	Z27.D, Z27.D, Z29.D

(165) 0x42a9a0 ADR	Z29.D, [Z25, Z30.D,SXTW #3]

(165) 0x42a9a4 ADR	Z28.D, [Z29, Z28.D,LSL #3]

(165) 0x42a9a8 ST1D	{Z27.D}, P1, [V28.D]

(165) 0x42a9ac WHILELO	P1.D, X10, X9

(165) 0x42a9b0 B.MI	42a8ac

0x42a9b4 ADRP	X0,

0x42a9b8 ADD	X0, X0, #200

0x42a9bc ORR	W1, WZR, W19

0x42a9c0 BL	4105b0

0x42a9c4 LDP	D9, D8, [SP, #96]

0x42a9c8 LDP	D11, D10, [SP, #80]

0x42a9cc LDP	D13, D12, [SP, #64]

0x42a9d0 LDP	D15, D14, [SP, #48]

0x42a9d4 LDP	X20, X19, [SP, #176]

0x42a9d8 LDP	X22, X21, [SP, #160]

0x42a9dc LDP	X24, X23, [SP, #144]

0x42a9e0 LDP	X26, X25, [SP, #128]

0x42a9e4 LDP	X29, X30, [SP, #112]

0x42a9e8 ADD	SP, SP, #192

0x42a9ec RET

Coverage (%)	Name	Module
►98.36+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.00 to 12.00 cycles (1.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 15.00 to 7.25 cycles (2.07x speedup).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

18% of VPU loads are used in vector version.
28% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	98
nb uops	98
loop length	392
used w registers	12
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	19
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.25 cycles
front end	12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	12.00	12.00	15.00	12.00	3.50	3.50	0.00	0.00	13.83	13.50	13.67	5.00	5.00
cycles	2.50	2.50	12.00	12.00	15.00	12.00	3.50	3.50	0.00	0.00	13.83	13.50	13.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Dispatch	15.00
Overall L1	15.00

Vectorization ratios

INT

all	11%
load	18%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	11%
load	18%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	30%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	17%
fma	25%
other	24%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	28%
load	30%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	17%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

1% of peak load performance is reached (1.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42a760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP D15, D14, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W8, W8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W9, W24, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 42a9c4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.17+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W25, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d7c8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UMADDL X26, W25, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X26, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X8, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 42a9b4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.17+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X10, [X29, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X13, [X29, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
INDEX Z26.D, X11, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	N/A
LDR X14, [X21, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X20, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z19.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
FDUP Z22.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
LD1RD {Z0.D}, P0/Z, [X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z2.D}, P0/Z, [X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X15, [X13, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X10, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X12, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LD1RD {Z1.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z3.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z4.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUBS X9, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB W10, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X9, XZR, X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P1.D, XZR, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
DUP Z5.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z7.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z16.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z17.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z23.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z18.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X10, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z21.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z24.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z25.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADRP X0, <47d9b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D9, D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D15, D14, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

18% of VPU loads are used in vector version.
28% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	98
nb uops	98
loop length	392
used w registers	12
used x registers	29
used b registers	0
used h registers	0
used s registers	1
used d registers	8
used q registers	0
used v registers	0
used z registers	19
nb stack references	24

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.25 cycles
front end	12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	12.00	12.00	15.00	12.00	3.50	3.50	0.00	0.00	13.83	13.50	13.67	5.00	5.00
cycles	2.50	2.50	12.00	12.00	15.00	12.00	3.50	3.50	0.00	0.00	13.83	13.50	13.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Dispatch	15.00
Overall L1	15.00

Vectorization ratios

INT

all	11%
load	18%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	11%
load	18%
store	28%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	29%
load	30%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	17%
fma	25%
other	24%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	28%
load	30%
store	41%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	17%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 15.00 cycles. At this rate:

1% of peak load performance is reached (1.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42a760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
STP D15, D14, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D13, D12, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D11, D10, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #112	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W23, [X4]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W8, W8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W24, W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W9, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
CCMP W9, W24, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 42a9c4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.17+0x264>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W25, W9, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ORR X21, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47d7c8>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #176	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UMADDL X26, W25, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X26, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X11, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X9, X8, X26, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X11, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X9, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 42a9b4 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.17+0x254>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X12, X10, [X29, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X13, [X29, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
INDEX Z26.D, X11, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	N/A
LDR X14, [X21, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X16, [X20, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X0, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z19.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
FDUP Z22.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
LD1RD {Z0.D}, P0/Z, [X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z2.D}, P0/Z, [X20]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X15, [X13, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X10, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X18, [X12, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LD1RD {Z1.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z3.D}, P0/Z, [X10]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z4.D}, P0/Z, [X12]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
SUBS X9, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
SUB W10, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
CSEL X9, XZR, X9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P1.D, XZR, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
DUP Z5.D, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z7.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z16.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z17.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z23.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z18.D, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUB X10, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z21.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z24.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z25.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADRP X0, <47d9b4>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #200	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D9, D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D13, D12, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D15, D14, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP X20, X19, [SP, #176]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #160]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X26, X25, [SP, #128]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #192	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.86	3.98
○Loop 165 - advec_mom.cpp:168-172 - exec	2.86	3.89

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Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

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Cycles summary

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Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code