OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage (incl. loops): 3.87% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

0x42a9f0 SUB	SP, SP, #160

0x42a9f4 STR	D12, [SP, #48]

0x42a9f8 STP	D11, D10, [SP, #56]

0x42a9fc STP	D9, D8, [SP, #72]

0x42aa00 STP	X29, X30, [SP, #88]

0x42aa04 STR	X25, [SP, #104]

0x42aa08 STP	X24, X23, [SP, #112]

0x42aa0c STP	X22, X21, [SP, #128]

0x42aa10 STP	X20, X19, [SP, #144]

0x42aa14 ADD	X29, SP, #88

0x42aa18 LDR	W9, [X4]

0x42aa1c LDR	W8, [X3]

0x42aa20 LDR	W22, [X2]

0x42aa24 ADD	W23, W9, #1

0x42aa28 LDR	W9, [X5]

0x42aa2c ADD	W8, W8, #3

0x42aa30 SUBS	W8, W8, W22

0x42aa34 ADD	W9, W9, #3

0x42aa38 CCMP	W9, W23, #4, #12

0x42aa3c B.LE	42ac8c

0x42aa40 LDR	W19, [X0]

0x42aa44 SUB	W24, W9, W23

0x42aa48 MOVN	X9, #0

0x42aa4c ORR	X20, XZR, X7

0x42aa50 ORR	X21, XZR, X6

0x42aa54 ADRP	X0,

0x42aa58 ADD	X0, X0, #248

0x42aa5c ORR	W1, WZR, W19

0x42aa60 UMADDL	X25, W24, W8, X9

0x42aa64 MOVZ	W8, #1

0x42aa68 ADD	X3, SP, #20

0x42aa6c ADD	X4, SP, #40

0x42aa70 ADD	X5, SP, #32

0x42aa74 ADD	X6, SP, #24

0x42aa78 MOVZ	W2, #34

0x42aa7c MOVZ	W7, #1

0x42aa80 STP	X25, XZR, [SP, #32]

0x42aa84 STR	X8, [SP, #24]

0x42aa88 STR	WZR, [SP, #20]

0x42aa8c STR	X8, [SP]

0x42aa90 BL	410680

0x42aa94 LDP	X8, X12, [SP, #32]

0x42aa98 CMP	X8, X25

0x42aa9c CSEL	X10, X8, X25, #11

0x42aaa0 CMP	X12, X10

0x42aaa4 STR	X10, [SP, #32]

0x42aaa8 B.GT	42ac7c

0x42aaac LDP	X13, X11, [X29, #80]

0x42aab0 LDR	X9, [X29, #72]

0x42aab4 PTRUE	P0.D, ALL

0x42aab8 INDEX	Z25.D, X12, #1

0x42aabc LDR	X14, [X21, #16]

0x42aac0 LDR	X15, [X20, #16]

0x42aac4 SUB	X10, X10, X12

0x42aac8 ADD	X18, X10, #1

0x42aacc DUP	Z16.D, #1

0x42aad0 MOVI	V18.2D, #0

0x42aad4 DUPM	Z19.D, #0x0

0x42aad8 FDUP	Z22.D, #0

0x42aadc LD1RD	{Z0.D}, P0/Z, [X21]

0x42aae0 LD1RD	{Z1.D}, P0/Z, [X20]

0x42aae4 LDR	X16, [X13, #16]

0x42aae8 LDR	X17, [X11, #16]

0x42aaec CNTD	X8, ALL

0x42aaf0 LD1RD	{Z2.D}, P0/Z, [X13]

0x42aaf4 LD1RD	{Z3.D}, P0/Z, [X11]

0x42aaf8 ORR	X13, XZR, #0x55

0x42aafc LDR	X9, [X9, #8]

0x42ab00 SUBS	X10, X18, X8

0x42ab04 CSEL	X10, XZR, X10, #3

0x42ab08 WHILELO	P1.D, XZR, X18

0x42ab0c SUB	X11, XZR, X8

0x42ab10 MOVK	X13, #16325

0x42ab14 DUP	Z4.D, X24

0x42ab18 DUP	Z5.D, X22

0x42ab1c DUP	Z6.D, X23

0x42ab20 DUP	Z7.D, X8

0x42ab24 DUP	Z17.D, X14

0x42ab28 DUP	Z20.D, X15

0x42ab2c DUP	Z23.D, X13

0x42ab30 DUP	Z21.D, X16

0x42ab34 DUP	Z24.D, X17

0x42ab38 HINT	#0

0x42ab3c HINT	#0

(166) 0x42ab40 SEL	Z26.D, P1, Z4.D, Z16.D

(166) 0x42ab44 ADD	X11, X11, X8

(166) 0x42ab48 SDIVR	Z26.D, P0/M, Z26.D, Z25.D

(166) 0x42ab4c ADD	Z27.D, Z5.D, Z26.D

(166) 0x42ab50 MSB	Z26.D, P0/M, Z4.D, Z25.D

(166) 0x42ab54 ADD	Z25.D, Z25.D, Z7.D

(166) 0x42ab58 MOVPRFX	Z28, Z27

(166) 0x42ab5c SXTW	Z28.D, P0/M, Z27.D

(166) 0x42ab60 ORR	Z9.D, Z27.D, Z27.D

(166) 0x42ab64 ADD	Z8.D, Z27.D, Z19.D

(166) 0x42ab68 MOVPRFX	Z29, Z0

(166) 0x42ab6c MUL	Z29.D, P0/M, Z29.D, Z28.D

(166) 0x42ab70 ADD	Z9.D, Z9.D, #2

(166) 0x42ab74 ADD	Z26.D, Z6.D, Z26.D

(166) 0x42ab78 ADR	Z30.D, [Z17, Z26.D,SXTW #3]

(166) 0x42ab7c ADR	Z12.D, [Z20, Z26.D,SXTW #3]

(166) 0x42ab80 ADR	Z29.D, [Z30, Z29.D,LSL #3]

(166) 0x42ab84 ORR	Z30.D, Z27.D, Z27.D

(166) 0x42ab88 LD1D	{Z29.D}, P1/Z, [V29.D]

(166) 0x42ab8c ADD	Z30.D, Z30.D, #1

(166) 0x42ab90 MOVPRFX	Z31, Z30

(166) 0x42ab94 SXTW	Z31.D, P0/M, Z30.D

(166) 0x42ab98 FCMLT	P2.D, P0/Z, Z29.D, #0.0000000

(166) 0x42ab9c SEL	Z10.D, P2, Z28.D, Z31.D

(166) 0x42aba0 SEL	Z31.D, P2, Z31.D, Z28.D

(166) 0x42aba4 SEL	Z30.D, P2, Z30.D, Z8.D

(166) 0x42aba8 SEL	Z8.D, P2, Z9.D, Z8.D

(166) 0x42abac MOVPRFX	Z9, Z29

(166) 0x42abb0 FABS	Z9.D, P0/M, Z29.D

(166) 0x42abb4 MUL	Z28.D, P0/M, Z28.D, Z3.D

(166) 0x42abb8 MOVPRFX	Z11, Z1

(166) 0x42abbc MUL	Z11.D, P0/M, Z11.D, Z31.D

(166) 0x42abc0 SXTW	Z8.D, P0/M, Z8.D

(166) 0x42abc4 MUL	Z31.D, P0/M, Z31.D, Z2.D

(166) 0x42abc8 MUL	Z10.D, P0/M, Z10.D, Z2.D

(166) 0x42abcc MUL	Z8.D, P0/M, Z8.D, Z2.D

(166) 0x42abd0 ADR	Z11.D, [Z12, Z11.D,LSL #3]

(166) 0x42abd4 LD1D	{Z11.D}, P1/Z, [V11.D]

(166) 0x42abd8 FDIV	Z9.D, P0/M, Z9.D, Z11.D

(166) 0x42abdc ADR	Z11.D, [Z21, Z26.D,SXTW #3]

(166) 0x42abe0 ADR	Z26.D, [Z24, Z26.D,SXTW #3]

(166) 0x42abe4 ADR	Z31.D, [Z11, Z31.D,LSL #3]

(166) 0x42abe8 ADR	Z8.D, [Z11, Z8.D,LSL #3]

(166) 0x42abec ADR	Z10.D, [Z11, Z10.D,LSL #3]

(166) 0x42abf0 ADR	Z26.D, [Z26, Z28.D,LSL #3]

(166) 0x42abf4 LD1D	{Z31.D}, P1/Z, [V31.D]

(166) 0x42abf8 LD1D	{Z8.D}, P1/Z, [V8.D]

(166) 0x42abfc LD1D	{Z10.D}, P1/Z, [V10.D]

(166) 0x42ac00 FSUB	Z12.D, Z31.D, Z8.D

(166) 0x42ac04 FSUB	Z11.D, Z10.D, Z31.D

(166) 0x42ac08 FABD	Z8.D, P0/M, Z8.D, Z31.D

(166) 0x42ac0c FABD	Z10.D, P0/M, Z10.D, Z31.D

(166) 0x42ac10 FMUL	Z12.D, Z11.D, Z12.D

(166) 0x42ac14 FCMGT	P4.D, P0/Z, Z11.D, #0.0000000

(166) 0x42ac18 FSUB	Z11.D, Z22.D, Z9.D

(166) 0x42ac1c FMUL	Z11.D, Z10.D, Z11.D

(166) 0x42ac20 FCMGT	P2.D, P0/Z, Z12.D, #0.0000000

(166) 0x42ac24 MOVPRFX	Z12, Z8

(166) 0x42ac28 FMLA	Z12.D, P0/M, Z9.D, Z8.D

(166) 0x42ac2c FSUBR	Z9.D, P0/M, Z9.D, #0.0000000

(166) 0x42ac30 AND	P3.B, P1/Z, P1.B, P2.B

(166) 0x42ac34 LD1D	{Z27.D}, P3/Z, [X9, Z27.D,SXTW #3]

(166) 0x42ac38 LD1D	{Z30.D}, P3/Z, [X9, Z30.D,SXTW #3]

(166) 0x42ac3c FDIV	Z11.D, P0/M, Z11.D, Z27.D

(166) 0x42ac40 FDIVR	Z30.D, P0/M, Z30.D, Z12.D

(166) 0x42ac44 FMUL	Z27.D, Z27.D, Z23.D

(166) 0x42ac48 FADD	Z30.D, Z30.D, Z11.D

(166) 0x42ac4c FMUL	Z27.D, Z27.D, Z30.D

(166) 0x42ac50 FMINNM	Z27.D, P0/M, Z27.D, Z8.D

(166) 0x42ac54 FMINNM	Z27.D, P0/M, Z27.D, Z10.D

(166) 0x42ac58 MOVPRFX	Z30, Z27

(166) 0x42ac5c FNEG	Z30.D, P0/M, Z27.D

(166) 0x42ac60 SEL	Z27.D, P4, Z27.D, Z30.D

(166) 0x42ac64 SEL	Z27.D, P2, Z27.D, Z18.D

(166) 0x42ac68 FMAD	Z27.D, P0/M, Z9.D, Z31.D

(166) 0x42ac6c FMUL	Z27.D, Z27.D, Z29.D

(166) 0x42ac70 ST1D	{Z27.D}, P1, [V26.D]

(166) 0x42ac74 WHILELO	P1.D, X11, X10

(166) 0x42ac78 B.MI	42ab40

0x42ac7c ADRP	X0,

0x42ac80 ADD	X0, X0, #272

0x42ac84 ORR	W1, WZR, W19

0x42ac88 BL	4105b0

0x42ac8c LDP	D9, D8, [SP, #72]

0x42ac90 LDP	D11, D10, [SP, #56]

0x42ac94 LDR	D12, [SP, #48]

0x42ac98 LDR	X25, [SP, #104]

0x42ac9c LDP	X20, X19, [SP, #144]

0x42aca0 LDP	X22, X21, [SP, #128]

0x42aca4 LDP	X24, X23, [SP, #112]

0x42aca8 LDP	X29, X30, [SP, #88]

0x42acac ADD	SP, SP, #160

0x42acb0 RET

0x42acb4 HINT	#0

0x42acb8 HINT	#0

0x42acbc HINT	#0

Coverage (%)	Name	Module
►98.42+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 10.00 cycles (1.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 13.00 to 7.41 cycles (1.76x speedup).

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU loads are used in vector version.
15% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	101
nb uops	96
loop length	404
used w registers	10
used x registers	28
used b registers	0
used h registers	0
used s registers	1
used d registers	5
used q registers	0
used v registers	1
used z registers	17
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.00 cycles
front end	12.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	12.50	12.25	13.00	12.25	3.50	3.50	0.50	0.50	12.83	12.50	12.67	5.00	5.00
cycles	2.50	2.50	12.50	12.25	13.00	12.25	3.50	3.50	0.50	0.50	12.83	12.50	12.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.00
Dispatch	13.00
Overall L1	13.00

Vectorization ratios

INT

all	8%
load	11%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	4%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	11%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	28%
load	28%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	25%
other	27%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	28%
load	28%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

1% of peak load performance is reached (1.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.23 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42a9f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D12, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP D11, D10, [SP, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W23, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD W9, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 42ac8c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.19+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W24, W9, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47da54>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UMADDL X25, W24, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X25, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X12, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X10, X8, X25, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 42ac7c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.19+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X11, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X29, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
INDEX Z25.D, X12, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
LDR X14, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X10, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z16.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V18.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUPM Z19.D, #0x0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FDUP Z22.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
LD1RD {Z0.D}, P0/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z1.D}, P0/Z, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X16, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LD1RD {Z2.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z3.D}, P0/Z, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
ORR X13, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X10, X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X10, XZR, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P1.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X13, #16325	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z4.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z5.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z17.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z23.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z21.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z24.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <47dc7c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D9, D8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D12, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_1

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

11% of VPU loads are used in vector version.
15% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
4% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 15 bytes. The binary function is storing 3 bytes.

General properties

nb instructions	101
nb uops	96
loop length	404
used w registers	10
used x registers	28
used b registers	0
used h registers	0
used s registers	1
used d registers	5
used q registers	0
used v registers	1
used z registers	17
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.00 cycles
front end	12.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	12.50	12.25	13.00	12.25	3.50	3.50	0.50	0.50	12.83	12.50	12.67	5.00	5.00
cycles	2.50	2.50	12.50	12.25	13.00	12.25	3.50	3.50	0.50	0.50	12.83	12.50	12.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.00
Dispatch	13.00
Overall L1	13.00

Vectorization ratios

INT

all	8%
load	11%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	4%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	11%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	4%

Vector efficiency ratios

INT

all	28%
load	28%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	25%
other	27%

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	3%

INT+FP

all	28%
load	28%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.00 cycles. At this rate:

1% of peak load performance is reached (1.15 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.23 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42a9f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
SUB SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STR D12, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
STP D11, D10, [SP, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP D9, D8, [SP, #72]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (50.0%)
STP X29, X30, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #88	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR W9, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W8, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W22, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W23, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR W9, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W8, W8, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUBS W8, W8, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
ADD W9, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CCMP W9, W23, #4, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.LE 42ac8c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.19+0x29c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
SUB W24, W9, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MOVN X9, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X20, XZR, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X21, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <47da54>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #248	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
UMADDL X25, W24, W8, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
MOVZ W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X3, SP, #20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X4, SP, #40	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X5, SP, #32	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X6, SP, #24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MOVZ W2, #34	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X25, XZR, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X8, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR WZR, [SP, #20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 410680 <@plt_start@+0x660>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X12, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
CMP X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X10, X8, X25, #11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
CMP X12, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
STR X10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
B.GT 42ac7c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.19+0x28c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X13, X11, [X29, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDR X9, [X29, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
PTRUE P0.D, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (100.0%)
INDEX Z25.D, X12, #1	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	5	2	N/A
LDR X14, [X21, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X15, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB X10, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD X18, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
DUP Z16.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
MOVI V18.2D, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUPM Z19.D, #0x0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	vect (100.0%)
FDUP Z22.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.50	scal (3.1%)
LD1RD {Z0.D}, P0/Z, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z1.D}, P0/Z, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LDR X16, [X13, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X17, [X11, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CNTD X8, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
LD1RD {Z2.D}, P0/Z, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
LD1RD {Z3.D}, P0/Z, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	6	0.50	scal (25.0%)
ORR X13, XZR, #0x55	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR X9, [X9, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SUBS X10, X18, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL X10, XZR, X10, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
WHILELO P1.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2	N/A
SUB X11, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVK X13, #16325	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z4.D, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z5.D, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z6.D, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z7.D, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z17.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z20.D, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z23.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z21.D, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
DUP Z24.D, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
ADRP X0, <47dc7c>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #272	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR W1, WZR, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 4105b0 <@plt_start@+0x590>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D9, D8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDP D11, D10, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
LDR D12, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X25, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
ADD SP, SP, #160	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A
HINT #0																			N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.87	5.39
○Loop 166 - advec_mom.cpp:181-211 - exec	3.87	5.26

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code