OV - exec - Loop 146

	Loop Id: 146	Module: exec	Source: accelerate.cpp:41-53 [...]	Coverage: 7.14%

0x427488 DUP	Z0.D, #1

0x42748c SUB	X11, X29, #64

0x427490 LDR	D23, [X19]    [51]

0x427494 ADD	X10, X10, X8

0x427498 LDR	Z2, [X11, #508, MUL VL]    [33]

0x42749c LDR	Z21, [X11, #510, MUL VL]    [33]

0x4274a0 SEL	Z24.D, P0, Z1.D, Z0.D

0x4274a4 LDR	Z0, [X11, #511, MUL VL]    [33]

0x4274a8 SDIVR	Z24.D, P1/M, Z24.D, Z12.D

0x4274ac ADD	Z27.D, Z0.D, Z24.D

0x4274b0 MOVPRFX	Z0, Z12

0x4274b4 MLS	Z0.D, P1/M, Z24.D, Z1.D

0x4274b8 ADD	Z14.D, Z2.D, Z0.D

0x4274bc LDR	Z2, [X11, #505, MUL VL]    [33]

0x4274c0 ADR	Z17.D, [Z26, Z14.D,SXTW #3]    [26]

0x4274c4 ADD	Z24.D, Z2.D, Z24.D

0x4274c8 MOVPRFX	Z13, Z24

0x4274cc SXTW	Z13.D, P1/M, Z24.D

0x4274d0 ADR	Z24.D, [Z25, Z14.D,SXTW #3]    [21]

0x4274d4 MOVPRFX	Z2, Z3

0x4274d8 MUL	Z2.D, P1/M, Z2.D, Z13.D

0x4274dc MOVPRFX	Z4, Z20

0x4274e0 MUL	Z4.D, P1/M, Z4.D, Z13.D

0x4274e4 ADR	Z15.D, [Z24, Z2.D,LSL #3]    [17]

0x4274e8 LD1D	{Z5.D}, P0/Z, [V15.D]    [20]

0x4274ec ADR	Z15.D, [Z17, Z4.D,LSL #3]    [32]

0x4274f0 LD1D	{Z18.D}, P0/Z, [V15.D]    [19]

0x4274f4 MOVPRFX	Z15, Z27

0x4274f8 SXTW	Z15.D, P1/M, Z27.D

0x4274fc MOVPRFX	Z27, Z3

0x427500 MUL	Z27.D, P1/M, Z27.D, Z15.D

0x427504 MOVPRFX	Z7, Z20

0x427508 MUL	Z7.D, P1/M, Z7.D, Z15.D

0x42750c ADR	Z24.D, [Z24, Z27.D,LSL #3]    [17]

0x427510 ADR	Z17.D, [Z17, Z7.D,LSL #3]    [32]

0x427514 LD1D	{Z19.D}, P0/Z, [V24.D]    [16]

0x427518 ADD	Z24.D, Z21.D, Z0.D

0x42751c FMUL	Z5.D, Z18.D, Z5.D

0x427520 LD1D	{Z17.D}, P0/Z, [V17.D]    [30]

0x427524 LDR	Z18, [X11, #501, MUL VL]    [33]

0x427528 ADR	Z0.D, [Z25, Z24.D,SXTW #3]    [21]

0x42752c ADR	Z21.D, [Z26, Z24.D,SXTW #3]    [26]

0x427530 ADR	Z28.D, [Z30, Z24.D,SXTW #3]    [6]

0x427534 ADR	Z27.D, [Z0, Z27.D,LSL #3]    [47]

0x427538 ADR	Z7.D, [Z21, Z7.D,LSL #3]    [11]

0x42753c ADR	Z0.D, [Z0, Z2.D,LSL #3]    [47]

0x427540 ADR	Z4.D, [Z21, Z4.D,LSL #3]    [11]

0x427544 DUP	Z2.D, Z23.D[0]

0x427548 MOVPRFX	Z23, Z16

0x42754c MUL	Z23.D, P1/M, Z23.D, Z15.D

0x427550 ADR	Z18.D, [Z18, Z24.D,SXTW #3]    [37]

0x427554 FMLA	Z5.D, P1/M, Z17.D, Z19.D

0x427558 LD1D	{Z27.D}, P0/Z, [V27.D]    [34]

0x42755c LD1D	{Z7.D}, P0/Z, [V7.D]    [7]

0x427560 LD1D	{Z0.D}, P0/Z, [V0.D]    [46]

0x427564 LD1D	{Z4.D}, P0/Z, [V4.D]    [2]

0x427568 LDR	Z17, [X11, #509, MUL VL]    [33]

0x42756c ADR	Z29.D, [Z28, Z23.D,LSL #3]    [38]

0x427570 LDR	Z19, [X11, #500, MUL VL]    [33]

0x427574 LD1D	{Z31.D}, P0/Z, [V29.D]    [43]

0x427578 FMLA	Z5.D, P1/M, Z7.D, Z27.D

0x42757c MUL	Z17.D, P1/M, Z17.D, Z15.D

0x427580 ADR	Z19.D, [Z19, Z24.D,SXTW #3]    [41]

0x427584 FMAD	Z0.D, P1/M, Z4.D, Z5.D

0x427588 ADR	Z4.D, [Z30, Z14.D,SXTW #3]    [6]

0x42758c ADR	Z17.D, [Z18, Z17.D,LSL #3]    [36]

0x427590 MOVPRFX	Z18, Z6

0x427594 MUL	Z18.D, P1/M, Z18.D, Z15.D

0x427598 ADR	Z5.D, [Z4, Z23.D,LSL #3]    [1]

0x42759c FDUP	Z23.D, #80

0x4275a0 LD1D	{Z17.D}, P0/Z, [V17.D]    [29]

0x4275a4 FMUL	Z0.D, Z0.D, Z23.D

0x4275a8 MOVPRFX	Z23, Z6

0x4275ac MUL	Z23.D, P1/M, Z23.D, Z13.D

0x4275b0 ADR	Z18.D, [Z19, Z18.D,LSL #3]    [40]

0x4275b4 LD1D	{Z7.D}, P0/Z, [V5.D]    [4]

0x4275b8 MOVPRFX	Z27, Z2

0x4275bc FDIV	Z27.D, P1/M, Z27.D, Z0.D

0x4275c0 MOVPRFX	Z0, Z16

0x4275c4 MUL	Z0.D, P1/M, Z0.D, Z13.D

0x4275c8 MUL	Z13.D, P1/M, Z13.D, Z22.D

0x4275cc LD1D	{Z21.D}, P0/Z, [V18.D]    [35]

0x4275d0 ADR	Z19.D, [Z19, Z23.D,LSL #3]    [40]

0x4275d4 ADR	Z2.D, [Z28, Z0.D,LSL #3]    [38]

0x4275d8 ADR	Z0.D, [Z4, Z0.D,LSL #3]    [1]

0x4275dc FSUB	Z7.D, Z7.D, Z31.D

0x4275e0 LD1D	{Z23.D}, P0/Z, [V19.D]    [39]

0x4275e4 LD1D	{Z28.D}, P0/Z, [V2.D]    [50]

0x4275e8 LD1D	{Z4.D}, P0/Z, [V0.D]    [45]

0x4275ec FMUL	Z7.D, Z7.D, Z21.D

0x4275f0 ADR	Z21.D, [Z9, Z24.D,SXTW #3]    [13]

0x4275f4 FSUB	Z4.D, Z4.D, Z28.D

0x4275f8 FMAD	Z4.D, P1/M, Z23.D, Z7.D

0x4275fc LDR	Z7, [X11, #507, MUL VL]    [33]

0x427600 FMAD	Z4.D, P1/M, Z27.D, Z17.D

0x427604 LDR	Z17, [X11, #499, MUL VL]    [33]

0x427608 MUL	Z7.D, P1/M, Z7.D, Z15.D

0x42760c ADR	Z17.D, [Z17, Z24.D,SXTW #3]    [28]

0x427610 ADR	Z7.D, [Z17, Z7.D,LSL #3]    [27]

0x427614 ADR	Z17.D, [Z8, Z24.D,SXTW #3]    [12]

0x427618 ST1D	{Z4.D}, P0, [V7.D]    [31]

0x42761c LDR	Z4, [X11, #506, MUL VL]    [33]

0x427620 LD1D	{Z28.D}, P0/Z, [V29.D]    [43]

0x427624 ADR	Z29.D, [Z9, Z14.D,SXTW #3]    [13]

0x427628 LD1D	{Z2.D}, P0/Z, [V2.D]    [50]

0x42762c LD1D	{Z5.D}, P0/Z, [V5.D]    [4]

0x427630 LD1D	{Z0.D}, P0/Z, [V0.D]    [45]

0x427634 MUL	Z4.D, P1/M, Z4.D, Z15.D

0x427638 FSUB	Z2.D, Z2.D, Z28.D

0x42763c FSUB	Z0.D, Z0.D, Z5.D

0x427640 ADR	Z4.D, [Z17, Z4.D,LSL #3]    [49]

0x427644 LDR	Z17, [X11, #504, MUL VL]    [33]

0x427648 LD1D	{Z4.D}, P0/Z, [V4.D]    [25]

0x42764c MUL	Z17.D, P1/M, Z17.D, Z15.D

0x427650 ADR	Z21.D, [Z21, Z17.D,LSL #3]    [10]

0x427654 ADR	Z17.D, [Z29, Z17.D,LSL #3]    [42]

0x427658 LD1D	{Z23.D}, P0/Z, [V21.D]    [9]

0x42765c FMUL	Z2.D, Z2.D, Z23.D

0x427660 ADR	Z23.D, [Z11, Z14.D,SXTW #3]    [8]

0x427664 LD1D	{Z29.D}, P0/Z, [V17.D]    [48]

0x427668 FMAD	Z0.D, P1/M, Z29.D, Z2.D

0x42766c LDR	Z2, [X11, #503, MUL VL]    [33]

0x427670 FMAD	Z0.D, P1/M, Z27.D, Z4.D

0x427674 ADR	Z4.D, [Z10, Z24.D,SXTW #3]    [5]

0x427678 MUL	Z2.D, P1/M, Z2.D, Z15.D

0x42767c MUL	Z15.D, P1/M, Z15.D, Z22.D

0x427680 ADR	Z2.D, [Z4, Z2.D,LSL #3]    [24]

0x427684 ADR	Z4.D, [Z11, Z24.D,SXTW #3]    [8]

0x427688 ADR	Z24.D, [Z23, Z15.D,LSL #3]    [14]

0x42768c ADR	Z23.D, [Z23, Z13.D,LSL #3]    [14]

0x427690 ADR	Z5.D, [Z4, Z15.D,LSL #3]    [23]

0x427694 ST1D	{Z0.D}, P0, [V2.D]    [18]

0x427698 ADR	Z4.D, [Z4, Z13.D,LSL #3]    [23]

0x42769c LD1D	{Z0.D}, P0/Z, [V18.D]    [35]

0x4276a0 LD1D	{Z28.D}, P0/Z, [V24.D]    [15]

0x4276a4 LD1D	{Z31.D}, P0/Z, [V23.D]    [44]

0x4276a8 LD1D	{Z19.D}, P0/Z, [V19.D]    [39]

0x4276ac LD1D	{Z18.D}, P0/Z, [V5.D]    [3]

0x4276b0 LD1D	{Z29.D}, P0/Z, [V4.D]    [22]

0x4276b4 FSUB	Z18.D, Z28.D, Z18.D

0x4276b8 FMUL	Z0.D, Z18.D, Z0.D

0x4276bc FSUB	Z18.D, Z31.D, Z29.D

0x4276c0 FMLA	Z0.D, P1/M, Z18.D, Z19.D

0x4276c4 LD1D	{Z18.D}, P0/Z, [V7.D]    [31]

0x4276c8 FMAD	Z0.D, P1/M, Z27.D, Z18.D

0x4276cc ST1D	{Z0.D}, P0, [V7.D]    [31]

0x4276d0 LD1D	{Z5.D}, P0/Z, [V5.D]    [3]

0x4276d4 LD1D	{Z4.D}, P0/Z, [V4.D]    [22]

0x4276d8 LD1D	{Z0.D}, P0/Z, [V21.D]    [9]

0x4276dc LD1D	{Z7.D}, P0/Z, [V24.D]    [15]

0x4276e0 FSUB	Z4.D, Z4.D, Z5.D

0x4276e4 LD1D	{Z5.D}, P0/Z, [V2.D]    [18]

0x4276e8 FMUL	Z0.D, Z4.D, Z0.D

0x4276ec LD1D	{Z4.D}, P0/Z, [V23.D]    [44]

0x4276f0 FSUB	Z4.D, Z4.D, Z7.D

0x4276f4 LD1D	{Z7.D}, P0/Z, [V17.D]    [48]

0x4276f8 FMLA	Z0.D, P1/M, Z4.D, Z7.D

0x4276fc FMAD	Z0.D, P1/M, Z27.D, Z5.D

0x427700 ST1D	{Z0.D}, P0, [V2.D]    [18]

0x427704 WHILELO	P0.D, X10, X9

0x427708 LDR	Z0, [X11, #502, MUL VL]    [33]

0x42770c ADD	Z12.D, Z12.D, Z0.D

0x427710 B.MI	427488

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp: 41 - 53

--------------------------------------------------------------------------------

41:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

42:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

43:       double stepbymass_s = halfdt / ((density0(i - 1, j - 1) * volume(i - 1, j - 1) + density0(i - 1, j + 0) * volume(i - 1, j + 0) +

44:                                        density0(i, j) * volume(i, j) + density0(i + 0, j - 1) * volume(i + 0, j - 1)) *

45:                                       0.25);

46:       xvel1(i, j) = xvel0(i, j) - stepbymass_s * (xarea(i, j) * (pressure(i, j) - pressure(i - 1, j + 0)) +

47:                                                   xarea(i + 0, j - 1) * (pressure(i + 0, j - 1) - pressure(i - 1, j - 1)));

48:       yvel1(i, j) = yvel0(i, j) - stepbymass_s * (yarea(i, j) * (pressure(i, j) - pressure(i + 0, j - 1)) +

49:                                                   yarea(i - 1, j + 0) * (pressure(i - 1, j + 0) - pressure(i - 1, j - 1)));

50:       xvel1(i, j) = xvel1(i, j) - stepbymass_s * (xarea(i, j) * (viscosity(i, j) - viscosity(i - 1, j + 0)) +

51:                                                   xarea(i + 0, j - 1) * (viscosity(i + 0, j - 1) - viscosity(i - 1, j - 1)));

52:       yvel1(i, j) = yvel1(i, j) - stepbymass_s * (yarea(i, j) * (viscosity(i, j) - viscosity(i + 0, j - 1)) +

53:                                                   yarea(i - 1, j + 0) * (viscosity(i - 1, j + 0) - viscosity(i - 1, j - 1)));

Coverage (%)	Name	Source Location	Module
►98.42+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	accelerate(global_variables&)	accelerate.cpp:66	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.42
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	context.h:69-69,accelerate.cpp:41-53
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	52.50
CQA cycles if no scalar integer	52.50
CQA cycles if FP arith vectorized	52.50
CQA cycles if fully vectorized	36.91
Front-end cycles	20.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	52.50
P7 cycles	52.50
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	18.17
P11 cycles	17.83
P12 cycles	18.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	7.87 - 34.08
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	163.00
Nb uops	163.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	2.82
Nb FLOP add-sub	32.00
Nb FLOP mul	24.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.40
Bytes prefetched	0.00
Bytes loaded	1572.88
Bytes stored	128.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	40.00
Stride indirect	10.00
Vectorization ratio all	65.63
Vectorization ratio load	55.06
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	25.93
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	22.22
Vector-efficiency ratio all	79.57
Vector-efficiency ratio load	66.29
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	44.44
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.24

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.42
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	context.h:69-69,accelerate.cpp:41-53
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	52.50
CQA cycles if no scalar integer	52.50
CQA cycles if FP arith vectorized	52.50
CQA cycles if fully vectorized	36.91
Front-end cycles	20.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	52.50
P7 cycles	52.50
P8 cycles	20.00
P9 cycles	20.00
P10 cycles	18.17
P11 cycles	17.83
P12 cycles	18.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	7.87 - 34.08
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	163.00
Nb uops	163.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	2.82
Nb FLOP add-sub	32.00
Nb FLOP mul	24.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.40
Bytes prefetched	0.00
Bytes loaded	1572.88
Bytes stored	128.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	40.00
Stride indirect	10.00
Vectorization ratio all	65.63
Vectorization ratio load	55.06
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	25.93
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	22.22
Vector-efficiency ratio all	79.57
Vector-efficiency ratio load	66.29
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	44.44
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	89.24

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	accelerate.cpp:41-53
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41-53

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 79% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 52.50 to 36.91 cycles (1.42x speedup).

Details

65% of VPU instructions are used in vector version (process two or more data elements in vector registers):

55% of VPU loads are used in vector version.
25% of VPU addition or subtraction instructions are used in vector version.
22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 40 occurrence(s)
Irregular (variable stride) or indirect: 10 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

76: addition or subtraction (44 inside FMA instructions)
68: multiply (44 inside FMA instructions)
4: divide

The binary loop is loading 1572 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	163
nb uops	163
loop length	652
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	1
used q registers	0
used v registers	14
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.38 cycles
front end	20.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	52.50	52.50	20.00	20.00	18.17	17.83	18.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	52.50	52.50	20.00	20.00	18.17	17.83	18.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	7.87-34.08
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	20.38
Dispatch	52.50
DIV/SQRT	7.87-34.08
Data deps.	2.00
Overall L1	52.50

Vectorization ratios

INT

all	59%
load	55%
store	100%
mul	100%
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

INT+FP

all	65%
load	55%
store	100%
mul	100%
add-sub	25%
fma	100%
div/sqrt	100%
other	22%

Vector efficiency ratios

INT

all	76%
load	66%
store	100%
mul	100%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
other	94%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	3%

INT+FP

all	79%
load	66%
store	100%
mul	100%
add-sub	44%
fma	100%
div/sqrt	100%
other	89%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 52.50 cycles. At this rate:

31% of peak load performance is reached (29.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.44 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 427488

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X11, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR Z2, [X11, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z21, [X11, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SEL Z24.D, P0, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X11, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SDIVR Z24.D, P1/M, Z24.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z27.D, Z0.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z0, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z0.D, P1/M, Z24.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z14.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z2, [X11, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z17.D, [Z26, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z24.D, Z2.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z13.D, P1/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADR Z24.D, [Z25, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z2, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z2.D, P1/M, Z2.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z4, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P1/M, Z4.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z15.D, [Z24, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z5.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z15.D, [Z17, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z18.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MOVPRFX Z15, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z15.D, P1/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z27, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P1/M, Z27.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z7, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z7.D, P1/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z24.D, [Z24, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z17, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z19.D}, P0/Z, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z24.D, Z21.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z17.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LDR Z18, [X11, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z0.D, [Z25, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z21.D, [Z26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z28.D, [Z30, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z0, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z21, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z0, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z21, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
DUP Z2.D, Z23.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z23, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z23.D, P1/M, Z23.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z18.D, [Z18, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMLA Z5.D, P1/M, Z17.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LDR Z17, [X11, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z29.D, [Z28, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z19, [X11, #500, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z31.D}, P0/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z5.D, P1/M, Z7.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MUL Z17.D, P1/M, Z17.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z19.D, [Z19, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMAD Z0.D, P1/M, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z4.D, [Z30, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z18, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z18, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z18.D, P1/M, Z18.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z4, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FDUP Z23.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
LD1D {Z17.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z0.D, Z0.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z23, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z23.D, P1/M, Z23.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z18.D, [Z19, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z7.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MOVPRFX Z27, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z27.D, P1/M, Z27.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z0, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z0.D, P1/M, Z0.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z13.D, P1/M, Z13.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z19.D, [Z19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z28, Z0.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z4, Z0.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FSUB Z7.D, Z7.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z28.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z7.D, Z7.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z21.D, [Z9, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FSUB Z4.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z4.D, P1/M, Z23.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z7, [X11, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z4.D, P1/M, Z27.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z17, [X11, #499, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MUL Z7.D, P1/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z17.D, [Z17, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z17, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z8, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z4.D}, P0, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LDR Z4, [X11, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z28.D}, P0/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z29.D, [Z9, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z4.D, P1/M, Z4.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FSUB Z2.D, Z2.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z0.D, Z0.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z4.D, [Z17, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z17, [X11, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z17.D, P1/M, Z17.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z21.D, [Z21, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z29, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z23.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z2.D, Z2.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z23.D, [Z11, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z29.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z0.D, P1/M, Z29.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z2, [X11, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z0.D, P1/M, Z27.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z4.D, [Z10, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MUL Z2.D, P1/M, Z2.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z15.D, P1/M, Z15.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z2.D, [Z4, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z11, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z24.D, [Z23, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z23.D, [Z23, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z4, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
ADR Z4.D, [Z4, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z0.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z28.D}, P0/Z, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z31.D}, P0/Z, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z18.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z29.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z18.D, Z28.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.D, Z18.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z18.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z0.D, P1/M, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z18.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z0.D, P1/M, Z27.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z0.D}, P0, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z0.D, Z4.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z4.D, Z4.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z0.D, P1/M, Z4.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z0.D, P1/M, Z27.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P0.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LDR Z0, [X11, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z12.D, Z12.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
B.MI 427488 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	accelerate.cpp:41-53
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41-53

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

65% of VPU instructions are used in vector version (process two or more data elements in vector registers):

55% of VPU loads are used in vector version.
25% of VPU addition or subtraction instructions are used in vector version.
22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 40 occurrence(s)
Irregular (variable stride) or indirect: 10 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

76: addition or subtraction (44 inside FMA instructions)
68: multiply (44 inside FMA instructions)
4: divide

The binary loop is loading 1572 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	163
nb uops	163
loop length	652
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	1
used q registers	0
used v registers	14
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.33

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.38 cycles
front end	20.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	52.50	52.50	20.00	20.00	18.17	17.83	18.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	52.50	52.50	20.00	20.00	18.17	17.83	18.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	7.87-34.08
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	20.38
Dispatch	52.50
DIV/SQRT	7.87-34.08
Data deps.	2.00
Overall L1	52.50

Vectorization ratios

INT

all	59%
load	55%
store	100%
mul	100%
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
other	27%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

INT+FP

all	65%
load	55%
store	100%
mul	100%
add-sub	25%
fma	100%
div/sqrt	100%
other	22%

Vector efficiency ratios

INT

all	76%
load	66%
store	100%
mul	100%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
other	94%

all	96%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	3%

INT+FP

all	79%
load	66%
store	100%
mul	100%
add-sub	44%
fma	100%
div/sqrt	100%
other	89%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 52.50 cycles. At this rate:

31% of peak load performance is reached (29.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.44 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 427488

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X11, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR D23, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR Z2, [X11, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z21, [X11, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SEL Z24.D, P0, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X11, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SDIVR Z24.D, P1/M, Z24.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z27.D, Z0.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z0, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z0.D, P1/M, Z24.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z14.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z2, [X11, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z17.D, [Z26, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z24.D, Z2.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z13, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z13.D, P1/M, Z24.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADR Z24.D, [Z25, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z2, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z2.D, P1/M, Z2.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z4, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P1/M, Z4.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z15.D, [Z24, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z5.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z15.D, [Z17, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z18.D}, P0/Z, [V15.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MOVPRFX Z15, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z15.D, P1/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z27, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P1/M, Z27.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z7, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z7.D, P1/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z24.D, [Z24, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z17, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z19.D}, P0/Z, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z24.D, Z21.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z17.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LDR Z18, [X11, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z0.D, [Z25, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z21.D, [Z26, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z28.D, [Z30, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z0, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z21, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z0, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z21, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
DUP Z2.D, Z23.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z23, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z23.D, P1/M, Z23.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z18.D, [Z18, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMLA Z5.D, P1/M, Z17.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z27.D}, P0/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LDR Z17, [X11, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z29.D, [Z28, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z19, [X11, #500, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z31.D}, P0/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z5.D, P1/M, Z7.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MUL Z17.D, P1/M, Z17.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z19.D, [Z19, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMAD Z0.D, P1/M, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z4.D, [Z30, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z18, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z18, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z18.D, P1/M, Z18.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z4, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FDUP Z23.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
LD1D {Z17.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z0.D, Z0.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z23, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z23.D, P1/M, Z23.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z18.D, [Z19, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z7.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MOVPRFX Z27, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FDIV Z27.D, P1/M, Z27.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
MOVPRFX Z0, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z0.D, P1/M, Z0.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z13.D, P1/M, Z13.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z21.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z19.D, [Z19, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z28, Z0.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z4, Z0.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FSUB Z7.D, Z7.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z23.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z28.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z7.D, Z7.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z21.D, [Z9, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FSUB Z4.D, Z4.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z4.D, P1/M, Z23.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z7, [X11, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z4.D, P1/M, Z27.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z17, [X11, #499, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MUL Z7.D, P1/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z17.D, [Z17, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z17, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z8, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z4.D}, P0, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LDR Z4, [X11, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z28.D}, P0/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z29.D, [Z9, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z4.D, P1/M, Z4.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FSUB Z2.D, Z2.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z0.D, Z0.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z4.D, [Z17, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z17, [X11, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z17.D, P1/M, Z17.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z21.D, [Z21, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z29, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z23.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z2.D, Z2.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z23.D, [Z11, Z14.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z29.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z0.D, P1/M, Z29.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z2, [X11, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAD Z0.D, P1/M, Z27.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z4.D, [Z10, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MUL Z2.D, P1/M, Z2.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z15.D, P1/M, Z15.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z2.D, [Z4, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z11, Z24.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z24.D, [Z23, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z23.D, [Z23, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z4, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
ADR Z4.D, [Z4, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z0.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z28.D}, P0/Z, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z31.D}, P0/Z, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z18.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z29.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z18.D, Z28.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.D, Z18.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FSUB Z18.D, Z31.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z0.D, P1/M, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z18.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z0.D, P1/M, Z27.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z0.D}, P0, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V21.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z0.D, Z4.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z4.D, Z4.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z0.D, P1/M, Z4.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMAD Z0.D, P1/M, Z27.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P0.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LDR Z0, [X11, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z12.D, Z12.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
B.MI 427488 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code