OV - exec - Loop 150

	Loop Id: 150	Module: exec	Source: advec_cell.cpp:66-110 [...]	Coverage: 2.92%

0x4280c4 DUP	Z0.D, #1

0x4280c8 SUB	X12, X29, #64

0x4280cc ADD	X11, X11, X8

0x4280d0 SEL	Z31.D, P0, Z4.D, Z0.D

0x4280d4 LDR	Z0, [X12, #511, MUL VL]    [21]

0x4280d8 SDIVR	Z31.D, P1/M, Z31.D, Z30.D

0x4280dc MOVPRFX	Z10, Z30

0x4280e0 MLS	Z10.D, P1/M, Z31.D, Z4.D

0x4280e4 ADD	Z8.D, Z7.D, Z31.D

0x4280e8 ADD	Z30.D, Z30.D, Z18.D

0x4280ec SXTW	Z8.D, P1/M, Z8.D

0x4280f0 MOVPRFX	Z9, Z0

0x4280f4 MUL	Z9.D, P1/M, Z9.D, Z8.D

0x4280f8 DUPM	Z0.D, #0xfffffffe

0x4280fc ADD	Z31.D, Z16.D, Z10.D

0x428100 ADD	Z10.D, Z17.D, Z10.D

0x428104 ADR	Z12.D, [Z20, Z31.D,SXTW #3]    [2]

0x428108 ORR	Z14.D, Z31.D, Z31.D

0x42810c ADD	Z13.D, Z31.D, Z0.D

0x428110 LDR	Z0, [X12, #510, MUL VL]    [21]

0x428114 MOVPRFX	Z11, Z31

0x428118 SXTW	Z11.D, P1/M, Z31.D

0x42811c MOVPRFX	Z15, Z10

0x428120 SXTW	Z15.D, P1/M, Z10.D

0x428124 ADR	Z9.D, [Z12, Z9.D,LSL #3]    [3]

0x428128 ADD	Z14.D, Z14.D, #1

0x42812c SXTW	Z14.D, P1/M, Z14.D

0x428130 SMIN	Z14.D, P1/M, Z14.D, Z21.D

0x428134 LD1D	{Z1.D}, P0/Z, [V9.D]    [7]

0x428138 LD1D	{Z12.D}, P0/Z, [X9, Z31.D,SXTW #3]    [4]

0x42813c FCMGT	P2.D, P1/Z, Z1.D, #0.0000000

0x428140 MOVPRFX	Z9, Z1

0x428144 FABS	Z9.D, P1/M, Z1.D

0x428148 SEL	Z19.D, P2, Z11.D, Z15.D

0x42814c SEL	Z11.D, P2, Z15.D, Z11.D

0x428150 SEL	Z15.D, P2, Z10.D, Z14.D

0x428154 MOVPRFX	Z10, Z0

0x428158 MUL	Z10.D, P1/M, Z10.D, Z8.D

0x42815c SEL	Z13.D, P2, Z13.D, Z14.D

0x428160 LDR	Z0, [X12, #509, MUL VL]    [21]

0x428164 ADR	Z14.D, [Z23, Z11.D,LSL #3]    [8]

0x428168 LD1D	{Z15.D}, P0/Z, [X9, Z15.D,SXTW #3]    [4]

0x42816c ADR	Z24.D, [Z25, Z11.D,LSL #3]    [19]

0x428170 ADR	Z10.D, [Z14, Z10.D,LSL #3]    [11]

0x428174 MOVPRFX	Z2, Z0

0x428178 MUL	Z2.D, P1/M, Z2.D, Z8.D

0x42817c LD1D	{Z14.D}, P0/Z, [V10.D]    [1]

0x428180 ADR	Z24.D, [Z24, Z2.D,LSL #3]    [13]

0x428184 FDIV	Z9.D, P1/M, Z9.D, Z14.D

0x428188 ADR	Z14.D, [Z25, Z13.D,SXTW #3]    [19]

0x42818c ADR	Z14.D, [Z14, Z2.D,LSL #3]    [10]

0x428190 LD1D	{Z0.D}, P0/Z, [V24.D]    [12]

0x428194 LD1D	{Z14.D}, P0/Z, [V14.D]    [9]

0x428198 FMAD	Z12.D, P1/M, Z9.D, Z12.D

0x42819c FDIV	Z12.D, P1/M, Z12.D, Z15.D

0x4281a0 ADR	Z15.D, [Z25, Z19.D,LSL #3]    [19]

0x4281a4 ADR	Z19.D, [Z28, Z19.D,LSL #3]    [22]

0x4281a8 ADR	Z2.D, [Z15, Z2.D,LSL #3]    [17]

0x4281ac FSUB	Z15.D, Z0.D, Z14.D

0x4281b0 FABD	Z14.D, P1/M, Z14.D, Z0.D

0x4281b4 LD1D	{Z2.D}, P0/Z, [V2.D]    [28]

0x4281b8 FSUB	Z22.D, Z2.D, Z0.D

0x4281bc FABD	Z2.D, P1/M, Z2.D, Z0.D

0x4281c0 FMUL	Z15.D, Z22.D, Z15.D

0x4281c4 FCMGT	P3.D, P1/Z, Z22.D, #0.0000000

0x4281c8 FCMGT	P2.D, P1/Z, Z15.D, #0.0000000

0x4281cc FDUP	Z15.D, #0

0x4281d0 FSUB	Z15.D, Z15.D, Z9.D

0x4281d4 FSUBR	Z9.D, P1/M, Z9.D, #0.0000000

0x4281d8 MOVPRFX	Z22, Z9

0x4281dc FNEG	Z22.D, P1/M, Z9.D

0x4281e0 SEL	Z22.D, P3, Z9.D, Z22.D

0x4281e4 MOVPRFX	Z9, Z14

0x4281e8 FMINNM	Z9.D, P1/M, Z9.D, Z2.D

0x4281ec FMUL	Z14.D, Z14.D, Z12.D

0x4281f0 FMAD	Z2.D, P1/M, Z15.D, Z14.D

0x4281f4 FMUL	Z2.D, Z2.D, Z26.D

0x4281f8 FMINNM	Z2.D, P1/M, Z2.D, Z9.D

0x4281fc FMLA	Z0.D, P2/M, Z2.D, Z22.D

0x428200 ADR	Z2.D, [Z27, Z31.D,SXTW #3]    [20]

0x428204 ADR	Z22.D, [Z28, Z13.D,SXTW #3]    [22]

0x428208 FMUL	Z0.D, Z0.D, Z1.D

0x42820c MOVPRFX	Z1, Z3

0x428210 MUL	Z1.D, P1/M, Z1.D, Z8.D

0x428214 ADR	Z1.D, [Z2, Z1.D,LSL #3]    [27]

0x428218 ADR	Z2.D, [Z28, Z11.D,LSL #3]    [22]

0x42821c ST1D	{Z0.D}, P0, [V1.D]    [26]

0x428220 MOVPRFX	Z1, Z5

0x428224 MUL	Z1.D, P1/M, Z1.D, Z8.D

0x428228 MUL	Z8.D, P1/M, Z8.D, Z6.D

0x42822c ADR	Z2.D, [Z2, Z1.D,LSL #3]    [18]

0x428230 ADR	Z22.D, [Z22, Z1.D,LSL #3]    [6]

0x428234 ADR	Z1.D, [Z19, Z1.D,LSL #3]    [23]

0x428238 LD1D	{Z2.D}, P0/Z, [V2.D]    [16]

0x42823c LD1D	{Z22.D}, P0/Z, [V22.D]    [5]

0x428240 LD1D	{Z1.D}, P0/Z, [V1.D]    [25]

0x428244 FSUB	Z9.D, Z2.D, Z22.D

0x428248 FSUB	Z19.D, Z1.D, Z2.D

0x42824c FABD	Z22.D, P1/M, Z22.D, Z2.D

0x428250 FABD	Z1.D, P1/M, Z1.D, Z2.D

0x428254 FMUL	Z9.D, Z19.D, Z9.D

0x428258 FCMGT	P4.D, P1/Z, Z19.D, #0.0000000

0x42825c FCMGT	P2.D, P1/Z, Z9.D, #0.0000000

0x428260 AND	P3.B, P0/Z, P0.B, P2.B

0x428264 LD1D	{Z24.D}, P3/Z, [V24.D]    [12]

0x428268 LD1D	{Z19.D}, P3/Z, [V10.D]    [1]

0x42826c FMUL	Z19.D, Z19.D, Z24.D

0x428270 MOVPRFX	Z24, Z0

0x428274 FABS	Z24.D, P1/M, Z0.D

0x428278 FDIVR	Z19.D, P1/M, Z19.D, Z24.D

0x42827c FSUBR	Z19.D, P1/M, Z19.D, #0.0000000

0x428280 MOVPRFX	Z24, Z19

0x428284 FNEG	Z24.D, P1/M, Z19.D

0x428288 SEL	Z19.D, P4, Z19.D, Z24.D

0x42828c FMUL	Z24.D, Z22.D, Z12.D

0x428290 FMLA	Z24.D, P1/M, Z1.D, Z15.D

0x428294 FMINNM	Z1.D, P1/M, Z1.D, Z22.D

0x428298 FMUL	Z22.D, Z24.D, Z26.D

0x42829c FMINNM	Z1.D, P1/M, Z1.D, Z22.D

0x4282a0 FMLA	Z2.D, P2/M, Z19.D, Z1.D

0x4282a4 ADR	Z1.D, [Z29, Z31.D,SXTW #3]    [24]

0x4282a8 ADR	Z1.D, [Z1, Z8.D,LSL #3]    [15]

0x4282ac FMUL	Z0.D, Z2.D, Z0.D

0x4282b0 ST1D	{Z0.D}, P0, [V1.D]    [14]

0x4282b4 WHILELO	P0.D, X11, X10

0x4282b8 B.MI	4280c4

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 66 - 110

--------------------------------------------------------------------------------

66:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Module
►98.42+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.19 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P6, P8,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.3]
Source	advec_cell.cpp:66-110,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	52.00 - 62.25
CQA cycles if no scalar integer	52.00 - 62.25
CQA cycles if FP arith vectorized	52.00 - 62.25
CQA cycles if fully vectorized	43.53 - 62.25
Front-end cycles	15.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	2.00
P5 cycles	0.50
P6 cycles	52.00
P7 cycles	52.00
P8 cycles	10.50
P9 cycles	10.50
P10 cycles	5.83
P11 cycles	5.50
P12 cycles	5.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	21.85 - 62.25
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	126.00
Nb uops	126.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.23 - 1.86
Nb FLOP add-sub	28.00
Nb FLOP mul	36.00
Nb FLOP fma	20.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.78 - 10.51
Bytes prefetched	0.00
Bytes loaded	482.50
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	21.00
Stride indirect	7.00
Vectorization ratio all	71.31
Vectorization ratio load	42.86
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	41.18
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	68.09
Vector-efficiency ratio all	85.40
Vector-efficiency ratio load	57.14
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	55.88
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	94.02

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.19 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P6, P8,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.3]
Source	advec_cell.cpp:66-110,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	52.00 - 62.25
CQA cycles if no scalar integer	52.00 - 62.25
CQA cycles if FP arith vectorized	52.00 - 62.25
CQA cycles if fully vectorized	43.53 - 62.25
Front-end cycles	15.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	2.00
P5 cycles	0.50
P6 cycles	52.00
P7 cycles	52.00
P8 cycles	10.50
P9 cycles	10.50
P10 cycles	5.83
P11 cycles	5.50
P12 cycles	5.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	21.85 - 62.25
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	126.00
Nb uops	126.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.23 - 1.86
Nb FLOP add-sub	28.00
Nb FLOP mul	36.00
Nb FLOP fma	20.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.78 - 10.51
Bytes prefetched	0.00
Bytes loaded	482.50
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	21.00
Stride indirect	7.00
Vectorization ratio all	71.31
Vectorization ratio load	42.86
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	41.18
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	68.09
Vector-efficiency ratio all	85.40
Vector-efficiency ratio load	57.14
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	55.88
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	94.02

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.3]
Source file and lines	advec_cell.cpp:66-110
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66-110
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions).

Details

71% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
41% of VPU addition or subtraction instructions are used in vector version.
68% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 62.25 to 50.00 cycles (1.25x speedup).

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 21 occurrence(s)
Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

48: addition or subtraction (20 inside FMA instructions)
56: multiply (20 inside FMA instructions)
12: divide

The binary loop is loading 482 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	126
nb uops	126
loop length	504
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	7
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	0.78

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.75 cycles
front end	15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	2.00	0.50	52.00	52.00	6.00	6.00	5.83	5.50	5.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	2.00	0.50	52.00	52.00	10.50	10.50	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	21.85-62.25
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	15.75
Dispatch	52.00
DIV/SQRT	21.85-62.25
Data deps.	0.00
Overall L1	52.00-62.25

Vectorization ratios

INT

all	57%
load	42%
store	100%
mul	100%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	53%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	71%
load	42%
store	100%
mul	100%
add-sub	41%
fma	100%
div/sqrt	100%
other	68%

Vector efficiency ratios

INT

all	78%
load	57%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	93%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	85%
load	57%
store	100%
mul	100%
add-sub	55%
fma	100%
div/sqrt	100%
other	94%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 62.25 cycles. At this rate:

8% of peak load performance is reached (7.75 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.03 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4280c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SEL Z31.D, P0, Z4.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SDIVR Z31.D, P1/M, Z31.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z10, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z10.D, P1/M, Z31.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z8.D, Z7.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z30.D, Z30.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z8.D, P1/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z9, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z9.D, P1/M, Z9.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
DUPM Z0.D, #0xfffffffe	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z31.D, Z16.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z10.D, Z17.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z12.D, [Z20, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ORR Z14.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z13.D, Z31.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X12, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z11, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z11.D, P1/M, Z31.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z15, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z15.D, P1/M, Z10.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADR Z9.D, [Z12, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z14.D, Z14.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z14.D, P1/M, Z14.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SMIN Z14.D, P1/M, Z14.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z1.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z12.D}, P0/Z, [X9, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FCMGT P2.D, P1/Z, Z1.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z9, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z9.D, P1/M, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z19.D, P2, Z11.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z11.D, P2, Z15.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z15.D, P2, Z10.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z10, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z10.D, P1/M, Z10.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SEL Z13.D, P2, Z13.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X12, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z14.D, [Z23, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z15.D}, P0/Z, [X9, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z24.D, [Z25, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z14, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z2, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z2.D, P1/M, Z2.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z24.D, [Z24, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FDIV Z9.D, P1/M, Z9.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z14.D, [Z25, Z13.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z14, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z0.D}, P0/Z, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z12.D, P1/M, Z9.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FDIV Z12.D, P1/M, Z12.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z15.D, [Z25, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z19.D, [Z28, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z15, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FSUB Z15.D, Z0.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z14.D, P1/M, Z14.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z22.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z2.D, P1/M, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z15.D, Z22.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMGT P3.D, P1/Z, Z22.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P2.D, P1/Z, Z15.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FDUP Z15.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
FSUB Z15.D, Z15.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z9.D, P1/M, Z9.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z22, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FNEG Z22.D, P1/M, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z22.D, P3, Z9.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z9, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMINNM Z9.D, P1/M, Z9.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z14.D, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z2.D, P1/M, Z15.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMINNM Z2.D, P1/M, Z2.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z0.D, P2/M, Z2.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z2.D, [Z27, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z22.D, [Z28, Z13.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z1, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z1.D, P1/M, Z1.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z1.D, [Z2, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z28, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z0.D}, P0, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z1, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z1.D, P1/M, Z1.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z8.D, P1/M, Z8.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z2.D, [Z2, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z22.D, [Z22, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z19, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z22.D}, P0/Z, [V22.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z1.D}, P0/Z, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z9.D, Z2.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z19.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z22.D, P1/M, Z22.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z1.D, P1/M, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z9.D, Z19.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMGT P4.D, P1/Z, Z19.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P2.D, P1/Z, Z9.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
AND P3.B, P0/Z, P0.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z24.D}, P3/Z, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z19.D}, P3/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z19.D, Z19.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z24, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z24.D, P1/M, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z19.D, P1/M, Z19.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FSUBR Z19.D, P1/M, Z19.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z24, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FNEG Z24.D, P1/M, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z19.D, P4, Z19.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z24.D, Z22.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z1.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMINNM Z1.D, P1/M, Z1.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z22.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMINNM Z1.D, P1/M, Z1.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z2.D, P2/M, Z19.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z1.D, [Z29, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z1, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z0.D}, P0, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P0.D, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 4280c4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.3+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.3]
Source file and lines	advec_cell.cpp:66-110
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66-110
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions).

Details

71% of VPU instructions are used in vector version (process two or more data elements in vector registers):

42% of VPU loads are used in vector version.
41% of VPU addition or subtraction instructions are used in vector version.
68% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 62.25 to 50.00 cycles (1.25x speedup).

FMA

Detected 20 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 21 occurrence(s)
Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 116 FP arithmetical operations:

48: addition or subtraction (20 inside FMA instructions)
56: multiply (20 inside FMA instructions)
12: divide

The binary loop is loading 482 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	126
nb uops	126
loop length	504
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	7
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	0.78

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.75 cycles
front end	15.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	2.00	0.50	52.00	52.00	6.00	6.00	5.83	5.50	5.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	2.00	0.50	52.00	52.00	10.50	10.50	5.83	5.50	5.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	21.85-62.25
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	15.75
Dispatch	52.00
DIV/SQRT	21.85-62.25
Data deps.	0.00
Overall L1	52.00-62.25

Vectorization ratios

INT

all	57%
load	42%
store	100%
mul	100%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	53%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	71%
load	42%
store	100%
mul	100%
add-sub	41%
fma	100%
div/sqrt	100%
other	68%

Vector efficiency ratios

INT

all	78%
load	57%
store	100%
mul	100%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	93%

all	97%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	94%

INT+FP

all	85%
load	57%
store	100%
mul	100%
add-sub	55%
fma	100%
div/sqrt	100%
other	94%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 62.25 cycles. At this rate:

8% of peak load performance is reached (7.75 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.03 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4280c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SEL Z31.D, P0, Z4.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SDIVR Z31.D, P1/M, Z31.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z10, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z10.D, P1/M, Z31.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z8.D, Z7.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z30.D, Z30.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z8.D, P1/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z9, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z9.D, P1/M, Z9.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
DUPM Z0.D, #0xfffffffe	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z31.D, Z16.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z10.D, Z17.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z12.D, [Z20, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ORR Z14.D, Z31.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z13.D, Z31.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X12, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z11, Z31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z11.D, P1/M, Z31.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z15, Z10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z15.D, P1/M, Z10.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADR Z9.D, [Z12, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z14.D, Z14.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z14.D, P1/M, Z14.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SMIN Z14.D, P1/M, Z14.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z1.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z12.D}, P0/Z, [X9, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FCMGT P2.D, P1/Z, Z1.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z9, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z9.D, P1/M, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z19.D, P2, Z11.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z11.D, P2, Z15.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z15.D, P2, Z10.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z10, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z10.D, P1/M, Z10.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SEL Z13.D, P2, Z13.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X12, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z14.D, [Z23, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z15.D}, P0/Z, [X9, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z24.D, [Z25, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z14, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z2, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z2.D, P1/M, Z2.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z24.D, [Z24, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FDIV Z9.D, P1/M, Z9.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z14.D, [Z25, Z13.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z14, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z0.D}, P0/Z, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z12.D, P1/M, Z9.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FDIV Z12.D, P1/M, Z12.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z15.D, [Z25, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z19.D, [Z28, Z19.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z15, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FSUB Z15.D, Z0.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z14.D, P1/M, Z14.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z22.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z2.D, P1/M, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z15.D, Z22.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMGT P3.D, P1/Z, Z22.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P2.D, P1/Z, Z15.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FDUP Z15.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
FSUB Z15.D, Z15.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUBR Z9.D, P1/M, Z9.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z22, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FNEG Z22.D, P1/M, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z22.D, P3, Z9.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z9, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMINNM Z9.D, P1/M, Z9.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z14.D, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z2.D, P1/M, Z15.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z2.D, Z2.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMINNM Z2.D, P1/M, Z2.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z0.D, P2/M, Z2.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z2.D, [Z27, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z22.D, [Z28, Z13.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z1, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z1.D, P1/M, Z1.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z1.D, [Z2, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z28, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z0.D}, P0, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z1, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z1.D, P1/M, Z1.D, Z8.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z8.D, P1/M, Z8.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z2.D, [Z2, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z22.D, [Z22, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z19, Z1.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z22.D}, P0/Z, [V22.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z1.D}, P0/Z, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z9.D, Z2.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z19.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z22.D, P1/M, Z22.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z1.D, P1/M, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z9.D, Z19.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMGT P4.D, P1/Z, Z19.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FCMGT P2.D, P1/Z, Z9.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
AND P3.B, P0/Z, P0.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z24.D}, P3/Z, [V24.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z19.D}, P3/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z19.D, Z19.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z24, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z24.D, P1/M, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIVR Z19.D, P1/M, Z19.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FSUBR Z19.D, P1/M, Z19.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z24, Z19	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FNEG Z24.D, P1/M, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z19.D, P4, Z19.D, Z24.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z24.D, Z22.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z24.D, P1/M, Z1.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMINNM Z1.D, P1/M, Z1.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z22.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMINNM Z1.D, P1/M, Z1.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMLA Z2.D, P2/M, Z19.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z1.D, [Z29, Z31.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z1.D, [Z1, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z0.D}, P0, [V1.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P0.D, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 4280c4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.3+0x194>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code