OV - exec - Loop 155

	Loop Id: 155	Module: exec	Source: advec_cell.cpp:209-216 [...]	Coverage: 4.00%

0x428f20 SEL	Z27.D, P1, Z4.D, Z19.D

0x428f24 ADD	X10, X10, X8

0x428f28 SDIVR	Z27.D, P0/M, Z27.D, Z26.D

0x428f2c ADD	Z28.D, Z7.D, Z27.D

0x428f30 MOVPRFX	Z29, Z26

0x428f34 MLS	Z29.D, P0/M, Z27.D, Z4.D

0x428f38 ADD	Z27.D, Z27.D, Z18.D

0x428f3c ADD	Z26.D, Z26.D, Z17.D

0x428f40 SXTW	Z28.D, P0/M, Z28.D

0x428f44 SXTW	Z27.D, P0/M, Z27.D

0x428f48 MOVPRFX	Z8, Z1

0x428f4c MUL	Z8.D, P0/M, Z8.D, Z28.D

0x428f50 MOVPRFX	Z30, Z0

0x428f54 MUL	Z30.D, P0/M, Z30.D, Z28.D

0x428f58 MOVPRFX	Z11, Z2

0x428f5c MUL	Z11.D, P0/M, Z11.D, Z27.D

0x428f60 MOVPRFX	Z12, Z5

0x428f64 MUL	Z12.D, P0/M, Z12.D, Z28.D

0x428f68 ADD	Z29.D, Z16.D, Z29.D

0x428f6c ADR	Z9.D, [Z21, Z29.D,SXTW #3]    [8]

0x428f70 ADR	Z31.D, [Z20, Z29.D,SXTW #3]    [4]

0x428f74 ADR	Z10.D, [Z22, Z29.D,SXTW #3]    [12]

0x428f78 ADR	Z13.D, [Z24, Z29.D,SXTW #3]    [17]

0x428f7c ADR	Z8.D, [Z9, Z8.D,LSL #3]    [14]

0x428f80 MOVPRFX	Z9, Z2

0x428f84 MUL	Z9.D, P0/M, Z9.D, Z28.D

0x428f88 ADR	Z30.D, [Z31, Z30.D,LSL #3]    [9]

0x428f8c ADR	Z12.D, [Z13, Z12.D,LSL #3]    [15]

0x428f90 ADR	Z9.D, [Z10, Z9.D,LSL #3]    [3]

0x428f94 ADR	Z10.D, [Z10, Z11.D,LSL #3]    [3]

0x428f98 LD1D	{Z31.D}, P1/Z, [V30.D]    [5]

0x428f9c LD1D	{Z8.D}, P1/Z, [V8.D]    [10]

0x428fa0 ADR	Z11.D, [Z23, Z29.D,SXTW #3]    [16]

0x428fa4 LD1D	{Z12.D}, P1/Z, [V12.D]    [11]

0x428fa8 ADR	Z29.D, [Z25, Z29.D,SXTW #3]    [18]

0x428fac FMUL	Z31.D, Z8.D, Z31.D

0x428fb0 LD1D	{Z9.D}, P1/Z, [V9.D]    [13]

0x428fb4 LD1D	{Z10.D}, P1/Z, [V10.D]    [2]

0x428fb8 FADD	Z9.D, Z9.D, Z31.D

0x428fbc FSUB	Z9.D, Z9.D, Z10.D

0x428fc0 MOVPRFX	Z10, Z3

0x428fc4 MUL	Z10.D, P0/M, Z10.D, Z28.D

0x428fc8 MUL	Z28.D, P0/M, Z28.D, Z6.D

0x428fcc ADR	Z10.D, [Z11, Z10.D,LSL #3]    [7]

0x428fd0 ADR	Z28.D, [Z29, Z28.D,LSL #3]    [21]

0x428fd4 LD1D	{Z11.D}, P1/Z, [V10.D]    [1]

0x428fd8 LD1D	{Z28.D}, P1/Z, [V28.D]    [20]

0x428fdc FMAD	Z31.D, P0/M, Z11.D, Z12.D

0x428fe0 MOVPRFX	Z11, Z5

0x428fe4 MUL	Z11.D, P0/M, Z11.D, Z27.D

0x428fe8 MUL	Z27.D, P0/M, Z27.D, Z6.D

0x428fec FADD	Z28.D, Z28.D, Z8.D

0x428ff0 ADR	Z11.D, [Z13, Z11.D,LSL #3]    [15]

0x428ff4 ADR	Z27.D, [Z29, Z27.D,LSL #3]    [21]

0x428ff8 LD1D	{Z11.D}, P1/Z, [V11.D]    [6]

0x428ffc LD1D	{Z27.D}, P1/Z, [V27.D]    [19]

0x429000 FSUB	Z31.D, Z31.D, Z11.D

0x429004 FSUB	Z27.D, Z28.D, Z27.D

0x429008 FDIV	Z31.D, P0/M, Z31.D, Z9.D

0x42900c FDIVR	Z27.D, P0/M, Z27.D, Z9.D

0x429010 ST1D	{Z27.D}, P1, [V30.D]    [5]

0x429014 ST1D	{Z31.D}, P1, [V10.D]    [1]

0x429018 WHILELO	P1.D, X10, X9

0x42901c B.MI	428f20

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 209 - 216

--------------------------------------------------------------------------------

209:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

210:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

211:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

212:         double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1);

213:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s;

214:         double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1);

215:         density1(i, j) = post_mass_s / advec_vol_s;

216:         energy1(i, j) = post_ener_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Module
►98.43+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.29 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.93
Bottlenecks	P6, P8,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.13]
Source	advec_cell.cpp:209-216,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.00 - 48.17
CQA cycles if no scalar integer	25.00 - 48.17
CQA cycles if FP arith vectorized	25.00 - 48.17
CQA cycles if fully vectorized	19.38 - 48.17
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	25.00
P7 cycles	25.00
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	3.67
P11 cycles	3.67
P12 cycles	3.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	14.86 - 48.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	64.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.60 - 0.83
Nb FLOP add-sub	20.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.35 - 14.15
Bytes prefetched	0.00
Bytes loaded	289.88
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	15.00
Stride indirect	6.00
Vectorization ratio all	62.30
Vectorization ratio load	37.50
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	40.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	27.27
Vector-efficiency ratio all	81.56
Vector-efficiency ratio load	53.13
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	55.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.29 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.93
Bottlenecks	P6, P8,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.13]
Source	advec_cell.cpp:209-216,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.00 - 48.17
CQA cycles if no scalar integer	25.00 - 48.17
CQA cycles if FP arith vectorized	25.00 - 48.17
CQA cycles if fully vectorized	19.38 - 48.17
Front-end cycles	8.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	25.00
P7 cycles	25.00
P8 cycles	5.50
P9 cycles	5.50
P10 cycles	3.67
P11 cycles	3.67
P12 cycles	3.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	14.86 - 48.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	64.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.60 - 0.83
Nb FLOP add-sub	20.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.35 - 14.15
Bytes prefetched	0.00
Bytes loaded	289.88
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	15.00
Stride indirect	6.00
Vectorization ratio all	62.30
Vectorization ratio load	37.50
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	40.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	27.27
Vector-efficiency ratio all	81.56
Vector-efficiency ratio load	53.13
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	55.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.13]
Source file and lines	advec_cell.cpp:209-216
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209-216
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 81% of vector register length is used (average across all VPU instructions).

Details

62% of VPU instructions are used in vector version (process two or more data elements in vector registers):

37% of VPU loads are used in vector version.
40% of VPU addition or subtraction instructions are used in vector version.
27% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.17 to 23.50 cycles (2.05x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 15 occurrence(s)
Irregular (variable stride) or indirect: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
8: divide

The binary loop is loading 289 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	64
nb uops	64
loop length	256
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	8
used z registers	30
nb stack references	0
ADD-SUB / MUL ratio	5.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	25.00	25.00	5.50	5.50	3.67	3.67	3.67	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	25.00	25.00	5.50	5.50	3.67	3.67	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-48.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.00
Dispatch	25.00
DIV/SQRT	14.86-48.17
Data deps.	2.00
Overall L1	25.00-48.17

Vectorization ratios

INT

all	55%
load	37%
store	100%
mul	100%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	62%
load	37%
store	100%
mul	100%
add-sub	40%
fma	100%
div/sqrt	100%
other	27%

Vector efficiency ratios

INT

all	78%
load	53%
store	100%
mul	100%
add-sub	43%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	81%
load	53%
store	100%
mul	100%
add-sub	55%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.17 cycles. At this rate:

6% of peak load performance is reached (6.02 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 428f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z27.D, P1, Z4.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z27.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z28.D, Z7.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z29.D, P0/M, Z27.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z27.D, Z27.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z26.D, Z26.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SXTW Z27.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z8, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z8.D, P0/M, Z8.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z30, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z30.D, P0/M, Z30.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z11, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z11.D, P0/M, Z11.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z12, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z29.D, Z16.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z9.D, [Z21, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z22, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z24, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z9, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z9, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z9.D, P0/M, Z9.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z30.D, [Z31, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z12.D, [Z13, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z9.D, [Z10, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z10, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z31.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z8.D}, P1/Z, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z11.D, [Z23, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z12.D}, P1/Z, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z29.D, [Z25, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z31.D, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z9.D}, P1/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z10.D}, P1/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z9.D, Z9.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z9.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z10, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z10.D, P0/M, Z10.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z28.D, P0/M, Z28.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z10.D, [Z11, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z28.D, [Z29, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z11.D}, P1/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z28.D}, P1/Z, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z31.D, P0/M, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z11.D, P0/M, Z11.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z27.D, P0/M, Z27.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FADD Z28.D, Z28.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z11.D, [Z13, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z29, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z11.D}, P1/Z, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z31.D, Z31.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z27.D, Z28.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z31.D, P0/M, Z31.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z27.D, P0/M, Z27.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ST1D {Z27.D}, P1, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
ST1D {Z31.D}, P1, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 428f20 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.13+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.13]
Source file and lines	advec_cell.cpp:209-216
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209-216
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 81% of vector register length is used (average across all VPU instructions).

Details

62% of VPU instructions are used in vector version (process two or more data elements in vector registers):

37% of VPU loads are used in vector version.
40% of VPU addition or subtraction instructions are used in vector version.
27% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.17 to 23.50 cycles (2.05x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 15 occurrence(s)
Irregular (variable stride) or indirect: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

24: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)
8: divide

The binary loop is loading 289 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	64
nb uops	64
loop length	256
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	8
used z registers	30
nb stack references	0
ADD-SUB / MUL ratio	5.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	25.00	25.00	5.50	5.50	3.67	3.67	3.67	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	25.00	25.00	5.50	5.50	3.67	3.67	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-48.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.00
Dispatch	25.00
DIV/SQRT	14.86-48.17
Data deps.	2.00
Overall L1	25.00-48.17

Vectorization ratios

INT

all	55%
load	37%
store	100%
mul	100%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	62%
load	37%
store	100%
mul	100%
add-sub	40%
fma	100%
div/sqrt	100%
other	27%

Vector efficiency ratios

INT

all	78%
load	53%
store	100%
mul	100%
add-sub	43%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	81%
load	53%
store	100%
mul	100%
add-sub	55%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.17 cycles. At this rate:

6% of peak load performance is reached (6.02 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 428f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z27.D, P1, Z4.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z27.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z28.D, Z7.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z29.D, P0/M, Z27.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z27.D, Z27.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z26.D, Z26.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SXTW Z27.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z8, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z8.D, P0/M, Z8.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z30, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z30.D, P0/M, Z30.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z11, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z11.D, P0/M, Z11.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z12, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z29.D, Z16.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z9.D, [Z21, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z22, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z24, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z9, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z9, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z9.D, P0/M, Z9.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z30.D, [Z31, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z12.D, [Z13, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z9.D, [Z10, Z9.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z10, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z31.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z8.D}, P1/Z, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z11.D, [Z23, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z12.D}, P1/Z, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z29.D, [Z25, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z31.D, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z9.D}, P1/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z10.D}, P1/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z9.D, Z9.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z9.D, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z10, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z10.D, P0/M, Z10.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z28.D, P0/M, Z28.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z10.D, [Z11, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z28.D, [Z29, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z11.D}, P1/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z28.D}, P1/Z, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z31.D, P0/M, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z11, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z11.D, P0/M, Z11.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z27.D, P0/M, Z27.D, Z6.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FADD Z28.D, Z28.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z11.D, [Z13, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z29, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z11.D}, P1/Z, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z31.D, Z31.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z27.D, Z28.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z31.D, P0/M, Z31.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z27.D, P0/M, Z27.D, Z9.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ST1D {Z27.D}, P1, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
ST1D {Z31.D}, P1, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 428f20 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.13+0x160>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code