OV - exec - Loop 161

	Loop Id: 161	Module: exec	Source: advec_mom.cpp:96-100 [...]	Coverage: 2.69%

0x429f6c SEL	Z27.D, P1, Z5.D, Z19.D

0x429f70 ADD	X10, X10, X8

0x429f74 SDIVR	Z27.D, P0/M, Z27.D, Z26.D

0x429f78 ADD	Z28.D, Z6.D, Z27.D

0x429f7c MOVPRFX	Z29, Z26

0x429f80 MLS	Z29.D, P0/M, Z27.D, Z5.D

0x429f84 ADD	Z27.D, Z16.D, Z27.D

0x429f88 ADD	Z26.D, Z26.D, Z17.D

0x429f8c SXTW	Z27.D, P0/M, Z27.D

0x429f90 SXTW	Z28.D, P0/M, Z28.D

0x429f94 MOVPRFX	Z31, Z0

0x429f98 MUL	Z31.D, P0/M, Z31.D, Z27.D

0x429f9c MUL	Z27.D, P0/M, Z27.D, Z1.D

0x429fa0 MOVPRFX	Z12, Z0

0x429fa4 MUL	Z12.D, P0/M, Z12.D, Z28.D

0x429fa8 MOVPRFX	Z13, Z1

0x429fac MUL	Z13.D, P0/M, Z13.D, Z28.D

0x429fb0 ADD	Z30.D, Z7.D, Z29.D

0x429fb4 ADD	Z29.D, Z29.D, Z18.D

0x429fb8 ADR	Z8.D, [Z20, Z30.D,SXTW #3]    [3]

0x429fbc ADR	Z10.D, [Z21, Z30.D,SXTW #3]    [5]

0x429fc0 ADR	Z14.D, [Z20, Z29.D,SXTW #3]    [3]

0x429fc4 ADR	Z15.D, [Z21, Z29.D,SXTW #3]    [5]

0x429fc8 ADR	Z29.D, [Z24, Z29.D,SXTW #3]    [16]

0x429fcc ADR	Z9.D, [Z8, Z31.D,LSL #3]    [11]

0x429fd0 ADR	Z11.D, [Z10, Z27.D,LSL #3]    [2]

0x429fd4 ADR	Z8.D, [Z8, Z12.D,LSL #3]    [11]

0x429fd8 ADR	Z10.D, [Z10, Z13.D,LSL #3]    [2]

0x429fdc ADR	Z31.D, [Z14, Z31.D,LSL #3]    [15]

0x429fe0 ADR	Z27.D, [Z15, Z27.D,LSL #3]    [17]

0x429fe4 LD1D	{Z9.D}, P1/Z, [V9.D]    [13]

0x429fe8 LD1D	{Z11.D}, P1/Z, [V11.D]    [4]

0x429fec LD1D	{Z8.D}, P1/Z, [V8.D]    [10]

0x429ff0 LD1D	{Z10.D}, P1/Z, [V10.D]    [1]

0x429ff4 LD1D	{Z31.D}, P1/Z, [V31.D]    [8]

0x429ff8 LD1D	{Z27.D}, P1/Z, [V27.D]    [19]

0x429ffc FMUL	Z9.D, Z11.D, Z9.D

0x42a000 FMAD	Z8.D, P0/M, Z10.D, Z9.D

0x42a004 ADR	Z9.D, [Z14, Z12.D,LSL #3]    [15]

0x42a008 FMAD	Z27.D, P0/M, Z31.D, Z8.D

0x42a00c ADR	Z31.D, [Z15, Z13.D,LSL #3]    [17]

0x42a010 LD1D	{Z9.D}, P1/Z, [V9.D]    [12]

0x42a014 ADR	Z8.D, [Z23, Z30.D,SXTW #3]    [14]

0x42a018 LD1D	{Z31.D}, P1/Z, [V31.D]    [7]

0x42a01c FMLA	Z27.D, P0/M, Z31.D, Z9.D

0x42a020 MOVPRFX	Z31, Z2

0x42a024 MUL	Z31.D, P0/M, Z31.D, Z28.D

0x42a028 FMUL	Z27.D, Z27.D, Z22.D

0x42a02c ADR	Z31.D, [Z8, Z31.D,LSL #3]    [9]

0x42a030 ST1D	{Z27.D}, P1, [V31.D]    [6]

0x42a034 MOVPRFX	Z31, Z3

0x42a038 MUL	Z31.D, P0/M, Z31.D, Z28.D

0x42a03c MUL	Z28.D, P0/M, Z28.D, Z4.D

0x42a040 ADR	Z29.D, [Z29, Z31.D,LSL #3]    [24]

0x42a044 LD1D	{Z29.D}, P1/Z, [V29.D]    [23]

0x42a048 FSUB	Z27.D, Z27.D, Z29.D

0x42a04c ADR	Z29.D, [Z24, Z30.D,SXTW #3]    [16]

0x42a050 ADR	Z29.D, [Z29, Z31.D,LSL #3]    [22]

0x42a054 LD1D	{Z29.D}, P1/Z, [V29.D]    [21]

0x42a058 FADD	Z27.D, Z27.D, Z29.D

0x42a05c ADR	Z29.D, [Z25, Z30.D,SXTW #3]    [18]

0x42a060 ADR	Z28.D, [Z29, Z28.D,LSL #3]    [25]

0x42a064 ST1D	{Z27.D}, P1, [V28.D]    [20]

0x42a068 WHILELO	P1.D, X10, X9

0x42a06c B.MI	429f6c

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 96 - 100

--------------------------------------------------------------------------------

96:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

97:         for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) {

98:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

99:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

100:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j);

Coverage (%)	Name	Module
►98.37+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.43 - 1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.9]
Source	context.h:69-69,advec_mom.cpp:96-100
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.00
CQA cycles if no scalar integer	25.00
CQA cycles if FP arith vectorized	25.00
CQA cycles if fully vectorized	17.50 - 20.00
Front-end cycles	8.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	25.00
P7 cycles	25.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	65.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.60
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.46
Bytes prefetched	0.00
Bytes loaded	322.50
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	20.00
Stride indirect	5.00
Vectorization ratio all	58.06
Vectorization ratio load	33.33
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	28.57
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	75.81
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	46.43
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.43 - 1.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.9]
Source	context.h:69-69,advec_mom.cpp:96-100
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	25.00
CQA cycles if no scalar integer	25.00
CQA cycles if FP arith vectorized	25.00
CQA cycles if fully vectorized	17.50 - 20.00
Front-end cycles	8.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	25.00
P7 cycles	25.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	65.00
Nb uops	65.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.60
Nb FLOP add-sub	8.00
Nb FLOP mul	8.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.46
Bytes prefetched	0.00
Bytes loaded	322.50
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	20.00
Stride indirect	5.00
Vectorization ratio all	58.06
Vectorization ratio load	33.33
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	28.57
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	75.81
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	46.43
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.9]
Source file and lines	advec_mom.cpp:96-100
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96-100

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 75% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 25.00 to 20.00 cycles (1.25x speedup).

Details

58% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
28% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 20 occurrence(s)
Irregular (variable stride) or indirect: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

20: addition or subtraction (12 inside FMA instructions)
20: multiply (12 inside FMA instructions)

The binary loop is loading 322 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	65
loop length	260
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	8
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	25.00	25.00	6.00	6.00	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	25.00	25.00	6.00	6.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.13
Dispatch	25.00
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	25.00

Vectorization ratios

INT

all	52%
load	33%
store	100%
mul	100%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	58%
load	33%
store	100%
mul	100%
add-sub	28%
fma	100%
div/sqrt	100%
other	33%

Vector efficiency ratios

INT

all	72%
load	50%
store	100%
mul	100%
add-sub	42%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	50%
store	100%
mul	100%
add-sub	46%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.00 cycles. At this rate:

13% of peak load performance is reached (12.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 429f6c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z27.D, P1, Z5.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z27.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z28.D, Z6.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z29.D, P0/M, Z27.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z27.D, Z16.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z26.D, Z26.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z27.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z31.D, P0/M, Z31.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z27.D, P0/M, Z27.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z12, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z13, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P0/M, Z13.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z30.D, Z7.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z29.D, Z29.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z8.D, [Z20, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z21, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z21, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z24, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z9.D, [Z8, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z11.D, [Z10, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z8, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z10, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z14, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z15, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z9.D}, P1/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z11.D}, P1/Z, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z8.D}, P1/Z, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z10.D}, P1/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z31.D}, P1/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z9.D, Z11.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z8.D, P0/M, Z10.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z9.D, [Z14, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMAD Z27.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z31.D, [Z15, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z9.D}, P1/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z8.D, [Z23, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z31.D}, P1/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z27.D, P0/M, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z31, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z31.D, P0/M, Z31.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMUL Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z31.D, [Z8, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z27.D}, P1, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z31, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z31.D, P0/M, Z31.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z28.D, P0/M, Z28.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z29.D, [Z29, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z29.D}, P1/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z27.D, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z29.D, [Z24, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z29, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z29.D}, P1/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z27.D, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z29.D, [Z25, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z28.D, [Z29, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z27.D}, P1, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 429f6c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.9+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.9]
Source file and lines	advec_mom.cpp:96-100
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96-100

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

58% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
28% of VPU addition or subtraction instructions are used in vector version.
33% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 20 occurrence(s)
Irregular (variable stride) or indirect: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

20: addition or subtraction (12 inside FMA instructions)
20: multiply (12 inside FMA instructions)

The binary loop is loading 322 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	65
nb uops	65
loop length	260
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	8
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	25.00	25.00	6.00	6.00	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	25.00	25.00	6.00	6.00	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	8.13
Dispatch	25.00
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	25.00

Vectorization ratios

INT

all	52%
load	33%
store	100%
mul	100%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	58%
load	33%
store	100%
mul	100%
add-sub	28%
fma	100%
div/sqrt	100%
other	33%

Vector efficiency ratios

INT

all	72%
load	50%
store	100%
mul	100%
add-sub	42%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	75%
load	50%
store	100%
mul	100%
add-sub	46%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 25.00 cycles. At this rate:

13% of peak load performance is reached (12.90 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.56 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 429f6c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z27.D, P1, Z5.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z27.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z28.D, Z6.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z29.D, P0/M, Z27.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z27.D, Z16.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z26.D, Z26.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z27.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SXTW Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z31, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z31.D, P0/M, Z31.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z27.D, P0/M, Z27.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z12, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z13, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P0/M, Z13.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z30.D, Z7.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z29.D, Z29.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z8.D, [Z20, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z21, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z20, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z15.D, [Z21, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z24, Z29.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z9.D, [Z8, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z11.D, [Z10, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z8, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z10, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z14, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z15, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z9.D}, P1/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z11.D}, P1/Z, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z8.D}, P1/Z, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z10.D}, P1/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z31.D}, P1/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z9.D, Z11.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAD Z8.D, P0/M, Z10.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z9.D, [Z14, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMAD Z27.D, P0/M, Z31.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z31.D, [Z15, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z9.D}, P1/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z8.D, [Z23, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z31.D}, P1/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z27.D, P0/M, Z31.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z31, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z31.D, P0/M, Z31.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMUL Z27.D, Z27.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z31.D, [Z8, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z27.D}, P1, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
MOVPRFX Z31, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z31.D, P0/M, Z31.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z28.D, P0/M, Z28.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z29.D, [Z29, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z29.D}, P1/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z27.D, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z29.D, [Z24, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z29, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z29.D}, P1/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z27.D, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z29.D, [Z25, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z28.D, [Z29, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z27.D}, P1, [V28.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 429f6c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.9+0x14c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code