OV - exec - Loop 166

	Loop Id: 166	Module: exec	Source: advec_mom.cpp:181-211 [...]	Coverage: 3.87%

0x42ab40 SEL	Z26.D, P1, Z4.D, Z16.D

0x42ab44 ADD	X11, X11, X8

0x42ab48 SDIVR	Z26.D, P0/M, Z26.D, Z25.D

0x42ab4c ADD	Z27.D, Z5.D, Z26.D

0x42ab50 MSB	Z26.D, P0/M, Z4.D, Z25.D

0x42ab54 ADD	Z25.D, Z25.D, Z7.D

0x42ab58 MOVPRFX	Z28, Z27

0x42ab5c SXTW	Z28.D, P0/M, Z27.D

0x42ab60 ORR	Z9.D, Z27.D, Z27.D

0x42ab64 ADD	Z8.D, Z27.D, Z19.D

0x42ab68 MOVPRFX	Z29, Z0

0x42ab6c MUL	Z29.D, P0/M, Z29.D, Z28.D

0x42ab70 ADD	Z9.D, Z9.D, #2

0x42ab74 ADD	Z26.D, Z6.D, Z26.D

0x42ab78 ADR	Z30.D, [Z17, Z26.D,SXTW #3]    [14]

0x42ab7c ADR	Z12.D, [Z20, Z26.D,SXTW #3]    [2]

0x42ab80 ADR	Z29.D, [Z30, Z29.D,LSL #3]    [3]

0x42ab84 ORR	Z30.D, Z27.D, Z27.D

0x42ab88 LD1D	{Z29.D}, P1/Z, [V29.D]    [15]

0x42ab8c ADD	Z30.D, Z30.D, #1

0x42ab90 MOVPRFX	Z31, Z30

0x42ab94 SXTW	Z31.D, P0/M, Z30.D

0x42ab98 FCMLT	P2.D, P0/Z, Z29.D, #0.0000000

0x42ab9c SEL	Z10.D, P2, Z28.D, Z31.D

0x42aba0 SEL	Z31.D, P2, Z31.D, Z28.D

0x42aba4 SEL	Z30.D, P2, Z30.D, Z8.D

0x42aba8 SEL	Z8.D, P2, Z9.D, Z8.D

0x42abac MOVPRFX	Z9, Z29

0x42abb0 FABS	Z9.D, P0/M, Z29.D

0x42abb4 MUL	Z28.D, P0/M, Z28.D, Z3.D

0x42abb8 MOVPRFX	Z11, Z1

0x42abbc MUL	Z11.D, P0/M, Z11.D, Z31.D

0x42abc0 SXTW	Z8.D, P0/M, Z8.D

0x42abc4 MUL	Z31.D, P0/M, Z31.D, Z2.D

0x42abc8 MUL	Z10.D, P0/M, Z10.D, Z2.D

0x42abcc MUL	Z8.D, P0/M, Z8.D, Z2.D

0x42abd0 ADR	Z11.D, [Z12, Z11.D,LSL #3]    [9]

0x42abd4 LD1D	{Z11.D}, P1/Z, [V11.D]    [5]

0x42abd8 FDIV	Z9.D, P0/M, Z9.D, Z11.D

0x42abdc ADR	Z11.D, [Z21, Z26.D,SXTW #3]    [6]

0x42abe0 ADR	Z26.D, [Z24, Z26.D,SXTW #3]    [11]

0x42abe4 ADR	Z31.D, [Z11, Z31.D,LSL #3]    [4]

0x42abe8 ADR	Z8.D, [Z11, Z8.D,LSL #3]    [4]

0x42abec ADR	Z10.D, [Z11, Z10.D,LSL #3]    [4]

0x42abf0 ADR	Z26.D, [Z26, Z28.D,LSL #3]    [13]

0x42abf4 LD1D	{Z31.D}, P1/Z, [V31.D]    [7]

0x42abf8 LD1D	{Z8.D}, P1/Z, [V8.D]    [8]

0x42abfc LD1D	{Z10.D}, P1/Z, [V10.D]    [1]

0x42ac00 FSUB	Z12.D, Z31.D, Z8.D

0x42ac04 FSUB	Z11.D, Z10.D, Z31.D

0x42ac08 FABD	Z8.D, P0/M, Z8.D, Z31.D

0x42ac0c FABD	Z10.D, P0/M, Z10.D, Z31.D

0x42ac10 FMUL	Z12.D, Z11.D, Z12.D

0x42ac14 FCMGT	P4.D, P0/Z, Z11.D, #0.0000000

0x42ac18 FSUB	Z11.D, Z22.D, Z9.D

0x42ac1c FMUL	Z11.D, Z10.D, Z11.D

0x42ac20 FCMGT	P2.D, P0/Z, Z12.D, #0.0000000

0x42ac24 MOVPRFX	Z12, Z8

0x42ac28 FMLA	Z12.D, P0/M, Z9.D, Z8.D

0x42ac2c FSUBR	Z9.D, P0/M, Z9.D, #0.0000000

0x42ac30 AND	P3.B, P1/Z, P1.B, P2.B

0x42ac34 LD1D	{Z27.D}, P3/Z, [X9, Z27.D,SXTW #3]    [10]

0x42ac38 LD1D	{Z30.D}, P3/Z, [X9, Z30.D,SXTW #3]    [10]

0x42ac3c FDIV	Z11.D, P0/M, Z11.D, Z27.D

0x42ac40 FDIVR	Z30.D, P0/M, Z30.D, Z12.D

0x42ac44 FMUL	Z27.D, Z27.D, Z23.D

0x42ac48 FADD	Z30.D, Z30.D, Z11.D

0x42ac4c FMUL	Z27.D, Z27.D, Z30.D

0x42ac50 FMINNM	Z27.D, P0/M, Z27.D, Z8.D

0x42ac54 FMINNM	Z27.D, P0/M, Z27.D, Z10.D

0x42ac58 MOVPRFX	Z30, Z27

0x42ac5c FNEG	Z30.D, P0/M, Z27.D

0x42ac60 SEL	Z27.D, P4, Z27.D, Z30.D

0x42ac64 SEL	Z27.D, P2, Z27.D, Z18.D

0x42ac68 FMAD	Z27.D, P0/M, Z9.D, Z31.D

0x42ac6c FMUL	Z27.D, Z27.D, Z29.D

0x42ac70 ST1D	{Z27.D}, P1, [V26.D]    [12]

0x42ac74 WHILELO	P1.D, X11, X10

0x42ac78 B.MI	42ab40

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 181 - 211

--------------------------------------------------------------------------------

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

Coverage (%)	Name	Module
►98.42+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.86
Bottlenecks	P6, P8,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.19]
Source	context.h:69-69,advec_mom.cpp:181-211
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	33.50 - 62.25
CQA cycles if no scalar integer	33.50 - 62.25
CQA cycles if FP arith vectorized	33.50 - 62.25
CQA cycles if fully vectorized	29.75 - 62.25
Front-end cycles	9.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	2.00
P5 cycles	0.25
P6 cycles	33.50
P7 cycles	33.50
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	2.83
P11 cycles	2.50
P12 cycles	2.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	21.85 - 62.25
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	79.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.03 - 1.09
Nb FLOP add-sub	20.00
Nb FLOP mul	20.00
Nb FLOP fma	8.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.13 - 7.68
Bytes prefetched	0.00
Bytes loaded	225.25
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	11.00
Stride indirect	4.00
Vectorization ratio all	77.63
Vectorization ratio load	41.18
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	52.38
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	75.86
Vector-efficiency ratio all	88.98
Vector-efficiency ratio load	55.88
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	64.29
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	96.98

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.13 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.86
Bottlenecks	P6, P8,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.19]
Source	context.h:69-69,advec_mom.cpp:181-211
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	33.50 - 62.25
CQA cycles if no scalar integer	33.50 - 62.25
CQA cycles if FP arith vectorized	33.50 - 62.25
CQA cycles if fully vectorized	29.75 - 62.25
Front-end cycles	9.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	2.00
P5 cycles	0.25
P6 cycles	33.50
P7 cycles	33.50
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	2.83
P11 cycles	2.50
P12 cycles	2.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	21.85 - 62.25
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	79.00
Nb uops	79.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.03 - 1.09
Nb FLOP add-sub	20.00
Nb FLOP mul	20.00
Nb FLOP fma	8.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.13 - 7.68
Bytes prefetched	0.00
Bytes loaded	225.25
Bytes stored	32.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	11.00
Stride indirect	4.00
Vectorization ratio all	77.63
Vectorization ratio load	41.18
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	52.38
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	75.86
Vector-efficiency ratio all	88.98
Vector-efficiency ratio load	55.88
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	64.29
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	96.98

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.19]
Source file and lines	advec_mom.cpp:181-211
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181-211

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions).

Details

77% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
52% of VPU addition or subtraction instructions are used in vector version.
75% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 62.25 to 31.50 cycles (1.98x speedup).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 11 occurrence(s)
Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (8 inside FMA instructions)
28: multiply (8 inside FMA instructions)
12: divide

The binary loop is loading 225 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	79
nb uops	79
loop length	316
used w registers	0
used x registers	4
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	6
used z registers	29
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.88 cycles
front end	9.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	33.50	33.50	3.00	3.00	2.83	2.50	2.67	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	33.50	33.50	6.00	6.00	2.83	2.50	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	21.85-62.25
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.88
Dispatch	33.50
DIV/SQRT	21.85-62.25
Data deps.	2.00
Overall L1	33.50-62.25

Vectorization ratios

INT

all	67%
load	41%
store	100%
mul	100%
add-sub	37%
fma	100%
other	66%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	77%
load	41%
store	100%
mul	100%
add-sub	52%
fma	100%
div/sqrt	100%
other	75%

Vector efficiency ratios

INT

all	83%
load	55%
store	100%
mul	100%
add-sub	53%
fma	100%
other	95%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	88%
load	55%
store	100%
mul	100%
add-sub	64%
fma	100%
div/sqrt	100%
other	96%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 62.25 cycles. At this rate:

3% of peak load performance is reached (3.62 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.51 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ab40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z26.D, P1, Z4.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X11, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z26.D, P0/M, Z26.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z27.D, Z5.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MSB Z26.D, P0/M, Z4.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z25.D, Z25.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z28, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z28.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ORR Z9.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z8.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z29.D, P0/M, Z29.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z9.D, Z9.D, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z26.D, Z6.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z30.D, [Z17, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z12.D, [Z20, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z30, Z29.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ORR Z30.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z29.D}, P1/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z30.D, Z30.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z31, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z31.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P2.D, P0/Z, Z29.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
SEL Z10.D, P2, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z31.D, P2, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z30.D, P2, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z8.D, P2, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z9, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z9.D, P0/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z28.D, P0/M, Z28.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z11, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z11.D, P0/M, Z11.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SXTW Z8.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MUL Z31.D, P0/M, Z31.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z10.D, P0/M, Z10.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z8.D, P0/M, Z8.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z11.D, [Z12, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z11.D}, P1/Z, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FDIV Z9.D, P0/M, Z9.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z11.D, [Z21, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z24, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z11, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z11, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z11, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z26, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z31.D}, P1/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z8.D}, P1/Z, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z10.D}, P1/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z12.D, Z31.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z11.D, Z10.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z8.D, P0/M, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z10.D, P0/M, Z10.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z12.D, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMGT P4.D, P0/Z, Z11.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FSUB Z11.D, Z22.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z11.D, Z10.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMGT P2.D, P0/Z, Z12.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z12, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z12.D, P0/M, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FSUBR Z9.D, P0/M, Z9.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
AND P3.B, P1/Z, P1.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z27.D}, P3/Z, [X9, Z27.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z30.D}, P3/Z, [X9, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FDIV Z11.D, P0/M, Z11.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z30.D, P0/M, Z30.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z27.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z30.D, Z30.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z27.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMINNM Z27.D, P0/M, Z27.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z27.D, P0/M, Z27.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FNEG Z30.D, P0/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z27.D, P4, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z27.D, P2, Z27.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z27.D, P0/M, Z9.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z27.D, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z27.D}, P1, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 42ab40 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.19+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.19]
Source file and lines	advec_mom.cpp:181-211
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:181-211

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 88% of vector register length is used (average across all VPU instructions).

Details

77% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
52% of VPU addition or subtraction instructions are used in vector version.
75% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 62.25 to 31.50 cycles (1.98x speedup).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 11 occurrence(s)
Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (8 inside FMA instructions)
28: multiply (8 inside FMA instructions)
12: divide

The binary loop is loading 225 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	79
nb uops	79
loop length	316
used w registers	0
used x registers	4
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	6
used z registers	29
nb stack references	0
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.88 cycles
front end	9.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	2.00	0.25	33.50	33.50	3.00	3.00	2.83	2.50	2.67	0.00	0.00
cycles	0.50	0.50	0.50	0.25	2.00	0.25	33.50	33.50	6.00	6.00	2.83	2.50	2.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	21.85-62.25
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.88
Dispatch	33.50
DIV/SQRT	21.85-62.25
Data deps.	2.00
Overall L1	33.50-62.25

Vectorization ratios

INT

all	67%
load	41%
store	100%
mul	100%
add-sub	37%
fma	100%
other	66%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	77%
load	41%
store	100%
mul	100%
add-sub	52%
fma	100%
div/sqrt	100%
other	75%

Vector efficiency ratios

INT

all	83%
load	55%
store	100%
mul	100%
add-sub	53%
fma	100%
other	95%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	88%
load	55%
store	100%
mul	100%
add-sub	64%
fma	100%
div/sqrt	100%
other	96%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 62.25 cycles. At this rate:

3% of peak load performance is reached (3.62 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.51 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ab40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z26.D, P1, Z4.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X11, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z26.D, P0/M, Z26.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z27.D, Z5.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MSB Z26.D, P0/M, Z4.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z25.D, Z25.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z28, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z28.D, P0/M, Z27.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ORR Z9.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z8.D, Z27.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z29, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z29.D, P0/M, Z29.D, Z28.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z9.D, Z9.D, #2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z26.D, Z6.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z30.D, [Z17, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z12.D, [Z20, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z29.D, [Z30, Z29.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ORR Z30.D, Z27.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z29.D}, P1/Z, [V29.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z30.D, Z30.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z31, Z30	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z31.D, P0/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
FCMLT P2.D, P0/Z, Z29.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
SEL Z10.D, P2, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z31.D, P2, Z31.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z30.D, P2, Z30.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z8.D, P2, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z9, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z9.D, P0/M, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z28.D, P0/M, Z28.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z11, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z11.D, P0/M, Z11.D, Z31.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SXTW Z8.D, P0/M, Z8.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MUL Z31.D, P0/M, Z31.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z10.D, P0/M, Z10.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z8.D, P0/M, Z8.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z11.D, [Z12, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z11.D}, P1/Z, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FDIV Z9.D, P0/M, Z9.D, Z11.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z11.D, [Z21, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z24, Z26.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z11, Z31.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z11, Z8.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z10.D, [Z11, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z26, Z28.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z31.D}, P1/Z, [V31.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z8.D}, P1/Z, [V8.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z10.D}, P1/Z, [V10.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z12.D, Z31.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z11.D, Z10.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z8.D, P0/M, Z8.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABD Z10.D, P0/M, Z10.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z12.D, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMGT P4.D, P0/Z, Z11.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
FSUB Z11.D, Z22.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z11.D, Z10.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FCMGT P2.D, P0/Z, Z12.D, #0.0000000	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z12, Z8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FMLA Z12.D, P0/M, Z9.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FSUBR Z9.D, P0/M, Z9.D, #0.0000000	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
AND P3.B, P1/Z, P1.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	0	0	1	1	vect (12.5%)
LD1D {Z27.D}, P3/Z, [X9, Z27.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z30.D}, P3/Z, [X9, Z30.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FDIV Z11.D, P0/M, Z11.D, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FDIVR Z30.D, P0/M, Z30.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FMUL Z27.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z30.D, Z30.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z27.D, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMINNM Z27.D, P0/M, Z27.D, Z8.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z27.D, P0/M, Z27.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z30, Z27	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FNEG Z30.D, P0/M, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z27.D, P4, Z27.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SEL Z27.D, P2, Z27.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z27.D, P0/M, Z9.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMUL Z27.D, Z27.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z27.D}, P1, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X11, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 42ab40 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.19+0x150>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code