OV - exec - Loop 183

	Loop Id: 183	Module: exec	Source: calc_dt.cpp:50-75 [...]	Coverage: 4.33%

0x42ca60 MOVPRFX	Z0, Z14

0x42ca64 SDIV	Z0.D, P0/M, Z0.D, Z1.D

0x42ca68 SUB	X19, X29, #64

0x42ca6c DUP	Z24.D, X18

0x42ca70 SUBS	X26, X26, X30

0x42ca74 LDR	Z2, [X19, #501, MUL VL]    [11]

0x42ca78 LDR	Z6, [X19, #509, MUL VL]    [11]

0x42ca7c LDR	Z20, [X19, #511, MUL VL]    [11]

0x42ca80 LDR	Z23, [X19, #506, MUL VL]    [11]

0x42ca84 ADD	Z15.D, Z2.D, Z0.D

0x42ca88 LDR	Z2, [X19, #500, MUL VL]    [11]

0x42ca8c MOVPRFX	Z25, Z14

0x42ca90 MLS	Z25.D, P0/M, Z0.D, Z1.D

0x42ca94 ADD	Z0.D, Z0.D, Z20.D

0x42ca98 LDR	Z5, [X19, #510, MUL VL]    [11]

0x42ca9c MOVPRFX	Z20, Z0

0x42caa0 SXTW	Z20.D, P0/M, Z0.D

0x42caa4 MOVPRFX	Z0, Z17

0x42caa8 MUL	Z0.D, P0/M, Z0.D, Z20.D

0x42caac ADD	Z3.D, Z2.D, Z25.D

0x42cab0 LD1D	{Z2.D}, P0/Z, [X9, Z15.D,SXTW #3]    [10]

0x42cab4 SXTW	Z15.D, P0/M, Z15.D

0x42cab8 ADD	Z25.D, Z25.D, Z30.D

0x42cabc MUL	Z6.D, P0/M, Z6.D, Z15.D

0x42cac0 ADR	Z7.D, [Z8, Z3.D,SXTW #3]    [9]

0x42cac4 ADR	Z16.D, [Z9, Z3.D,SXTW #3]    [12]

0x42cac8 ADR	Z18.D, [Z11, Z3.D,SXTW #3]    [7]

0x42cacc LD1D	{Z4.D}, P0/Z, [X8, Z3.D,SXTW #3]    [32]

0x42cad0 ADR	Z28.D, [Z11, Z25.D,SXTW #3]    [7]

0x42cad4 MUL	Z23.D, P0/M, Z23.D, Z15.D

0x42cad8 MUL	Z5.D, P0/M, Z5.D, Z15.D

0x42cadc ADR	Z26.D, [Z24, Z3.D,SXTW #3]    [16]

0x42cae0 ADR	Z27.D, [Z31, Z3.D,SXTW #3]    [8]

0x42cae4 ADR	Z6.D, [Z7, Z6.D,LSL #3]    [6]

0x42cae8 LDR	Z7, [X19, #508, MUL VL]    [11]

0x42caec ADR	Z26.D, [Z26, Z23.D,LSL #3]    [22]

0x42caf0 ADR	Z5.D, [Z27, Z5.D,LSL #3]    [24]

0x42caf4 LD1D	{Z6.D}, P0/Z, [V6.D]    [4]

0x42caf8 FMINNM	Z2.D, P0/M, Z2.D, Z4.D

0x42cafc FADD	Z4.D, Z6.D, Z6.D

0x42cb00 MUL	Z7.D, P0/M, Z7.D, Z15.D

0x42cb04 ADR	Z7.D, [Z16, Z7.D,LSL #3]    [18]

0x42cb08 MOVPRFX	Z16, Z17

0x42cb0c MUL	Z16.D, P0/M, Z16.D, Z15.D

0x42cb10 LD1D	{Z26.D}, P0/Z, [V26.D]    [21]

0x42cb14 LD1D	{Z5.D}, P0/Z, [V5.D]    [3]

0x42cb18 LD1D	{Z7.D}, P0/Z, [V7.D]    [5]

0x42cb1c ADR	Z19.D, [Z18, Z16.D,LSL #3]    [28]

0x42cb20 ADR	Z18.D, [Z18, Z0.D,LSL #3]    [28]

0x42cb24 ADR	Z16.D, [Z28, Z16.D,LSL #3]    [29]

0x42cb28 ADR	Z0.D, [Z28, Z0.D,LSL #3]    [29]

0x42cb2c LD1D	{Z19.D}, P0/Z, [V19.D]    [30]

0x42cb30 LD1D	{Z18.D}, P0/Z, [V18.D]    [27]

0x42cb34 LD1D	{Z16.D}, P0/Z, [V16.D]    [17]

0x42cb38 LD1D	{Z0.D}, P0/Z, [V0.D]    [1]

0x42cb3c FDIV	Z4.D, P0/M, Z4.D, Z7.D

0x42cb40 LDR	Z7, [X19, #505, MUL VL]    [11]

0x42cb44 FADD	Z6.D, Z18.D, Z19.D

0x42cb48 ADR	Z18.D, [Z24, Z25.D,SXTW #3]    [16]

0x42cb4c FADD	Z0.D, Z0.D, Z16.D

0x42cb50 DUP	Z16.D, X1

0x42cb54 MUL	Z7.D, P0/M, Z7.D, Z15.D

0x42cb58 ADR	Z18.D, [Z18, Z23.D,LSL #3]    [26]

0x42cb5c FMUL	Z6.D, Z26.D, Z6.D

0x42cb60 DUP	Z23.D, X3

0x42cb64 ADR	Z16.D, [Z16, Z3.D,SXTW #3]    [34]

0x42cb68 LD1D	{Z18.D}, P0/Z, [V18.D]    [25]

0x42cb6c ADR	Z24.D, [Z23, Z3.D,SXTW #3]    [14]

0x42cb70 ADR	Z23.D, [Z23, Z25.D,SXTW #3]    [14]

0x42cb74 ADR	Z7.D, [Z16, Z7.D,LSL #3]    [33]

0x42cb78 MOVPRFX	Z16, Z6

0x42cb7c FABS	Z16.D, P0/M, Z6.D

0x42cb80 LD1D	{Z7.D}, P0/Z, [V7.D]    [23]

0x42cb84 FMLA	Z4.D, P0/M, Z5.D, Z5.D

0x42cb88 DUP	Z5.D, X5

0x42cb8c FMUL	Z0.D, Z0.D, Z18.D

0x42cb90 MOVPRFX	Z18, Z21

0x42cb94 MUL	Z18.D, P0/M, Z18.D, Z15.D

0x42cb98 ADR	Z3.D, [Z5, Z3.D,SXTW #3]    [2]

0x42cb9c MOVPRFX	Z5, Z21

0x42cba0 MUL	Z5.D, P0/M, Z5.D, Z20.D

0x42cba4 MUL	Z15.D, P0/M, Z15.D, Z22.D

0x42cba8 MUL	Z20.D, P0/M, Z20.D, Z22.D

0x42cbac FSQRT	Z4.D, P0/M, Z4.D

0x42cbb0 MOVPRFX	Z19, Z0

0x42cbb4 FABS	Z19.D, P0/M, Z0.D

0x42cbb8 FMUL	Z25.D, Z7.D, Z10.D

0x42cbbc FMAXNM	Z16.D, P0/M, Z16.D, Z19.D

0x42cbc0 LDR	Z19, [X19, #504, MUL VL]    [11]

0x42cbc4 ADR	Z26.D, [Z24, Z18.D,LSL #3]    [15]

0x42cbc8 ADR	Z18.D, [Z23, Z18.D,LSL #3]    [13]

0x42cbcc FMAXNM	Z16.D, P0/M, Z16.D, Z25.D

0x42cbd0 FMUL	Z19.D, Z7.D, Z19.D

0x42cbd4 FDIVR	Z16.D, P0/M, Z16.D, Z19.D

0x42cbd8 ADR	Z19.D, [Z24, Z5.D,LSL #3]    [15]

0x42cbdc ADR	Z5.D, [Z23, Z5.D,LSL #3]    [13]

0x42cbe0 ADR	Z23.D, [Z3, Z15.D,LSL #3]    [38]

0x42cbe4 ADR	Z3.D, [Z3, Z20.D,LSL #3]    [38]

0x42cbe8 LDR	Z20, [X19, #507, MUL VL]    [11]

0x42cbec FMAXNM	Z4.D, P0/M, Z4.D, Z10.D

0x42cbf0 FMUL	Z2.D, Z20.D, Z2.D

0x42cbf4 FDIV	Z2.D, P0/M, Z2.D, Z4.D

0x42cbf8 LD1D	{Z26.D}, P0/Z, [V26.D]    [20]

0x42cbfc LD1D	{Z18.D}, P0/Z, [V18.D]    [35]

0x42cc00 LD1D	{Z4.D}, P0/Z, [V23.D]    [31]

0x42cc04 LD1D	{Z19.D}, P0/Z, [V19.D]    [36]

0x42cc08 LD1D	{Z5.D}, P0/Z, [V5.D]    [19]

0x42cc0c LD1D	{Z3.D}, P0/Z, [V3.D]    [37]

0x42cc10 FADD	Z18.D, Z18.D, Z26.D

0x42cc14 FADD	Z5.D, Z5.D, Z19.D

0x42cc18 FMUL	Z3.D, Z5.D, Z3.D

0x42cc1c FMUL	Z4.D, Z4.D, Z18.D

0x42cc20 FADD	Z5.D, Z6.D, Z4.D

0x42cc24 FABS	Z4.D, P0/M, Z4.D

0x42cc28 FSUB	Z0.D, Z0.D, Z5.D

0x42cc2c FADD	Z0.D, Z0.D, Z3.D

0x42cc30 FABS	Z3.D, P0/M, Z3.D

0x42cc34 FMAXNM	Z3.D, P0/M, Z3.D, Z4.D

0x42cc38 LDR	Z4, [X19, #503, MUL VL]    [11]

0x42cc3c FMAXNM	Z3.D, P0/M, Z3.D, Z25.D

0x42cc40 FMUL	Z4.D, Z7.D, Z4.D

0x42cc44 FDIVR	Z3.D, P0/M, Z3.D, Z4.D

0x42cc48 FADD	Z4.D, Z7.D, Z7.D

0x42cc4c FDIV	Z0.D, P0/M, Z0.D, Z4.D

0x42cc50 LDR	Z4, [X19, #502, MUL VL]    [11]

0x42cc54 FDIV	Z4.D, P0/M, Z4.D, Z0.D

0x42cc58 FCMGT	P1.D, P0/Z, Z12.D, Z0.D

0x42cc5c ORR	Z0.D, Z13.D, Z13.D

0x42cc60 FMINNM	Z0.D, P1/M, Z0.D, Z4.D

0x42cc64 FMINNM	Z0.D, P0/M, Z0.D, Z3.D

0x42cc68 FMINNM	Z0.D, P0/M, Z0.D, Z16.D

0x42cc6c FMINNM	Z0.D, P0/M, Z0.D, Z2.D

0x42cc70 FMINNM	Z29.D, P0/M, Z29.D, Z0.D

0x42cc74 LDR	Z0, [X19, #499, MUL VL]    [11]

0x42cc78 ADD	Z14.D, Z14.D, Z0.D

0x42cc7c B.NE	42ca60

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 50 - 75

--------------------------------------------------------------------------------

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►98.39+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.61+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	calc_dt_kernel(int, int, int, [...]	calc_dt.cpp:82	exec
○	calc_dt(global_variables&, int[...]	calc_dt.cpp:131	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:80	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02 - 2.42
Bottlenecks	P6, P8,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .omp_outlined]
Source	calc_dt.cpp:50-75,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	49.83 - 118.59
CQA cycles if no scalar integer	49.83 - 118.59
CQA cycles if FP arith vectorized	49.83 - 118.59
CQA cycles if fully vectorized	49.83 - 118.59
Front-end cycles	17.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	4.00
P5 cycles	0.50
P6 cycles	49.00
P7 cycles	49.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	10.50
P11 cycles	10.17
P12 cycles	10.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	49.83 - 118.59
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	136.00
Nb uops	136.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.09 - 0.88
Nb FLOP add-sub	36.00
Nb FLOP mul	32.00
Nb FLOP fma	4.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.39 - 19.98
Bytes prefetched	0.00
Bytes loaded	995.38
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	28.00
Stride indirect	10.00
Vectorization ratio all	69.40
Vectorization ratio load	53.45
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	34.88
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	59.38
Vector-efficiency ratio all	82.09
Vector-efficiency ratio load	65.09
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	51.16
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	90.63

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02 - 2.42
Bottlenecks	P6, P8,
Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .omp_outlined]
Source	calc_dt.cpp:50-75,context.h:69-69
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	49.83 - 118.59
CQA cycles if no scalar integer	49.83 - 118.59
CQA cycles if FP arith vectorized	49.83 - 118.59
CQA cycles if fully vectorized	49.83 - 118.59
Front-end cycles	17.00
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	4.00
P5 cycles	0.50
P6 cycles	49.00
P7 cycles	49.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	10.50
P11 cycles	10.17
P12 cycles	10.33
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	49.83 - 118.59
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	136.00
Nb uops	136.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.09 - 0.88
Nb FLOP add-sub	36.00
Nb FLOP mul	32.00
Nb FLOP fma	4.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.39 - 19.98
Bytes prefetched	0.00
Bytes loaded	995.38
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	28.00
Stride indirect	10.00
Vectorization ratio all	69.40
Vectorization ratio load	53.45
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	34.88
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	59.38
Vector-efficiency ratio all	82.09
Vector-efficiency ratio load	65.09
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	51.16
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	90.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .omp_outlined]
Source file and lines	calc_dt.cpp:50-75
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50-75
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 82% of vector register length is used (average across all VPU instructions).

Details

69% of VPU instructions are used in vector version (process two or more data elements in vector registers):

53% of VPU loads are used in vector version.
34% of VPU addition or subtraction instructions are used in vector version.
59% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 118.59 to 45.00 cycles (2.64x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 28 occurrence(s)
Irregular (variable stride) or indirect: 10 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 104 FP arithmetical operations:

40: addition or subtraction (4 inside FMA instructions)
36: multiply (4 inside FMA instructions)
24: divide
4: square root

The binary loop is loading 995 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	136
nb uops	136
loop length	544
used w registers	0
used x registers	10
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	10
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	4.00	0.50	49.00	49.00	8.00	8.00	10.50	10.17	10.33	0.00	0.00
cycles	0.50	0.50	0.75	0.75	4.00	0.50	49.00	49.00	9.00	9.00	10.50	10.17	10.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	49.83-118.59
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	17.00
Dispatch	49.00
DIV/SQRT	49.83-118.59
Data deps.	2.00
Overall L1	49.83-118.59

Vectorization ratios

INT

all	55%
load	53%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	17%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	69%
load	53%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	34%
fma	100%
div/sqrt	100%
other	59%

Vector efficiency ratios

INT

all	74%
load	65%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
other	82%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	82%
load	65%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	51%
fma	100%
div/sqrt	100%
other	90%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 118.59 cycles. At this rate:

8% of peak load performance is reached (8.39 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ca60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MOVPRFX Z0, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SDIV Z0.D, P0/M, Z0.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X19, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z24.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUBS X26, X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR Z2, [X19, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z6, [X19, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z20, [X19, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z23, [X19, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z15.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z2, [X19, #500, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z25, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z25.D, P0/M, Z0.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z0.D, Z0.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z5, [X19, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z20.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z0, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z0.D, P0/M, Z0.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z3.D, Z2.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z2.D}, P0/Z, [X9, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SXTW Z15.D, P0/M, Z15.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADD Z25.D, Z25.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z7.D, [Z8, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z16.D, [Z9, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z18.D, [Z11, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z4.D}, P0/Z, [X8, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z28.D, [Z11, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MUL Z23.D, P0/M, Z23.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z5.D, P0/M, Z5.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z26.D, [Z24, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z31, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z7, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z7, [X19, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z26.D, [Z26, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z27, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMINNM Z2.D, P0/M, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z4.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z7.D, P0/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z7.D, [Z16, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z16, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z16.D, P0/M, Z16.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z26.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z19.D, [Z18, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z18.D, [Z18, Z0.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z16.D, [Z28, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z28, Z0.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z18.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FDIV Z4.D, P0/M, Z4.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LDR Z7, [X19, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z6.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z18.D, [Z24, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z0.D, Z0.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z16.D, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MUL Z7.D, P0/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z18.D, [Z18, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z6.D, Z26.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
DUP Z23.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADR Z16.D, [Z16, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z18.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z24.D, [Z23, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z23.D, [Z23, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z16, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z16, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z16.D, P0/M, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z4.D, P0/M, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
DUP Z5.D, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
FMUL Z0.D, Z0.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z18, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z18.D, P0/M, Z18.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z3.D, [Z5, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z5, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P0/M, Z5.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z15.D, P0/M, Z15.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z20.D, P0/M, Z20.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FSQRT Z4.D, P0/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
MOVPRFX Z19, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z19.D, P0/M, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z25.D, Z7.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAXNM Z16.D, P0/M, Z16.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z19, [X19, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z26.D, [Z24, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z18.D, [Z23, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMAXNM Z16.D, P0/M, Z16.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z19.D, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z16.D, P0/M, Z16.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z19.D, [Z24, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z23, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z23.D, [Z3, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z3, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z20, [X19, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAXNM Z4.D, P0/M, Z4.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z2.D, Z20.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z2.D, P0/M, Z2.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LD1D {Z26.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z18.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z18.D, Z18.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z5.D, Z5.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z4.D, Z4.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z5.D, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABS Z4.D, P0/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z0.D, Z0.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABS Z3.D, P0/M, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z3.D, P0/M, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [X19, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAXNM Z3.D, P0/M, Z3.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z4.D, Z7.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z3.D, P0/M, Z3.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z4.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z0.D, P0/M, Z0.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LDR Z4, [X19, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FDIV Z4.D, P0/M, Z4.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCMGT P1.D, P0/Z, Z12.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
ORR Z0.D, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P1/M, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z29.D, P0/M, Z29.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X19, #499, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z14.D, Z14.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
B.NE 42ca60 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, double&, int&, double&, double&, int&, int&, int&) [clone .omp_outlined]
Source file and lines	calc_dt.cpp:50-75
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:50-75
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 82% of vector register length is used (average across all VPU instructions).

Details

69% of VPU instructions are used in vector version (process two or more data elements in vector registers):

53% of VPU loads are used in vector version.
34% of VPU addition or subtraction instructions are used in vector version.
59% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 118.59 to 45.00 cycles (2.64x speedup).

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 28 occurrence(s)
Irregular (variable stride) or indirect: 10 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 104 FP arithmetical operations:

40: addition or subtraction (4 inside FMA instructions)
36: multiply (4 inside FMA instructions)
24: divide
4: square root

The binary loop is loading 995 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	136
nb uops	136
loop length	544
used w registers	0
used x registers	10
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	10
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.00 cycles
front end	17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	4.00	0.50	49.00	49.00	8.00	8.00	10.50	10.17	10.33	0.00	0.00
cycles	0.50	0.50	0.75	0.75	4.00	0.50	49.00	49.00	9.00	9.00	10.50	10.17	10.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	49.83-118.59
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	17.00
Dispatch	49.00
DIV/SQRT	49.83-118.59
Data deps.	2.00
Overall L1	49.83-118.59

Vectorization ratios

INT

all	55%
load	53%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	17%
fma	NA (no fma vectorizable/vectorized instructions)
other	23%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	69%
load	53%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	34%
fma	100%
div/sqrt	100%
other	59%

Vector efficiency ratios

INT

all	74%
load	65%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
other	82%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	82%
load	65%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	51%
fma	100%
div/sqrt	100%
other	90%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 118.59 cycles. At this rate:

8% of peak load performance is reached (8.39 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42ca60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MOVPRFX Z0, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SDIV Z0.D, P0/M, Z0.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
SUB X19, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
DUP Z24.D, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
SUBS X26, X26, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
LDR Z2, [X19, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z6, [X19, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z20, [X19, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z23, [X19, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z15.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z2, [X19, #500, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z25, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z25.D, P0/M, Z0.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z0.D, Z0.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z5, [X19, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z20, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z20.D, P0/M, Z0.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z0, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z0.D, P0/M, Z0.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z3.D, Z2.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z2.D}, P0/Z, [X9, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SXTW Z15.D, P0/M, Z15.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
ADD Z25.D, Z25.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z7.D, [Z8, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z16.D, [Z9, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z18.D, [Z11, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z4.D}, P0/Z, [X8, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z28.D, [Z11, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MUL Z23.D, P0/M, Z23.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z5.D, P0/M, Z5.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z26.D, [Z24, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z31, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z7, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z7, [X19, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z26.D, [Z26, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z27, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMINNM Z2.D, P0/M, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z4.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MUL Z7.D, P0/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z7.D, [Z16, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z16, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z16.D, P0/M, Z16.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z26.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z19.D, [Z18, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z18.D, [Z18, Z0.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z16.D, [Z28, Z16.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z28, Z0.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z18.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FDIV Z4.D, P0/M, Z4.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LDR Z7, [X19, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FADD Z6.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z18.D, [Z24, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z0.D, Z0.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z16.D, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
MUL Z7.D, P0/M, Z7.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z18.D, [Z18, Z23.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z6.D, Z26.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
DUP Z23.D, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADR Z16.D, [Z16, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z18.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z24.D, [Z23, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z23.D, [Z23, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z16, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z16, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z16.D, P0/M, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z4.D, P0/M, Z5.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
DUP Z5.D, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
FMUL Z0.D, Z0.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z18, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z18.D, P0/M, Z18.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z3.D, [Z5, Z3.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z5, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P0/M, Z5.D, Z20.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z15.D, P0/M, Z15.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z20.D, P0/M, Z20.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FSQRT Z4.D, P0/M, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
MOVPRFX Z19, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
FABS Z19.D, P0/M, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z25.D, Z7.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMAXNM Z16.D, P0/M, Z16.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z19, [X19, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z26.D, [Z24, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z18.D, [Z23, Z18.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMAXNM Z16.D, P0/M, Z16.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z19.D, Z7.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z16.D, P0/M, Z16.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z19.D, [Z24, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z23, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z23.D, [Z3, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z3, Z20.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z20, [X19, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAXNM Z4.D, P0/M, Z4.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z2.D, Z20.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z2.D, P0/M, Z2.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LD1D {Z26.D}, P0/Z, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z18.D}, P0/Z, [V18.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V23.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z19.D}, P0/Z, [V19.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z18.D, Z18.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z5.D, Z5.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z4.D, Z4.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z5.D, Z6.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABS Z4.D, P0/M, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FSUB Z0.D, Z0.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z0.D, Z0.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FABS Z3.D, P0/M, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAXNM Z3.D, P0/M, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [X19, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FMAXNM Z3.D, P0/M, Z3.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z4.D, Z7.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z3.D, P0/M, Z3.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FADD Z4.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z0.D, P0/M, Z0.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LDR Z4, [X19, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FDIV Z4.D, P0/M, Z4.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FCMGT P1.D, P0/Z, Z12.D, Z0.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1	vect (100.0%)
ORR Z0.D, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P1/M, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMINNM Z29.D, P0/M, Z29.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X19, #499, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z14.D, Z14.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
B.NE 42ca60 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_.omp_outlined+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code