OV - exec - Loop 199

	Loop Id: 199	Module: exec	Source: field_summary.cpp:76-91 [...]	Coverage: 0.33%

0x42e1e8 MOVPRFX	Z9, Z18

0x42e1ec SXTW	Z9.D, P0/M, Z18.D

0x42e1f0 DUP	Z4.D, #8

0x42e1f4 SUBS	W22, W22, W21

0x42e1f8 SDIV	Z9.D, P0/M, Z9.D, Z21.D

0x42e1fc MOVPRFX	Z11, Z18

0x42e200 MLS	Z11.D, P0/M, Z9.D, Z1.D

0x42e204 ADD	Z9.D, Z2.D, Z9.D

0x42e208 ADD	Z18.D, Z18.D, Z20.D

0x42e20c MOVPRFX	Z10, Z9

0x42e210 SXTW	Z10.D, P0/M, Z9.D

0x42e214 MOVPRFX	Z12, Z3

0x42e218 MUL	Z12.D, P0/M, Z12.D, Z10.D

0x42e21c ADD	Z9.D, Z0.D, Z11.D

0x42e220 MOVPRFX	Z11, Z23

0x42e224 MUL	Z11.D, P0/M, Z11.D, Z10.D

0x42e228 ADR	Z15.D, [Z4, Z9.D,SXTW #3]    [3]

0x42e22c ADR	Z12.D, [Z24, Z12.D,LSL #3]    [20]

0x42e230 ADR	Z11.D, [Z22, Z11.D,LSL #3]    [11]

0x42e234 ADR	Z13.D, [Z12, Z9.D,SXTW #3]    [9]

0x42e238 ADD	Z12.D, Z12.D, Z15.D

0x42e23c ADR	Z14.D, [Z11, Z9.D,SXTW #3]    [5]

0x42e240 ADD	Z11.D, Z11.D, Z15.D

0x42e244 LD1D	{Z13.D}, P0/Z, [V13.D]    [15]

0x42e248 FMUL	Z13.D, Z13.D, Z13.D

0x42e24c LD1D	{Z14.D}, P0/Z, [V14.D]    [19]

0x42e250 LD1D	{Z12.D}, P0/Z, [V12.D]    [8]

0x42e254 LD1D	{Z11.D}, P0/Z, [V11.D]    [4]

0x42e258 FMLA	Z13.D, P0/M, Z14.D, Z14.D

0x42e25c MOVPRFX	Z14, Z5

0x42e260 MUL	Z14.D, P0/M, Z14.D, Z10.D

0x42e264 FMAD	Z12.D, P0/M, Z12.D, Z13.D

0x42e268 ORR	Z13.D, Z10.D, Z10.D

0x42e26c ADD	Z13.D, Z13.D, #1

0x42e270 MOVPRFX	Z4, Z23

0x42e274 MUL	Z4.D, P0/M, Z4.D, Z13.D

0x42e278 MUL	Z13.D, P0/M, Z13.D, Z3.D

0x42e27c FMAD	Z11.D, P0/M, Z11.D, Z12.D

0x42e280 ADR	Z12.D, [Z24, Z13.D,LSL #3]    [20]

0x42e284 ADR	Z4.D, [Z22, Z4.D,LSL #3]    [11]

0x42e288 ADR	Z13.D, [Z12, Z9.D,SXTW #3]    [7]

0x42e28c ADD	Z12.D, Z12.D, Z15.D

0x42e290 LD1D	{Z13.D}, P0/Z, [V13.D]    [13]

0x42e294 FMLA	Z11.D, P0/M, Z13.D, Z13.D

0x42e298 ADR	Z13.D, [Z4, Z9.D,SXTW #3]    [2]

0x42e29c ADD	Z4.D, Z4.D, Z15.D

0x42e2a0 LD1D	{Z12.D}, P0/Z, [V12.D]    [6]

0x42e2a4 MOVPRFX	Z15, Z16

0x42e2a8 MUL	Z15.D, P0/M, Z15.D, Z10.D

0x42e2ac LD1D	{Z13.D}, P0/Z, [V13.D]    [27]

0x42e2b0 LD1D	{Z4.D}, P0/Z, [V4.D]    [1]

0x42e2b4 FMLA	Z11.D, P0/M, Z13.D, Z13.D

0x42e2b8 MOVPRFX	Z13, Z6

0x42e2bc MUL	Z13.D, P0/M, Z13.D, Z10.D

0x42e2c0 MUL	Z10.D, P0/M, Z10.D, Z7.D

0x42e2c4 FMLA	Z11.D, P0/M, Z12.D, Z12.D

0x42e2c8 ADR	Z12.D, [Z25, Z9.D,SXTW #3]    [21]

0x42e2cc ADR	Z12.D, [Z12, Z14.D,LSL #3]    [25]

0x42e2d0 ADR	Z14.D, [Z26, Z9.D,SXTW #3]    [22]

0x42e2d4 ADR	Z13.D, [Z14, Z13.D,LSL #3]    [18]

0x42e2d8 ADR	Z14.D, [Z8, Z9.D,SXTW #3]    [10]

0x42e2dc ADR	Z9.D, [Z27, Z9.D,SXTW #3]    [23]

0x42e2e0 LD1D	{Z12.D}, P0/Z, [V12.D]    [24]

0x42e2e4 FMAD	Z4.D, P0/M, Z4.D, Z11.D

0x42e2e8 ADR	Z9.D, [Z9, Z10.D,LSL #3]    [14]

0x42e2ec LD1D	{Z10.D}, P0/Z, [V13.D]    [26]

0x42e2f0 ADR	Z14.D, [Z14, Z15.D,LSL #3]    [17]

0x42e2f4 FMUL	Z4.D, Z4.D, Z29.D

0x42e2f8 FADD	Z17.D, Z17.D, Z12.D

0x42e2fc LD1D	{Z14.D}, P0/Z, [V14.D]    [16]

0x42e300 LD1D	{Z9.D}, P0/Z, [V9.D]    [12]

0x42e304 FMUL	Z10.D, Z10.D, Z12.D

0x42e308 FMLA	Z19.D, P0/M, Z14.D, Z12.D

0x42e30c FMLA	Z30.D, P0/M, Z9.D, Z10.D

0x42e310 FMLA	Z28.D, P0/M, Z4.D, Z10.D

0x42e314 FADD	Z31.D, Z31.D, Z10.D

0x42e318 B.NE	42e1e8

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp: 76 - 91

--------------------------------------------------------------------------------

76:     for (int idx = (0); idx < ((ymax - ymin + 1) * (xmax - xmin + 1)); idx++) {

77:       const int j = xmin + 1 + idx % (xmax - xmin + 1);

78:       const int k = ymin + 1 + idx / (xmax - xmin + 1);

79:       double vsqrd = 0.0;

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

83:         }

84:       }

85:       double cell_vol = field.volume(j, k);

86:       double cell_mass = cell_vol * field.density0(j, k);

87:       vol += cell_vol;

88:       mass += cell_mass;

89:       ie += cell_mass * field.energy0(j, k);

90:       ke += cell_mass * 0.5 * vsqrd;

91:       press += cell_vol * field.pressure(j, k);

Coverage (%)	Name	Source Location	Module
►98.42+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.27+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	field_summary(global_variables[...]	field_summary.cpp:66	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:105	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.28
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source	context.h:69-69,field_summary.cpp:76-91
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	31.50
CQA cycles if no scalar integer	31.50
CQA cycles if FP arith vectorized	31.50
CQA cycles if fully vectorized	24.66
Front-end cycles	9.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	0.25
P6 cycles	31.50
P7 cycles	31.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	77.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.17
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	40.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.26
Bytes prefetched	0.00
Bytes loaded	386.13
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	18.00
Stride indirect	9.00
Vectorization ratio all	63.16
Vectorization ratio load	41.38
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	37.93
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	23.08
Vector-efficiency ratio all	80.80
Vector-efficiency ratio load	56.03
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	53.02
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	92.55

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.28
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source	context.h:69-69,field_summary.cpp:76-91
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	NA
Unroll factor	2
CQA cycles	31.50
CQA cycles if no scalar integer	31.50
CQA cycles if FP arith vectorized	31.50
CQA cycles if fully vectorized	24.66
Front-end cycles	9.63
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	0.25
P4 cycles	0.25
P5 cycles	0.25
P6 cycles	31.50
P7 cycles	31.50
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	0.87 - 20.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	77.00
Nb uops	77.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.17
Nb FLOP add-sub	8.00
Nb FLOP mul	12.00
Nb FLOP fma	40.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.26
Bytes prefetched	0.00
Bytes loaded	386.13
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	18.00
Stride indirect	9.00
Vectorization ratio all	63.16
Vectorization ratio load	41.38
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	37.93
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	23.08
Vector-efficiency ratio all	80.80
Vector-efficiency ratio load	56.03
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	53.02
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	92.55

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source file and lines	field_summary.cpp:76-91
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76-91

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 80% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 31.50 to 24.66 cycles (1.28x speedup).

Details

63% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
37% of VPU addition or subtraction instructions are used in vector version.
23% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 40 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 18 occurrence(s)
Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 100 FP arithmetical operations:

48: addition or subtraction (40 inside FMA instructions)
52: multiply (40 inside FMA instructions)

The binary loop is loading 386 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	77
nb uops	77
loop length	308
used w registers	2
used x registers	0
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	6
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	31.50	31.50	6.00	6.00	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	31.50	31.50	7.50	7.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.63
Dispatch	31.50
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	31.50

Vectorization ratios

INT

all	54%
load	41%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	63%
load	41%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	37%
fma	100%
div/sqrt	100%
other	23%

Vector efficiency ratios

INT

all	76%
load	56%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	49%
fma	NA (no fma vectorizable/vectorized instructions)
other	93%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	80%
load	56%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	53%
fma	100%
div/sqrt	100%
other	92%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.50 cycles. At this rate:

12% of peak load performance is reached (12.26 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42e1e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MOVPRFX Z9, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z9.D, P0/M, Z18.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
DUP Z4.D, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUBS W22, W22, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SDIV Z9.D, P0/M, Z9.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z11, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z11.D, P0/M, Z9.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z9.D, Z2.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z18.D, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z10, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z10.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z12, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z9.D, Z0.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z11, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z11.D, P0/M, Z11.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z15.D, [Z4, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z12.D, [Z24, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z11.D, [Z22, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z12, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z12.D, Z12.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z14.D, [Z11, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z11.D, Z11.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z13.D, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z11.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z13.D, P0/M, Z14.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z14, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z14.D, P0/M, Z14.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMAD Z12.D, P0/M, Z12.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ORR Z13.D, Z10.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z13.D, Z13.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z4, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P0/M, Z4.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z13.D, P0/M, Z13.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMAD Z11.D, P0/M, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z12.D, [Z24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z22, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z12, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z12.D, Z12.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z11.D, P0/M, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z13.D, [Z4, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z4.D, Z4.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MOVPRFX Z15, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P0/M, Z15.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z11.D, P0/M, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z13, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P0/M, Z13.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z10.D, P0/M, Z10.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMLA Z11.D, P0/M, Z12.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z12.D, [Z25, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z12.D, [Z12, Z14.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z26, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z14, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z8, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z9.D, [Z27, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z4.D, P0/M, Z4.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z9.D, [Z9, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z10.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z14.D, [Z14, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z4.D, Z4.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z9.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z10.D, Z10.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z19.D, P0/M, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z30.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z28.D, P0/M, Z4.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FADD Z31.D, Z31.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
B.NE 42e1e8 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source file and lines	field_summary.cpp:76-91
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76-91

The related source loop is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

63% of VPU instructions are used in vector version (process two or more data elements in vector registers):

41% of VPU loads are used in vector version.
37% of VPU addition or subtraction instructions are used in vector version.
23% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 40 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 18 occurrence(s)
Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 100 FP arithmetical operations:

48: addition or subtraction (40 inside FMA instructions)
52: multiply (40 inside FMA instructions)

The binary loop is loading 386 bytes.

Arithmetic intensity

Arithmetic intensity is 0.26 FP operations per loaded or stored byte.

General properties

nb instructions	77
nb uops	77
loop length	308
used w registers	2
used x registers	0
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	6
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.25	0.25	0.25	0.25	31.50	31.50	6.00	6.00	4.00	4.00	4.00	0.00	0.00
cycles	0.50	0.50	0.25	0.25	0.25	0.25	31.50	31.50	7.50	7.50	4.00	4.00	4.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.87-20.00
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	9.63
Dispatch	31.50
DIV/SQRT	0.87-20.00
Data deps.	2.00
Overall L1	31.50

Vectorization ratios

INT

all	54%
load	41%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	63%
load	41%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	37%
fma	100%
div/sqrt	100%
other	23%

Vector efficiency ratios

INT

all	76%
load	56%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	49%
fma	NA (no fma vectorizable/vectorized instructions)
other	93%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	80%
load	56%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	53%
fma	100%
div/sqrt	100%
other	92%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 31.50 cycles. At this rate:

12% of peak load performance is reached (12.26 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42e1e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
MOVPRFX Z9, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z9.D, P0/M, Z18.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
DUP Z4.D, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUBS W22, W22, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
SDIV Z9.D, P0/M, Z9.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
MOVPRFX Z11, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z11.D, P0/M, Z9.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z9.D, Z2.D, Z9.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z18.D, Z18.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z10, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z10.D, P0/M, Z9.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z12, Z3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z12.D, P0/M, Z12.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z9.D, Z0.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z11, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z11.D, P0/M, Z11.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z15.D, [Z4, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z12.D, [Z24, Z12.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z11.D, [Z22, Z11.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z12, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z12.D, Z12.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z14.D, [Z11, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z11.D, Z11.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z13.D, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z11.D}, P0/Z, [V11.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z13.D, P0/M, Z14.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z14, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z14.D, P0/M, Z14.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMAD Z12.D, P0/M, Z12.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ORR Z13.D, Z10.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z13.D, Z13.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z4, Z23	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P0/M, Z4.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z13.D, P0/M, Z13.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMAD Z11.D, P0/M, Z11.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z12.D, [Z24, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z22, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z12, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z12.D, Z12.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z11.D, P0/M, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z13.D, [Z4, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADD Z4.D, Z4.D, Z15.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MOVPRFX Z15, Z16	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z15.D, P0/M, Z15.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z13.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMLA Z11.D, P0/M, Z13.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
MOVPRFX Z13, Z6	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z13.D, P0/M, Z13.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z10.D, P0/M, Z10.D, Z7.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMLA Z11.D, P0/M, Z12.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z12.D, [Z25, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z12.D, [Z12, Z14.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z26, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z13.D, [Z14, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z14.D, [Z8, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z9.D, [Z27, Z9.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z12.D}, P0/Z, [V12.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z4.D, P0/M, Z4.D, Z11.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z9.D, [Z9, Z10.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z10.D}, P0/Z, [V13.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z14.D, [Z14, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z4.D, Z4.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z17.D, Z17.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z14.D}, P0/Z, [V14.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z9.D}, P0/Z, [V9.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z10.D, Z10.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMLA Z19.D, P0/M, Z14.D, Z12.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z30.D, P0/M, Z9.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMLA Z28.D, P0/M, Z4.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FADD Z31.D, Z31.D, Z10.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
B.NE 42e1e8 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x1c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code