OV - exec - Loop 209

	Loop Id: 209	Module: exec	Source: ideal_gas.cpp:38-45 [...]	Coverage: 4.14%

0x42f884 SEL	Z25.D, P1, Z4.D, Z16.D

0x42f888 ADD	X10, X10, X8

0x42f88c SDIVR	Z25.D, P0/M, Z25.D, Z24.D

0x42f890 ADD	Z26.D, Z5.D, Z25.D

0x42f894 MSB	Z25.D, P0/M, Z4.D, Z24.D

0x42f898 ADD	Z24.D, Z24.D, Z7.D

0x42f89c SXTW	Z26.D, P0/M, Z26.D

0x42f8a0 MOVPRFX	Z27, Z0

0x42f8a4 MUL	Z27.D, P0/M, Z27.D, Z26.D

0x42f8a8 MOVPRFX	Z30, Z1

0x42f8ac MUL	Z30.D, P0/M, Z30.D, Z26.D

0x42f8b0 ADD	Z25.D, Z6.D, Z25.D

0x42f8b4 ADR	Z28.D, [Z17, Z25.D,SXTW #3]    [10]

0x42f8b8 ADR	Z31.D, [Z20, Z25.D,SXTW #3]    [1]

0x42f8bc ADR	Z27.D, [Z28, Z27.D,LSL #3]    [12]

0x42f8c0 ADR	Z30.D, [Z31, Z30.D,LSL #3]    [6]

0x42f8c4 ADR	Z31.D, [Z21, Z25.D,SXTW #3]    [4]

0x42f8c8 ADR	Z25.D, [Z23, Z25.D,SXTW #3]    [7]

0x42f8cc LD1D	{Z28.D}, P1/Z, [V27.D]    [11]

0x42f8d0 FMUL	Z29.D, Z28.D, Z19.D

0x42f8d4 FDIVR	Z28.D, P0/M, Z28.D, Z18.D

0x42f8d8 FABS	Z28.D, P0/M, Z28.D

0x42f8dc LD1D	{Z30.D}, P1/Z, [V30.D]    [3]

0x42f8e0 FMUL	Z29.D, Z29.D, Z30.D

0x42f8e4 MOVPRFX	Z30, Z2

0x42f8e8 MUL	Z30.D, P0/M, Z30.D, Z26.D

0x42f8ec ADR	Z30.D, [Z31, Z30.D,LSL #3]    [5]

0x42f8f0 ST1D	{Z29.D}, P1, [V30.D]    [2]

0x42f8f4 LD1D	{Z27.D}, P1/Z, [V27.D]    [11]

0x42f8f8 MUL	Z26.D, P0/M, Z26.D, Z3.D

0x42f8fc ADR	Z25.D, [Z25, Z26.D,LSL #3]    [9]

0x42f900 FMUL	Z27.D, Z22.D, Z27.D

0x42f904 FMUL	Z27.D, Z29.D, Z27.D

0x42f908 FSQRT	Z27.D, P0/M, Z27.D

0x42f90c FMUL	Z27.D, Z27.D, Z28.D

0x42f910 ST1D	{Z27.D}, P1, [V25.D]    [8]

0x42f914 WHILELO	P1.D, X10, X9

0x42f918 B.MI	42f884

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp: 38 - 45

--------------------------------------------------------------------------------

38:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

39:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Module
►98.44+	__kmp_invoke_microtask	libomp.so
○	__kmp_invoke_task_func	libomp.so
○	__kmp_launch_thread	libomp.so
○	__kmp_launch_worker(void*)	libomp.so
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.21
Bottlenecks	P6, P8,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	ideal_gas.cpp:38-45,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00 - 48.17
CQA cycles if no scalar integer	15.00 - 48.17
CQA cycles if FP arith vectorized	15.00 - 48.17
CQA cycles if fully vectorized	14.86 - 48.17
Front-end cycles	4.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	15.00
P7 cycles	15.00
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	1.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	14.86 - 48.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.87 - 0.58
Nb FLOP add-sub	0.00
Nb FLOP mul	20.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.34 - 10.73
Bytes prefetched	0.00
Bytes loaded	97.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	4.00
Vectorization ratio all	68.57
Vectorization ratio load	27.27
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	27.27
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	82.86
Vector-efficiency ratio load	45.45
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	45.45
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.21
Bottlenecks	P6, P8,
Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	ideal_gas.cpp:38-45,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00 - 48.17
CQA cycles if no scalar integer	15.00 - 48.17
CQA cycles if FP arith vectorized	15.00 - 48.17
CQA cycles if fully vectorized	14.86 - 48.17
Front-end cycles	4.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.25
P4 cycles	1.00
P5 cycles	0.25
P6 cycles	15.00
P7 cycles	15.00
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	1.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	14.86 - 48.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	38.00
Nb uops	38.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.87 - 0.58
Nb FLOP add-sub	0.00
Nb FLOP mul	20.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	4.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.34 - 10.73
Bytes prefetched	0.00
Bytes loaded	97.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	8.00
Stride indirect	4.00
Vectorization ratio all	68.57
Vectorization ratio load	27.27
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	27.27
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	82.86
Vector-efficiency ratio load	45.45
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	45.45
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	ideal_gas.cpp:38-45
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-45
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 82% of vector register length is used (average across all VPU instructions).

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

27% of VPU loads are used in vector version.
27% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.17 to 13.50 cycles (3.57x speedup).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)
Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

20: multiply
4: divide
4: square root

The binary loop is loading 97 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	38
nb uops	38
loop length	152
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	3
used z registers	24
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	15.00	15.00	2.50	2.50	1.67	1.67	1.67	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	15.00	15.00	2.50	2.50	1.67	1.67	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-48.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.75
Dispatch	15.00
DIV/SQRT	14.86-48.17
Data deps.	2.00
Overall L1	15.00-48.17

Vectorization ratios

INT

all	59%
load	27%
store	100%
mul	100%
add-sub	27%
fma	100%
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	68%
load	27%
store	100%
mul	100%
add-sub	27%
fma	100%
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	77%
load	45%
store	100%
mul	100%
add-sub	45%
fma	100%
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	82%
load	45%
store	100%
mul	100%
add-sub	45%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.17 cycles. At this rate:

2% of peak load performance is reached (2.01 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42f884

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z25.D, P1, Z4.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z25.D, P0/M, Z25.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z26.D, Z5.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MSB Z25.D, P0/M, Z4.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z24.D, Z24.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z27, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z30, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z30.D, P0/M, Z30.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z25.D, Z6.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z28.D, [Z17, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z20, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z28, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z31, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z21, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z25.D, [Z23, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z28.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z29.D, Z28.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z28.D, P0/M, Z28.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FABS Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z30.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z29.D, Z29.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z30, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z30.D, P0/M, Z30.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z30.D, [Z31, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z29.D}, P1, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z26.D, P0/M, Z26.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z25.D, [Z25, Z26.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z27.D, Z22.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z27.D, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FSQRT Z27.D, P0/M, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z27.D, Z27.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z27.D}, P1, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 42f884 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.omp_outlined+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	ideal_gas.cpp:38-45
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:38-45
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 82% of vector register length is used (average across all VPU instructions).

Details

68% of VPU instructions are used in vector version (process two or more data elements in vector registers):

27% of VPU loads are used in vector version.
27% of VPU addition or subtraction instructions are used in vector version.
50% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.17 to 13.50 cycles (3.57x speedup).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 8 occurrence(s)
Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 28 FP arithmetical operations:

20: multiply
4: divide
4: square root

The binary loop is loading 97 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	38
nb uops	38
loop length	152
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	0
used v registers	3
used z registers	24
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.75 cycles
front end	4.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	15.00	15.00	2.50	2.50	1.67	1.67	1.67	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	15.00	15.00	2.50	2.50	1.67	1.67	1.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-48.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	4.75
Dispatch	15.00
DIV/SQRT	14.86-48.17
Data deps.	2.00
Overall L1	15.00-48.17

Vectorization ratios

INT

all	59%
load	27%
store	100%
mul	100%
add-sub	27%
fma	100%
other	50%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	68%
load	27%
store	100%
mul	100%
add-sub	27%
fma	100%
div/sqrt	100%
other	50%

Vector efficiency ratios

INT

all	77%
load	45%
store	100%
mul	100%
add-sub	45%
fma	100%
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	82%
load	45%
store	100%
mul	100%
add-sub	45%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.17 cycles. At this rate:

2% of peak load performance is reached (2.01 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42f884

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
SEL Z25.D, P1, Z4.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
SDIVR Z25.D, P0/M, Z25.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z26.D, Z5.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MSB Z25.D, P0/M, Z4.D, Z24.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z24.D, Z24.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z26.D, P0/M, Z26.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z27, Z0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z30, Z1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z30.D, P0/M, Z30.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z25.D, Z6.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z28.D, [Z17, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z20, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z28, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z31, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z21, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z25.D, [Z23, Z25.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z28.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z29.D, Z28.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z28.D, P0/M, Z28.D, Z18.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
FABS Z28.D, P0/M, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z30.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z29.D, Z29.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z30, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z30.D, P0/M, Z30.D, Z26.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z30.D, [Z31, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z29.D}, P1, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z26.D, P0/M, Z26.D, Z3.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z25.D, [Z25, Z26.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z27.D, Z22.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FMUL Z27.D, Z29.D, Z27.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FSQRT Z27.D, P0/M, Z27.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-16	6.99-14.08	vect (100.0%)
FMUL Z27.D, Z27.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ST1D {Z27.D}, P1, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X10, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 42f884 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_.omp_outlined+0x144>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code