OV - exec - Loop 253

	Loop Id: 253	Module: exec	Source: PdV.cpp:49-63 [...]	Coverage: 6.07%

0x433ba8 DUP	Z0.D, #1

0x433bac SUB	X12, X29, #64

0x433bb0 ADD	X11, X11, X8

0x433bb4 LDR	Z2, [X12, #510, MUL VL]    [39]

0x433bb8 LDR	Z6, [X12, #502, MUL VL]    [39]

0x433bbc SEL	Z22.D, P0, Z1.D, Z0.D

0x433bc0 LDR	Z0, [X12, #511, MUL VL]    [39]

0x433bc4 SDIVR	Z22.D, P1/M, Z22.D, Z14.D

0x433bc8 ADD	Z30.D, Z0.D, Z22.D

0x433bcc MOVPRFX	Z0, Z14

0x433bd0 MLS	Z0.D, P1/M, Z22.D, Z1.D

0x433bd4 SXTW	Z30.D, P1/M, Z30.D

0x433bd8 MOVPRFX	Z4, Z17

0x433bdc MUL	Z4.D, P1/M, Z4.D, Z30.D

0x433be0 MOVPRFX	Z7, Z18

0x433be4 MUL	Z7.D, P1/M, Z7.D, Z30.D

0x433be8 ADD	Z15.D, Z2.D, Z0.D

0x433bec LDR	Z2, [X12, #509, MUL VL]    [39]

0x433bf0 ADD	Z0.D, Z0.D, Z6.D

0x433bf4 MOVPRFX	Z6, Z21

0x433bf8 MUL	Z6.D, P1/M, Z6.D, Z30.D

0x433bfc ADR	Z5.D, [Z27, Z15.D,SXTW #3]    [38]

0x433c00 ADR	Z19.D, [Z29, Z15.D,SXTW #3]    [42]

0x433c04 ADR	Z23.D, [Z29, Z0.D,SXTW #3]    [42]

0x433c08 ADR	Z16.D, [Z5, Z4.D,LSL #3]    [10]

0x433c0c ADR	Z20.D, [Z19, Z7.D,LSL #3]    [41]

0x433c10 ADR	Z7.D, [Z23, Z7.D,LSL #3]    [25]

0x433c14 MOVPRFX	Z3, Z2

0x433c18 MUL	Z3.D, P1/M, Z3.D, Z30.D

0x433c1c LDR	Z2, [X12, #506, MUL VL]    [39]

0x433c20 LD1D	{Z16.D}, P0/Z, [V16.D]    [31]

0x433c24 ADD	Z22.D, Z22.D, Z2.D

0x433c28 SXTW	Z22.D, P1/M, Z22.D

0x433c2c MOVPRFX	Z2, Z17

0x433c30 MUL	Z2.D, P1/M, Z2.D, Z22.D

0x433c34 LD1D	{Z20.D}, P0/Z, [V20.D]    [15]

0x433c38 LD1D	{Z7.D}, P0/Z, [V7.D]    [18]

0x433c3c FADD	Z7.D, Z7.D, Z20.D

0x433c40 ADR	Z5.D, [Z5, Z2.D,LSL #3]    [10]

0x433c44 LD1D	{Z5.D}, P0/Z, [V5.D]    [9]

0x433c48 FADD	Z5.D, Z5.D, Z16.D

0x433c4c ADR	Z16.D, [Z28, Z15.D,SXTW #3]    [40]

0x433c50 ADR	Z6.D, [Z16, Z6.D,LSL #3]    [29]

0x433c54 LD1D	{Z6.D}, P0/Z, [V6.D]    [13]

0x433c58 FMUL	Z6.D, Z6.D, Z7.D

0x433c5c ADR	Z7.D, [Z26, Z15.D,SXTW #3]    [34]

0x433c60 ADR	Z7.D, [Z7, Z3.D,LSL #3]    [17]

0x433c64 LD1D	{Z7.D}, P0/Z, [V7.D]    [16]

0x433c68 FMAD	Z5.D, P1/M, Z7.D, Z6.D

0x433c6c ADR	Z6.D, [Z26, Z0.D,SXTW #3]    [34]

0x433c70 ADR	Z0.D, [Z27, Z0.D,SXTW #3]    [38]

0x433c74 ADR	Z4.D, [Z0, Z4.D,LSL #3]    [2]

0x433c78 ADR	Z0.D, [Z0, Z2.D,LSL #3]    [2]

0x433c7c MOVPRFX	Z2, Z18

0x433c80 MUL	Z2.D, P1/M, Z2.D, Z22.D

0x433c84 MUL	Z22.D, P1/M, Z22.D, Z21.D

0x433c88 ADR	Z3.D, [Z6, Z3.D,LSL #3]    [12]

0x433c8c ADR	Z6.D, [Z16, Z22.D,LSL #3]    [29]

0x433c90 LD1D	{Z4.D}, P0/Z, [V4.D]    [5]

0x433c94 LD1D	{Z0.D}, P0/Z, [V0.D]    [1]

0x433c98 LD1D	{Z3.D}, P0/Z, [V3.D]    [46]

0x433c9c LD1D	{Z6.D}, P0/Z, [V6.D]    [11]

0x433ca0 FADD	Z0.D, Z0.D, Z4.D

0x433ca4 ADR	Z4.D, [Z19, Z2.D,LSL #3]    [41]

0x433ca8 ADR	Z2.D, [Z23, Z2.D,LSL #3]    [25]

0x433cac LD1D	{Z4.D}, P0/Z, [V4.D]    [4]

0x433cb0 FNMSB	Z0.D, P1/M, Z3.D, Z5.D

0x433cb4 LD1D	{Z2.D}, P0/Z, [V2.D]    [43]

0x433cb8 ADR	Z3.D, [Z31, Z15.D,SXTW #3]    [20]

0x433cbc ADR	Z5.D, [Z9, Z15.D,SXTW #3]    [23]

0x433cc0 FADD	Z2.D, Z2.D, Z4.D

0x433cc4 LDR	D4, [X10]    [32]

0x433cc8 FMLA	Z0.D, P1/M, Z2.D, Z6.D

0x433ccc FMOV	D2, #0.2500000

0x433cd0 ADR	Z6.D, [Z10, Z15.D,SXTW #3]    [14]

0x433cd4 FMUL	D2, D4, D2

0x433cd8 ADR	Z4.D, [Z8, Z15.D,SXTW #3]    [21]

0x433cdc DUP	Z2.D, Z2.D[0]

0x433ce0 FMUL	Z0.D, Z2.D, Z0.D

0x433ce4 LDR	Z2, [X12, #507, MUL VL]    [39]

0x433ce8 MUL	Z2.D, P1/M, Z2.D, Z30.D

0x433cec ADR	Z2.D, [Z3, Z2.D,LSL #3]    [45]

0x433cf0 LDR	Z3, [X12, #505, MUL VL]    [39]

0x433cf4 LD1D	{Z2.D}, P0/Z, [V2.D]    [27]

0x433cf8 MUL	Z3.D, P1/M, Z3.D, Z30.D

0x433cfc ADR	Z3.D, [Z4, Z3.D,LSL #3]    [3]

0x433d00 LDR	Z4, [X12, #504, MUL VL]    [39]

0x433d04 LD1D	{Z3.D}, P0/Z, [V3.D]    [44]

0x433d08 MUL	Z4.D, P1/M, Z4.D, Z30.D

0x433d0c ADR	Z4.D, [Z5, Z4.D,LSL #3]    [8]

0x433d10 LDR	Z5, [X12, #503, MUL VL]    [39]

0x433d14 MUL	Z5.D, P1/M, Z5.D, Z30.D

0x433d18 ADR	Z5.D, [Z6, Z5.D,LSL #3]    [37]

0x433d1c LD1D	{Z6.D}, P0/Z, [V4.D]    [28]

0x433d20 LD1D	{Z5.D}, P0/Z, [V5.D]    [7]

0x433d24 FADD	Z3.D, Z5.D, Z3.D

0x433d28 FMUL	Z5.D, Z6.D, Z2.D

0x433d2c ADR	Z6.D, [Z11, Z15.D,SXTW #3]    [19]

0x433d30 FMUL	Z3.D, Z3.D, Z0.D

0x433d34 FADD	Z0.D, Z0.D, Z2.D

0x433d38 FDIV	Z3.D, P1/M, Z3.D, Z5.D

0x433d3c LDR	Z5, [X12, #501, MUL VL]    [39]

0x433d40 MUL	Z5.D, P1/M, Z5.D, Z30.D

0x433d44 ADR	Z5.D, [Z6, Z5.D,LSL #3]    [36]

0x433d48 ADR	Z6.D, [Z12, Z15.D,SXTW #3]    [22]

0x433d4c LD1D	{Z5.D}, P0/Z, [V5.D]    [33]

0x433d50 FSUB	Z3.D, Z5.D, Z3.D

0x433d54 MOVPRFX	Z5, Z24

0x433d58 MUL	Z5.D, P1/M, Z5.D, Z30.D

0x433d5c MUL	Z30.D, P1/M, Z30.D, Z25.D

0x433d60 ADR	Z5.D, [Z6, Z5.D,LSL #3]    [35]

0x433d64 ST1D	{Z3.D}, P0, [V5.D]    [30]

0x433d68 LD1D	{Z3.D}, P0/Z, [V4.D]    [28]

0x433d6c FMUL	Z2.D, Z3.D, Z2.D

0x433d70 FDIVR	Z0.D, P1/M, Z0.D, Z2.D

0x433d74 ADR	Z2.D, [Z13, Z15.D,SXTW #3]    [24]

0x433d78 ADR	Z2.D, [Z2, Z30.D,LSL #3]    [26]

0x433d7c ST1D	{Z0.D}, P0, [V2.D]    [6]

0x433d80 WHILELO	P0.D, X11, X9

0x433d84 LDR	Z0, [X12, #508, MUL VL]    [39]

0x433d88 ADD	Z14.D, Z14.D, Z0.D

0x433d8c B.MI	433ba8

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 49 - 63

--------------------------------------------------------------------------------

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►98.42+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	PdV(global_variables&, bool)	PdV.cpp:99	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.44 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.75 - 1.15
Bottlenecks	P6, P8,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	PdV.cpp:49-63,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	42.00 - 48.17
CQA cycles if no scalar integer	42.00 - 48.17
CQA cycles if FP arith vectorized	42.00 - 48.17
CQA cycles if fully vectorized	29.16 - 48.17
Front-end cycles	15.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	42.00
P7 cycles	42.00
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	10.83
P11 cycles	10.50
P12 cycles	10.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	14.86 - 48.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	122.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.93 - 1.68
Nb FLOP add-sub	28.00
Nb FLOP mul	21.00
Nb FLOP fma	12.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.68 - 23.72
Bytes prefetched	0.00
Bytes loaded	932.13
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	34.00
Stride indirect	11.00
Vectorization ratio all	61.34
Vectorization ratio load	46.03
Vectorization ratio store	100.00
Vectorization ratio mul	95.00
Vectorization ratio add_sub	27.66
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	28.57
Vector-efficiency ratio all	75.87
Vector-efficiency ratio load	59.52
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	96.25
Vector-efficiency ratio add_sub	45.74
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	87.72

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.44 - 1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.75 - 1.15
Bottlenecks	P6, P8,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source	PdV.cpp:49-63,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	42.00 - 48.17
CQA cycles if no scalar integer	42.00 - 48.17
CQA cycles if FP arith vectorized	42.00 - 48.17
CQA cycles if fully vectorized	29.16 - 48.17
Front-end cycles	15.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	1.00
P5 cycles	0.50
P6 cycles	42.00
P7 cycles	42.00
P8 cycles	11.00
P9 cycles	11.00
P10 cycles	10.83
P11 cycles	10.50
P12 cycles	10.67
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	14.86 - 48.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	122.00
Nb uops	122.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.93 - 1.68
Nb FLOP add-sub	28.00
Nb FLOP mul	21.00
Nb FLOP fma	12.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.68 - 23.72
Bytes prefetched	0.00
Bytes loaded	932.13
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	34.00
Stride indirect	11.00
Vectorization ratio all	61.34
Vectorization ratio load	46.03
Vectorization ratio store	100.00
Vectorization ratio mul	95.00
Vectorization ratio add_sub	27.66
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	28.57
Vector-efficiency ratio all	75.87
Vector-efficiency ratio load	59.52
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	96.25
Vector-efficiency ratio add_sub	45.74
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	87.72

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	PdV.cpp:49-63
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49-63
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 75% of vector register length is used (average across all VPU instructions).

Details

61% of VPU instructions are used in vector version (process two or more data elements in vector registers):

46% of VPU loads are used in vector version.
27% of VPU addition or subtraction instructions are used in vector version.
95% of VPU multiply instructions are used in vector version.
28% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.17 to 40.50 cycles (1.19x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 34 occurrence(s)
Irregular (variable stride) or indirect: 11 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 81 FP arithmetical operations:

40: addition or subtraction (12 inside FMA instructions)
33: multiply (12 inside FMA instructions)
8: divide

The binary loop is loading 932 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	122
nb uops	122
loop length	488
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	9
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.25 cycles
front end	15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	42.00	42.00	11.00	11.00	10.83	10.50	10.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	42.00	42.00	11.00	11.00	10.83	10.50	10.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-48.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.25
Dispatch	42.00
DIV/SQRT	14.86-48.17
Data deps.	2.00
Overall L1	42.00-48.17

Vectorization ratios

INT

all	56%
load	46%
store	100%
mul	100%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	89%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	83%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

INT+FP

all	61%
load	46%
store	100%
mul	95%
add-sub	27%
fma	100%
div/sqrt	100%
other	28%

Vector efficiency ratios

INT

all	72%
load	59%
store	100%
mul	100%
add-sub	36%
fma	NA (no fma vectorizable/vectorized instructions)
other	93%

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	87%
add-sub	100%
fma	100%
div/sqrt	100%
other	25%

INT+FP

all	75%
load	59%
store	100%
mul	96%
add-sub	45%
fma	100%
div/sqrt	100%
other	87%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.17 cycles. At this rate:

20% of peak load performance is reached (19.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 433ba8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR Z2, [X12, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z6, [X12, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SEL Z22.D, P0, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SDIVR Z22.D, P1/M, Z22.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z30.D, Z0.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z0, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z0.D, P1/M, Z22.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SXTW Z30.D, P1/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z4, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P1/M, Z4.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z7, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z7.D, P1/M, Z7.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z15.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z2, [X12, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z0.D, Z0.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z6, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z6.D, P1/M, Z6.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z27, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z19.D, [Z29, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z23.D, [Z29, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z16.D, [Z5, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z20.D, [Z19, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z23, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z3, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z3.D, P1/M, Z3.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LDR Z2, [X12, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z22.D, Z22.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z22.D, P1/M, Z22.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z2, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z2.D, P1/M, Z2.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z7.D, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z5.D, [Z5, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z5.D, Z5.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z16.D, [Z28, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z16, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z6.D, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z7.D, [Z26, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z7, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z7.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z5.D, P1/M, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z6.D, [Z26, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z27, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z0, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z0, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z2, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z2.D, P1/M, Z2.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z22.D, P1/M, Z22.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z3.D, [Z6, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z16, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z4.D, [Z19, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z23, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FNMSB Z0.D, P1/M, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z3.D, [Z31, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z9, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR D4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMLA Z0.D, P1/M, Z2.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMOV D2, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADR Z6.D, [Z10, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL D2, D4, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
ADR Z4.D, [Z8, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
DUP Z2.D, Z2.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LDR Z2, [X12, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MUL Z2.D, P1/M, Z2.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z2.D, [Z3, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z3, [X12, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z3.D, P1/M, Z3.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z3.D, [Z4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z4, [X12, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z4.D, P1/M, Z4.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z4.D, [Z5, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z5, [X12, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MUL Z5.D, P1/M, Z5.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, Z6.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z6.D, [Z11, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z3.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z3.D, P1/M, Z3.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LDR Z5, [X12, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MUL Z5.D, P1/M, Z5.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z12, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z5, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P1/M, Z5.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z30.D, P1/M, Z30.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z3.D}, P0, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z0.D, P1/M, Z0.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z2.D, [Z13, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z2, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P0.D, X11, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LDR Z0, [X12, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z14.D, Z14.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
B.MI 433ba8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined]
Source file and lines	PdV.cpp:49-63
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:49-63
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 75% of vector register length is used (average across all VPU instructions).

Details

61% of VPU instructions are used in vector version (process two or more data elements in vector registers):

46% of VPU loads are used in vector version.
27% of VPU addition or subtraction instructions are used in vector version.
95% of VPU multiply instructions are used in vector version.
28% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 48.17 to 40.50 cycles (1.19x speedup).

FMA

Detected 12 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 34 occurrence(s)
Irregular (variable stride) or indirect: 11 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 81 FP arithmetical operations:

40: addition or subtraction (12 inside FMA instructions)
33: multiply (12 inside FMA instructions)
8: divide

The binary loop is loading 932 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	122
nb uops	122
loop length	488
used w registers	0
used x registers	6
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	9
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	1.17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.25 cycles
front end	15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	1.00	0.50	42.00	42.00	11.00	11.00	10.83	10.50	10.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	1.00	0.50	42.00	42.00	11.00	11.00	10.83	10.50	10.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-48.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	15.25
Dispatch	42.00
DIV/SQRT	14.86-48.17
Data deps.	2.00
Overall L1	42.00-48.17

Vectorization ratios

INT

all	56%
load	46%
store	100%
mul	100%
add-sub	15%
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	89%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	83%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

INT+FP

all	61%
load	46%
store	100%
mul	95%
add-sub	27%
fma	100%
div/sqrt	100%
other	28%

Vector efficiency ratios

INT

all	72%
load	59%
store	100%
mul	100%
add-sub	36%
fma	NA (no fma vectorizable/vectorized instructions)
other	93%

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	87%
add-sub	100%
fma	100%
div/sqrt	100%
other	25%

INT+FP

all	75%
load	59%
store	100%
mul	96%
add-sub	45%
fma	100%
div/sqrt	100%
other	87%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 48.17 cycles. At this rate:

20% of peak load performance is reached (19.35 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 433ba8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X12, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X11, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
LDR Z2, [X12, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z6, [X12, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SEL Z22.D, P0, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X12, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SDIVR Z22.D, P1/M, Z22.D, Z14.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z30.D, Z0.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z0, Z14	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z0.D, P1/M, Z22.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
SXTW Z30.D, P1/M, Z30.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z4, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P1/M, Z4.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z7, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z7.D, P1/M, Z7.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z15.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z2, [X12, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z0.D, Z0.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z6, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z6.D, P1/M, Z6.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z27, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z19.D, [Z29, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z23.D, [Z29, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z16.D, [Z5, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z20.D, [Z19, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z23, Z7.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z3, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z3.D, P1/M, Z3.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LDR Z2, [X12, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z16.D}, P0/Z, [V16.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADD Z22.D, Z22.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
SXTW Z22.D, P1/M, Z22.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z2, Z17	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z2.D, P1/M, Z2.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LD1D {Z20.D}, P0/Z, [V20.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z7.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z7.D, Z7.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z5.D, [Z5, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z5.D, Z5.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z16.D, [Z28, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z16, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z6.D, Z6.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z7.D, [Z26, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z7.D, [Z7, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z7.D}, P0/Z, [V7.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMAD Z5.D, P1/M, Z7.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
ADR Z6.D, [Z26, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z27, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z0, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z0, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z2, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z2.D, P1/M, Z2.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z22.D, P1/M, Z22.D, Z21.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z3.D, [Z6, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z16, Z22.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z0.D}, P0/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z6.D}, P0/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z0.D, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z4.D, [Z19, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z23, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z4.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FNMSB Z0.D, P1/M, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z3.D, [Z31, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z9, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR D4, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
FMLA Z0.D, P1/M, Z2.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
FMOV D2, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
ADR Z6.D, [Z10, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL D2, D4, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
ADR Z4.D, [Z8, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
DUP Z2.D, Z2.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LDR Z2, [X12, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MUL Z2.D, P1/M, Z2.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z2.D, [Z3, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z3, [X12, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z2.D}, P0/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z3.D, P1/M, Z3.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z3.D, [Z4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z4, [X12, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z4.D, P1/M, Z4.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z4.D, [Z5, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z5, [X12, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MUL Z5.D, P1/M, Z5.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z5.D, Z6.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
ADR Z6.D, [Z11, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z3.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FDIV Z3.D, P1/M, Z3.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LDR Z5, [X12, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MUL Z5.D, P1/M, Z5.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z12, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z5.D}, P0/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FSUB Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z5, Z24	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P1/M, Z5.D, Z30.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z30.D, P1/M, Z30.D, Z25.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z3.D}, P0, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z3.D}, P0/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z0.D, P1/M, Z0.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
ADR Z2.D, [Z13, Z15.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z2, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z0.D}, P0, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P0.D, X11, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
LDR Z0, [X12, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADD Z14.D, Z14.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
B.MI 433ba8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code