OV - exec - Loop 254

	Loop Id: 254	Module: exec	Source: PdV.cpp:70-83 [...]	Coverage: 7.82%

0x433fe0 DUP	Z0.D, #1

0x433fe4 SUB	X16, X29, #64

0x433fe8 ADD	X15, X15, X9

0x433fec LDR	Z2, [X16, #507, MUL VL]    [51]

0x433ff0 LDR	Z3, [X16, #509, MUL VL]    [51]

0x433ff4 LDR	Z30, [X16, #508, MUL VL]    [51]

0x433ff8 SEL	Z12.D, P1, Z1.D, Z0.D

0x433ffc LDR	Z0, [X16, #511, MUL VL]    [51]

0x434000 MOVPRFX	Z13, Z29

0x434004 SDIV	Z13.D, P0/M, Z13.D, Z12.D

0x434008 ADD	Z12.D, Z0.D, Z13.D

0x43400c MOVPRFX	Z0, Z29

0x434010 MLS	Z0.D, P0/M, Z13.D, Z1.D

0x434014 ADD	Z13.D, Z13.D, Z3.D

0x434018 ADD	Z29.D, Z29.D, Z14.D

0x43401c MOVPRFX	Z15, Z12

0x434020 SXTW	Z15.D, P0/M, Z12.D

0x434024 SXTW	Z13.D, P0/M, Z13.D

0x434028 MOVPRFX	Z5, Z2

0x43402c MUL	Z5.D, P0/M, Z5.D, Z15.D

0x434030 LDR	Z2, [X16, #510, MUL VL]    [51]

0x434034 MOVPRFX	Z6, Z20

0x434038 MUL	Z6.D, P0/M, Z6.D, Z15.D

0x43403c MOVPRFX	Z3, Z20

0x434040 MUL	Z3.D, P0/M, Z3.D, Z13.D

0x434044 MOVPRFX	Z17, Z28

0x434048 MUL	Z17.D, P0/M, Z17.D, Z15.D

0x43404c MOVPRFX	Z25, Z28

0x434050 MUL	Z25.D, P0/M, Z25.D, Z13.D

0x434054 ADD	Z12.D, Z2.D, Z0.D

0x434058 ADD	Z0.D, Z0.D, Z30.D

0x43405c ADR	Z4.D, [Z16, Z12.D,SXTW #3]    [32]

0x434060 ADR	Z26.D, [Z19, Z12.D,SXTW #3]    [48]

0x434064 ADR	Z31.D, [Z16, Z0.D,SXTW #3]    [32]

0x434068 ADR	Z30.D, [Z7, Z0.D,SXTW #3]    [13]

0x43406c ADR	Z8.D, [Z7, Z12.D,SXTW #3]    [13]

0x434070 ADR	Z2.D, [Z4, Z6.D,LSL #3]    [4]

0x434074 ADR	Z4.D, [Z4, Z3.D,LSL #3]    [4]

0x434078 ADR	Z27.D, [Z26, Z17.D,LSL #3]    [38]

0x43407c ADR	Z26.D, [Z26, Z25.D,LSL #3]    [38]

0x434080 ADR	Z6.D, [Z31, Z6.D,LSL #3]    [15]

0x434084 ADR	Z3.D, [Z31, Z3.D,LSL #3]    [15]

0x434088 ADR	Z30.D, [Z30, Z5.D,LSL #3]    [12]

0x43408c ADR	Z5.D, [Z8, Z5.D,LSL #3]    [16]

0x434090 LD1D	{Z2.D}, P1/Z, [V2.D]    [58]

0x434094 LD1D	{Z4.D}, P1/Z, [V4.D]    [3]

0x434098 LD1D	{Z27.D}, P1/Z, [V27.D]    [47]

0x43409c LD1D	{Z26.D}, P1/Z, [V26.D]    [36]

0x4340a0 LD1D	{Z6.D}, P1/Z, [V6.D]    [9]

0x4340a4 LD1D	{Z3.D}, P1/Z, [V3.D]    [60]

0x4340a8 LD1D	{Z30.D}, P1/Z, [V30.D]    [11]

0x4340ac LD1D	{Z5.D}, P1/Z, [V5.D]    [6]

0x4340b0 FADD	Z2.D, Z4.D, Z2.D

0x4340b4 FADD	Z4.D, Z27.D, Z26.D

0x4340b8 FADD	Z3.D, Z3.D, Z6.D

0x4340bc ADR	Z6.D, [Z23, Z12.D,SXTW #3]    [17]

0x4340c0 ADR	Z26.D, [Z24, Z12.D,SXTW #3]    [18]

0x4340c4 FADD	Z2.D, Z2.D, Z4.D

0x4340c8 ADR	Z4.D, [Z19, Z0.D,SXTW #3]    [48]

0x4340cc ADR	Z17.D, [Z4, Z17.D,LSL #3]    [2]

0x4340d0 ADR	Z4.D, [Z4, Z25.D,LSL #3]    [2]

0x4340d4 ADR	Z25.D, [Z23, Z0.D,SXTW #3]    [17]

0x4340d8 ADR	Z0.D, [Z24, Z0.D,SXTW #3]    [18]

0x4340dc FMUL	Z2.D, Z2.D, Z5.D

0x4340e0 LDR	D5, [X8]    [52]

0x4340e4 LD1D	{Z17.D}, P1/Z, [V17.D]    [45]

0x4340e8 LD1D	{Z4.D}, P1/Z, [V4.D]    [1]

0x4340ec FADD	Z4.D, Z17.D, Z4.D

0x4340f0 FADD	Z3.D, Z3.D, Z4.D

0x4340f4 MOVPRFX	Z4, Z21

0x4340f8 MUL	Z4.D, P0/M, Z4.D, Z15.D

0x4340fc FMUL	Z3.D, Z3.D, Z30.D

0x434100 MOVPRFX	Z30, Z18

0x434104 MUL	Z30.D, P0/M, Z30.D, Z15.D

0x434108 ADR	Z17.D, [Z6, Z4.D,LSL #3]    [8]

0x43410c ADR	Z4.D, [Z25, Z4.D,LSL #3]    [27]

0x434110 LD1D	{Z17.D}, P1/Z, [V17.D]    [44]

0x434114 LD1D	{Z4.D}, P1/Z, [V4.D]    [31]

0x434118 FADD	Z4.D, Z4.D, Z17.D

0x43411c MOVPRFX	Z17, Z22

0x434120 MUL	Z17.D, P0/M, Z17.D, Z15.D

0x434124 ADR	Z27.D, [Z26, Z17.D,LSL #3]    [35]

0x434128 ADR	Z17.D, [Z0, Z17.D,LSL #3]    [50]

0x43412c LD1D	{Z27.D}, P1/Z, [V27.D]    [46]

0x434130 LD1D	{Z17.D}, P1/Z, [V17.D]    [43]

0x434134 FADD	Z17.D, Z27.D, Z17.D

0x434138 MOVPRFX	Z27, Z21

0x43413c MUL	Z27.D, P0/M, Z27.D, Z13.D

0x434140 FADD	Z4.D, Z4.D, Z17.D

0x434144 LDR	Z17, [X16, #506, MUL VL]    [51]

0x434148 ADR	Z6.D, [Z6, Z27.D,LSL #3]    [8]

0x43414c ADR	Z25.D, [Z25, Z27.D,LSL #3]    [27]

0x434150 MOVPRFX	Z27, Z18

0x434154 MUL	Z27.D, P0/M, Z27.D, Z13.D

0x434158 ADR	Z17.D, [Z17, Z12.D,SXTW #3]    [57]

0x43415c LD1D	{Z6.D}, P1/Z, [V6.D]    [7]

0x434160 LD1D	{Z25.D}, P1/Z, [V25.D]    [26]

0x434164 MUL	Z13.D, P0/M, Z13.D, Z22.D

0x434168 ADR	Z0.D, [Z0, Z13.D,LSL #3]    [50]

0x43416c ADR	Z30.D, [Z17, Z30.D,LSL #3]    [56]

0x434170 ADR	Z17.D, [Z17, Z27.D,LSL #3]    [56]

0x434174 FADD	Z6.D, Z25.D, Z6.D

0x434178 ADR	Z25.D, [Z26, Z13.D,LSL #3]    [35]

0x43417c LD1D	{Z0.D}, P1/Z, [V0.D]    [49]

0x434180 LD1D	{Z17.D}, P1/Z, [V17.D]    [55]

0x434184 LD1D	{Z25.D}, P1/Z, [V25.D]    [24]

0x434188 FADD	Z0.D, Z25.D, Z0.D

0x43418c FADD	Z0.D, Z6.D, Z0.D

0x434190 FMAD	Z0.D, P0/M, Z17.D, Z3.D

0x434194 LDR	Z3, [X16, #503, MUL VL]    [51]

0x434198 LD1D	{Z6.D}, P1/Z, [V30.D]    [10]

0x43419c DUP	Z17.D, X11

0x4341a0 ADR	Z17.D, [Z17, Z12.D,SXTW #3]    [54]

0x4341a4 ADR	Z3.D, [Z3, Z12.D,SXTW #3]    [59]

0x4341a8 FMLA	Z2.D, P0/M, Z4.D, Z6.D

0x4341ac LDR	Z4, [X16, #502, MUL VL]    [51]

0x4341b0 LDR	Z6, [X16, #500, MUL VL]    [51]

0x4341b4 FSUB	Z0.D, Z0.D, Z2.D

0x4341b8 FMOV	D2, #0.2500000

0x4341bc FMUL	D2, D5, D2

0x4341c0 ADR	Z4.D, [Z4, Z12.D,SXTW #3]    [30]

0x4341c4 MUL	Z6.D, P0/M, Z6.D, Z15.D

0x4341c8 ADR	Z5.D, [Z11, Z12.D,SXTW #3]    [14]

0x4341cc DUP	Z2.D, Z2.D[0]

0x4341d0 FMUL	Z0.D, Z2.D, Z0.D

0x4341d4 LDR	Z2, [X16, #505, MUL VL]    [51]

0x4341d8 ADR	Z6.D, [Z17, Z6.D,LSL #3]    [53]

0x4341dc MUL	Z2.D, P0/M, Z2.D, Z15.D

0x4341e0 ADR	Z2.D, [Z3, Z2.D,LSL #3]    [25]

0x4341e4 LDR	Z3, [X16, #504, MUL VL]    [51]

0x4341e8 LD1D	{Z6.D}, P1/Z, [V6.D]    [42]

0x4341ec MUL	Z3.D, P0/M, Z3.D, Z15.D

0x4341f0 ADR	Z3.D, [Z4, Z3.D,LSL #3]    [29]

0x4341f4 LDR	Z4, [X16, #501, MUL VL]    [51]

0x4341f8 LD1D	{Z2.D}, P1/Z, [V2.D]    [22]

0x4341fc MUL	Z4.D, P0/M, Z4.D, Z15.D

0x434200 ADR	Z4.D, [Z5, Z4.D,LSL #3]    [5]

0x434204 LD1D	{Z3.D}, P1/Z, [V3.D]    [23]

0x434208 FADD	Z3.D, Z6.D, Z3.D

0x43420c DUP	Z6.D, X12

0x434210 FMUL	Z3.D, Z3.D, Z0.D

0x434214 FADD	Z0.D, Z0.D, Z2.D

0x434218 LD1D	{Z5.D}, P1/Z, [V4.D]    [28]

0x43421c ADR	Z6.D, [Z6, Z12.D,SXTW #3]    [41]

0x434220 FMUL	Z5.D, Z5.D, Z2.D

0x434224 FDIV	Z3.D, P0/M, Z3.D, Z5.D

0x434228 LDR	Z5, [X16, #499, MUL VL]    [51]

0x43422c MUL	Z5.D, P0/M, Z5.D, Z15.D

0x434230 ADR	Z5.D, [Z6, Z5.D,LSL #3]    [40]

0x434234 DUP	Z6.D, X13

0x434238 LD1D	{Z5.D}, P1/Z, [V5.D]    [34]

0x43423c ADR	Z6.D, [Z6, Z12.D,SXTW #3]    [39]

0x434240 FSUB	Z3.D, Z5.D, Z3.D

0x434244 MOVPRFX	Z5, Z9

0x434248 MUL	Z5.D, P0/M, Z5.D, Z15.D

0x43424c MUL	Z15.D, P0/M, Z15.D, Z10.D

0x434250 ADR	Z5.D, [Z6, Z5.D,LSL #3]    [37]

0x434254 ST1D	{Z3.D}, P1, [V5.D]    [33]

0x434258 LD1D	{Z3.D}, P1/Z, [V4.D]    [28]

0x43425c FMUL	Z2.D, Z3.D, Z2.D

0x434260 FDIVR	Z0.D, P0/M, Z0.D, Z2.D

0x434264 DUP	Z2.D, X14

0x434268 ADR	Z2.D, [Z2, Z12.D,SXTW #3]    [21]

0x43426c ADR	Z2.D, [Z2, Z15.D,LSL #3]    [20]

0x434270 ST1D	{Z0.D}, P1, [V2.D]    [19]

0x434274 WHILELO	P1.D, X15, X10

0x434278 B.MI	433fe0

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 70 - 83

--------------------------------------------------------------------------------

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module
►98.56+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_launch_thread		libomp.so
○	__kmp_launch_worker(void*)		libomp.so
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.44+	__kmp_invoke_microtask		libomp.so
○	__kmp_invoke_task_func		libomp.so
○	__kmp_fork_call		libomp.so
○	__kmpc_fork_call		libomp.so
○	PdV(global_variables&, bool)	PdV.cpp:99	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1077	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	ostream:93	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.43 - 1.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.1]
Source	PdV.cpp:70-83,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	57.50
CQA cycles if no scalar integer	57.50
CQA cycles if FP arith vectorized	57.50
CQA cycles if fully vectorized	40.16 - 48.17
Front-end cycles	20.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	5.00
P5 cycles	0.50
P6 cycles	57.50
P7 cycles	57.50
P8 cycles	15.00
P9 cycles	15.00
P10 cycles	14.17
P11 cycles	13.83
P12 cycles	14.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	14.86 - 48.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	167.00
Nb uops	167.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.97
Nb FLOP add-sub	64.00
Nb FLOP mul	25.00
Nb FLOP fma	8.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.92
Bytes prefetched	0.00
Bytes loaded	1253.63
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	46.00
Stride indirect	13.00
Vectorization ratio all	58.90
Vectorization ratio load	45.88
Vectorization ratio store	100.00
Vectorization ratio mul	96.00
Vectorization ratio add_sub	32.84
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	16.67
Vector-efficiency ratio all	75.48
Vector-efficiency ratio load	59.41
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	97.00
Vector-efficiency ratio add_sub	49.63
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	80.34

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.43 - 1.19
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P6, P7,
Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.1]
Source	PdV.cpp:70-83,context.h:69-69
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	57.50
CQA cycles if no scalar integer	57.50
CQA cycles if FP arith vectorized	57.50
CQA cycles if fully vectorized	40.16 - 48.17
Front-end cycles	20.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	5.00
P5 cycles	0.50
P6 cycles	57.50
P7 cycles	57.50
P8 cycles	15.00
P9 cycles	15.00
P10 cycles	14.17
P11 cycles	13.83
P12 cycles	14.00
P13 cycles	0.00
P14 cycles	0.00
DIV/SQRT cycles	14.86 - 48.17
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	167.00
Nb uops	167.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	1.97
Nb FLOP add-sub	64.00
Nb FLOP mul	25.00
Nb FLOP fma	8.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.92
Bytes prefetched	0.00
Bytes loaded	1253.63
Bytes stored	64.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	46.00
Stride indirect	13.00
Vectorization ratio all	58.90
Vectorization ratio load	45.88
Vectorization ratio store	100.00
Vectorization ratio mul	96.00
Vectorization ratio add_sub	32.84
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	16.67
Vector-efficiency ratio all	75.48
Vector-efficiency ratio load	59.41
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	97.00
Vector-efficiency ratio add_sub	49.63
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	80.34

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.1]
Source file and lines	PdV.cpp:70-83
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70-83
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 75% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 57.50 to 48.17 cycles (1.19x speedup).

Details

58% of VPU instructions are used in vector version (process two or more data elements in vector registers):

45% of VPU loads are used in vector version.
32% of VPU addition or subtraction instructions are used in vector version.
96% of VPU multiply instructions are used in vector version.
16% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 46 occurrence(s)
Irregular (variable stride) or indirect: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 113 FP arithmetical operations:

72: addition or subtraction (8 inside FMA instructions)
33: multiply (8 inside FMA instructions)
8: divide

The binary loop is loading 1253 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	167
nb uops	167
loop length	668
used w registers	0
used x registers	10
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	11
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	2.29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.88 cycles
front end	20.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	5.00	0.50	57.50	57.50	15.00	15.00	14.17	13.83	14.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	5.00	0.50	57.50	57.50	15.00	15.00	14.17	13.83	14.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-48.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	20.88
Dispatch	57.50
DIV/SQRT	14.86-48.17
Data deps.	2.00
Overall L1	57.50

Vectorization ratios

INT

all	51%
load	45%
store	100%
mul	100%
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	85%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

INT+FP

all	58%
load	45%
store	100%
mul	96%
add-sub	32%
fma	100%
div/sqrt	100%
other	16%

Vector efficiency ratios

INT

all	71%
load	59%
store	100%
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	83%

all	94%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	89%
add-sub	100%
fma	100%
div/sqrt	100%
other	25%

INT+FP

all	75%
load	59%
store	100%
mul	97%
add-sub	49%
fma	100%
div/sqrt	100%
other	80%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 57.50 cycles. At this rate:

22% of peak load performance is reached (21.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 433fe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X16, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z2, [X16, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z3, [X16, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z30, [X16, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SEL Z12.D, P1, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X16, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SDIV Z13.D, P0/M, Z13.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z12.D, Z0.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z0, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z0.D, P0/M, Z13.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z13.D, Z13.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z29.D, Z29.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z15, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z15.D, P0/M, Z12.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SXTW Z13.D, P0/M, Z13.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z5, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P0/M, Z5.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LDR Z2, [X16, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z6, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z3, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z3.D, P0/M, Z3.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z17, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z17.D, P0/M, Z17.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z25, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z25.D, P0/M, Z25.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z12.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z0.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z4.D, [Z16, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z19, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z16, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z7, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z7, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z4, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z26, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z26, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z31, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z31, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z30, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z8, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z2.D}, P1/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z26.D}, P1/Z, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z3.D}, P1/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z30.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P1/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z2.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z4.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z6.D, [Z23, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z24, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z4.D, [Z19, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z4, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z4, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z25.D, [Z23, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z24, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z2.D, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LDR D5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1D {Z17.D}, P1/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z4.D, Z17.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z4, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P0/M, Z4.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMUL Z3.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z30, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z30.D, P0/M, Z30.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z17.D, [Z6, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z25, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z17.D}, P1/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z4.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z17, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z17.D, P0/M, Z17.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z27.D, [Z26, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z0, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z17.D}, P1/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z17.D, Z27.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z27, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FADD Z4.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z17, [X16, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z6.D, [Z6, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z25.D, [Z25, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z27, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z17.D, [Z17, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z25.D}, P1/Z, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z13.D, P0/M, Z13.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z0.D, [Z0, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z17, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z17, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z6.D, Z25.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z25.D, [Z26, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z0.D}, P1/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z17.D}, P1/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z25.D}, P1/Z, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z0.D, Z25.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z0.D, Z6.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z0.D, P0/M, Z17.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z3, [X16, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z6.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
DUP Z17.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADR Z17.D, [Z17, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z3, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMLA Z2.D, P0/M, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z4, [X16, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z6, [X16, #500, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMOV D2, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D2, D5, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
ADR Z4.D, [Z4, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z11, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
DUP Z2.D, Z2.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LDR Z2, [X16, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z6.D, [Z17, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MUL Z2.D, P0/M, Z2.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z2.D, [Z3, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z3, [X16, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z3.D, P0/M, Z3.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z3.D, [Z4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z4, [X16, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z2.D}, P1/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z4.D, P0/M, Z4.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z4.D, [Z5, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z3.D}, P1/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z3.D, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z6.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
FMUL Z3.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z5.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z6.D, [Z6, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z5.D, Z5.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z3.D, P0/M, Z3.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LDR Z5, [X16, #499, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MUL Z5.D, P0/M, Z5.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
DUP Z6.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LD1D {Z5.D}, P1/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z6.D, [Z6, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FSUB Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z5, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P0/M, Z5.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z15.D, P0/M, Z15.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z3.D}, P1, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z3.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
DUP Z2.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADR Z2.D, [Z2, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z2, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z0.D}, P1, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X15, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 433fe0 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.1+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.1]
Source file and lines	PdV.cpp:70-83
Module	exec

The loop is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:70-83
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

58% of VPU instructions are used in vector version (process two or more data elements in vector registers):

45% of VPU loads are used in vector version.
32% of VPU addition or subtraction instructions are used in vector version.
96% of VPU multiply instructions are used in vector version.
16% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 46 occurrence(s)
Irregular (variable stride) or indirect: 13 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 113 FP arithmetical operations:

72: addition or subtraction (8 inside FMA instructions)
33: multiply (8 inside FMA instructions)
8: divide

The binary loop is loading 1253 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	167
nb uops	167
loop length	668
used w registers	0
used x registers	10
used b registers	0
used h registers	0
used s registers	0
used d registers	2
used q registers	0
used v registers	11
used z registers	32
nb stack references	0
ADD-SUB / MUL ratio	2.29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.88 cycles
front end	20.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	5.00	0.50	57.50	57.50	15.00	15.00	14.17	13.83	14.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	5.00	0.50	57.50	57.50	15.00	15.00	14.17	13.83	14.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	14.86-48.17
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	20.88
Dispatch	57.50
DIV/SQRT	14.86-48.17
Data deps.	2.00
Overall L1	57.50

Vectorization ratios

INT

all	51%
load	45%
store	100%
mul	100%
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	85%
add-sub	100%
fma	100%
div/sqrt	100%
other	0%

INT+FP

all	58%
load	45%
store	100%
mul	96%
add-sub	32%
fma	100%
div/sqrt	100%
other	16%

Vector efficiency ratios

INT

all	71%
load	59%
store	100%
mul	100%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	83%

all	94%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	89%
add-sub	100%
fma	100%
div/sqrt	100%
other	25%

INT+FP

all	75%
load	59%
store	100%
mul	97%
add-sub	49%
fma	100%
div/sqrt	100%
other	80%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 57.50 cycles. At this rate:

22% of peak load performance is reached (21.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 433fe0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
DUP Z0.D, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (3.1%)
SUB X16, X29, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
ADD X15, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25	N/A
LDR Z2, [X16, #507, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z3, [X16, #509, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z30, [X16, #508, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
SEL Z12.D, P1, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z0, [X16, #511, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z13, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SDIV Z13.D, P0/M, Z13.D, Z12.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-20	0.87-20	vect (100.0%)
ADD Z12.D, Z0.D, Z13.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z0, Z29	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MLS Z0.D, P0/M, Z13.D, Z1.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z13.D, Z13.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z29.D, Z29.D, Z14.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z15, Z12	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
SXTW Z15.D, P0/M, Z12.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
SXTW Z13.D, P0/M, Z13.D	1	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	vect (100.0%)
MOVPRFX Z5, Z2	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P0/M, Z5.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
LDR Z2, [X16, #510, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MOVPRFX Z6, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z3, Z20	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z3.D, P0/M, Z3.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z17, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z17.D, P0/M, Z17.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MOVPRFX Z25, Z28	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z25.D, P0/M, Z25.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADD Z12.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADD Z0.D, Z0.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z4.D, [Z16, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z19, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z31.D, [Z16, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z7, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z8.D, [Z7, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z4, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z27.D, [Z26, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z26, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z6.D, [Z31, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z31, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z30, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z5.D, [Z8, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z2.D}, P1/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z26.D}, P1/Z, [V26.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z3.D}, P1/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z30.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z5.D}, P1/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z2.D, Z4.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z4.D, Z27.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z6.D, [Z23, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z26.D, [Z24, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z4.D, [Z19, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z4, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z4, Z25.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z25.D, [Z23, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z0.D, [Z24, Z0.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z2.D, Z2.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LDR D5, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (25.0%)
LD1D {Z17.D}, P1/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z4.D, Z17.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z3.D, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z4, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z4.D, P0/M, Z4.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FMUL Z3.D, Z3.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
MOVPRFX Z30, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z30.D, P0/M, Z30.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z17.D, [Z6, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z4.D, [Z25, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z17.D}, P1/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z4.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z4.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z17, Z22	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z17.D, P0/M, Z17.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z27.D, [Z26, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z0, Z17.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z27.D}, P1/Z, [V27.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z17.D}, P1/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z17.D, Z27.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z27, Z21	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
FADD Z4.D, Z4.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LDR Z17, [X16, #506, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z6.D, [Z6, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z25.D, [Z25, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MOVPRFX Z27, Z18	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z27.D, P0/M, Z27.D, Z13.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z17.D, [Z17, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z25.D}, P1/Z, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z13.D, P0/M, Z13.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z0.D, [Z0, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z30.D, [Z17, Z30.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z17.D, [Z17, Z27.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FADD Z6.D, Z25.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
ADR Z25.D, [Z26, Z13.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z0.D}, P1/Z, [V0.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z17.D}, P1/Z, [V17.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
LD1D {Z25.D}, P1/Z, [V25.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z0.D, Z25.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FADD Z0.D, Z6.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMAD Z0.D, P0/M, Z17.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z3, [X16, #503, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z6.D}, P1/Z, [V30.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
DUP Z17.D, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADR Z17.D, [Z17, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z3.D, [Z3, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMLA Z2.D, P0/M, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	4	0.50	vect (100.0%)
LDR Z4, [X16, #502, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LDR Z6, [X16, #500, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
FSUB Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMOV D2, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
FMUL D2, D5, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (25.0%)
ADR Z4.D, [Z4, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MUL Z6.D, P0/M, Z6.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z11, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
DUP Z2.D, Z2.D[0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
FMUL Z0.D, Z2.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
LDR Z2, [X16, #505, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
ADR Z6.D, [Z17, Z6.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
MUL Z2.D, P0/M, Z2.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z2.D, [Z3, Z2.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z3, [X16, #504, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z6.D}, P1/Z, [V6.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z3.D, P0/M, Z3.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z3.D, [Z4, Z3.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LDR Z4, [X16, #501, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
LD1D {Z2.D}, P1/Z, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
MUL Z4.D, P0/M, Z4.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z4.D, [Z5, Z4.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
LD1D {Z3.D}, P1/Z, [V3.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FADD Z3.D, Z6.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
DUP Z6.D, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
FMUL Z3.D, Z3.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FADD Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
LD1D {Z5.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z6.D, [Z6, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FMUL Z5.D, Z5.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIV Z3.D, P0/M, Z3.D, Z5.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
LDR Z5, [X16, #499, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	6	0.50	vect (100.0%)
MUL Z5.D, P0/M, Z5.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
DUP Z6.D, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
LD1D {Z5.D}, P1/Z, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
ADR Z6.D, [Z6, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
FSUB Z3.D, Z5.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	vect (100.0%)
MOVPRFX Z5, Z9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (100.0%)
MUL Z5.D, P0/M, Z5.D, Z15.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
MUL Z15.D, P0/M, Z15.D, Z10.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	5	2	vect (100.0%)
ADR Z5.D, [Z6, Z5.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z3.D}, P1, [V5.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
LD1D {Z3.D}, P1/Z, [V4.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	9	2	vect (100.0%)
FMUL Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	3	0.50	vect (100.0%)
FDIVR Z0.D, P0/M, Z0.D, Z2.D	1	0	0	0	0	0	0	1	0	0	0	0	0	0	7-15	6.99-14.08	vect (100.0%)
DUP Z2.D, X14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	1	scal (25.0%)
ADR Z2.D, [Z2, Z12.D,SXTW #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ADR Z2.D, [Z2, Z15.D,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50	scal (25.0%)
ST1D {Z0.D}, P1, [V2.D]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	6	2	vect (100.0%)
WHILELO P1.D, X15, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2	N/A
B.MI 433fe0 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined.1+0x200>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code