OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:48-63 [...]	Coverage (incl. loops): 6.65% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 48 - 63

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48: #pragma omp parallel for simd collapse(2)

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x43d5c0 STP	X29, X30, [SP, #656]!

0x43d5c4 ADD	X29, SP, #0

0x43d5c8 STP	X19, X20, [SP, #16]

0x43d5cc ORR	X20, XZR, X0

0x43d5d0 STP	X21, X22, [SP, #32]

0x43d5d4 LDP	W22, W1, [X0, #104]

0x43d5d8 LDR	W0, [X0, #96]

0x43d5dc LDR	W2, [X20, #100]

0x43d5e0 ADD	W3, W1, #2

0x43d5e4 ADD	W22, W22, #1

0x43d5e8 ADD	W4, W0, #1

0x43d5ec STR	W3, [SP, #264]

0x43d5f0 STR	W4, [SP, #268]

0x43d5f4 CMP	W22, W3

0x43d5f8 B.GE	43daec

0x43d5fc ADD	W19, W2, #2

0x43d600 STP	X23, X24, [SP, #48]

0x43d604 SUB	W23, W3, W22

0x43d608 CMP	W4, W19

0x43d60c B.GE	43dae8

0x43d610 SUB	W5, W19, W4

0x43d614 MUL	W24, W23, W5

0x43d618 STR	W5, [SP, #272]

0x43d61c BL	410210

0x43d620 ORR	W21, WZR, W0

0x43d624 BL	410240

0x43d628 UDIV	W7, W24, W21

0x43d62c ORR	W6, WZR, W0

0x43d630 MSUB	W8, W7, W21, W24

0x43d634 CMP	W0, W8

0x43d638 B.CC	43db18

0x43d63c MADD	W23, W7, W6, W8

0x43d640 ADD	W9, W7, W23

0x43d644 STR	W9, [SP, #276]

0x43d648 CMP	W23, W9

0x43d64c B.CS	43dae8

0x43d650 LDR	W10, [SP, #272]

0x43d654 FMOV	D30, #0.1250000

0x43d658 STP	X25, X26, [SP, #64]

0x43d65c STP	X27, X28, [SP, #80]

0x43d660 UDIV	W11, W23, W10

0x43d664 LDR	D31, [X20]

0x43d668 LDR	X25, [X20, #24]

0x43d66c LDR	X28, [X20, #64]

0x43d670 LDR	X14, [X20, #8]

0x43d674 FMUL	D30, D31, D30

0x43d678 LDR	X17, [X20, #16]

0x43d67c MSUB	W12, W11, W10, W23

0x43d680 ADD	W13, W11, W22

0x43d684 SBFM	X27, X13, #0, #31

0x43d688 LDR	X15, [X20, #48]

0x43d68c STR	X14, [SP, #280]

0x43d690 LDR	X18, [X20, #56]

0x43d694 DUP	V29.2D, V30.D[0]

0x43d698 STP	X25, X28, [SP, #312]

0x43d69c LDR	X30, [X20, #32]

0x43d6a0 STR	X17, [SP, #296]

0x43d6a4 LDR	X0, [X20, #72]

0x43d6a8 STR	X15, [SP, #344]

0x43d6ac LDR	W16, [SP, #268]

0x43d6b0 STR	X18, [SP, #352]

0x43d6b4 STP	X30, X0, [SP, #328]

0x43d6b8 ADD	W26, W12, W16

0x43d6bc LDR	X22, [X20, #40]

0x43d6c0 SUB	W14, W19, W26

0x43d6c4 LDR	X3, [X20, #80]

0x43d6c8 LDR	X20, [X20, #88]

0x43d6cc STR	X22, [SP, #360]

0x43d6d0 STR	X3, [SP, #288]

0x43d6d4 STR	X20, [SP, #304]

0x43d6d8 HINT	#0

0x43d6dc HINT	#0

(293) 0x43d6e0 CMP	W7, W14

(293) 0x43d6e4 CSEL	W9, W7, W14, #9

(293) 0x43d6e8 ADD	W4, W23, W9

(293) 0x43d6ec STR	W4, [SP, #212]

(293) 0x43d6f0 CMP	W23, W4

(293) 0x43d6f4 B.CS	43dac4

(293) 0x43d6f8 LDP	X23, X5, [SP, #280]

(293) 0x43d6fc LDP	X21, X6, [SP, #296]

(293) 0x43d700 LDP	X7, X11, [SP, #312]

(293) 0x43d704 LDP	X30, X22, [SP, #328]

(293) 0x43d708 LDR	X1, [X5]

(293) 0x43d70c LDR	X2, [X21]

(293) 0x43d710 LDR	X19, [X6]

(293) 0x43d714 MUL	X24, X1, X27

(293) 0x43d718 LDR	X13, [X7]

(293) 0x43d71c MUL	X10, X2, X27

(293) 0x43d720 ADD	X16, X1, X24

(293) 0x43d724 LDR	X8, [X23]

(293) 0x43d728 MUL	X25, X19, X27

(293) 0x43d72c ADD	X17, X2, X10

(293) 0x43d730 LDR	X15, [X11]

(293) 0x43d734 MUL	X14, X27, X13

(293) 0x43d738 LDR	X13, [SP, #344]

(293) 0x43d73c ADD	X19, X19, X25

(293) 0x43d740 MUL	X18, X27, X8

(293) 0x43d744 LDR	X0, [X30]

(293) 0x43d748 STR	X14, [SP, #200]

(293) 0x43d74c MUL	X28, X27, X15

(293) 0x43d750 LDR	X12, [SP, #352]

(293) 0x43d754 STP	X19, X17, [SP, #224]

(293) 0x43d758 MUL	X3, X27, X0

(293) 0x43d75c LDR	X14, [SP, #360]

(293) 0x43d760 STP	X10, X16, [SP, #240]

(293) 0x43d764 LDR	X20, [X22]

(293) 0x43d768 STR	X3, [SP, #168]

(293) 0x43d76c LDR	X2, [X13]

(293) 0x43d770 STR	X28, [SP, #184]

(293) 0x43d774 LDR	X1, [X12]

(293) 0x43d778 MUL	X4, X27, X20

(293) 0x43d77c STR	X18, [SP, #256]

(293) 0x43d780 LDR	X15, [X14]

(293) 0x43d784 MUL	X8, X27, X2

(293) 0x43d788 LDR	X3, [X22, #16]

(293) 0x43d78c STR	X4, [SP, #152]

(293) 0x43d790 MUL	X20, X27, X1

(293) 0x43d794 LDR	X28, [X23, #16]

(293) 0x43d798 STR	X8, [SP, #112]

(293) 0x43d79c MUL	X0, X27, X15

(293) 0x43d7a0 LDR	X4, [X30, #16]

(293) 0x43d7a4 STR	X3, [SP, #104]

(293) 0x43d7a8 LDR	X22, [X5, #16]

(293) 0x43d7ac STR	X0, [SP, #216]

(293) 0x43d7b0 LDR	X5, [X7, #16]

(293) 0x43d7b4 STR	X4, [SP, #160]

(293) 0x43d7b8 LDR	X30, [X21, #16]

(293) 0x43d7bc LDR	X23, [X6, #16]

(293) 0x43d7c0 STR	X5, [SP, #192]

(293) 0x43d7c4 LDR	X21, [X11, #16]

(293) 0x43d7c8 LDR	X6, [X13, #16]

(293) 0x43d7cc LDR	X7, [X12, #16]

(293) 0x43d7d0 STR	X21, [SP, #176]

(293) 0x43d7d4 LDR	X11, [X14, #16]

(293) 0x43d7d8 STP	X6, X20, [SP, #120]

(293) 0x43d7dc STP	X7, X11, [SP, #136]

(293) 0x43d7e0 CMP	W9, #1

(293) 0x43d7e4 B.EQ	43d980

(293) 0x43d7e8 SBFM	X1, X26, #0, #31

(293) 0x43d7ec UBFM	W12, W9, #1, #31

(293) 0x43d7f0 ADD	X2, X16, X1

(293) 0x43d7f4 ADD	X18, X18, X1

(293) 0x43d7f8 LDR	X11, [SP, #152]

(293) 0x43d7fc ADD	X3, X28, X18,LSL #3

(293) 0x43d800 ADD	X16, X10, X1

(293) 0x43d804 ADD	X13, X24, X1

(293) 0x43d808 ADD	X10, X22, X2,LSL #3

(293) 0x43d80c ADD	X4, X19, X1

(293) 0x43d810 ADD	X14, X25, X1

(293) 0x43d814 ADD	X20, X22, X13,LSL #3

(293) 0x43d818 LDR	X13, [SP, #200]

(293) 0x43d81c ORR	X8, XZR, X3

(293) 0x43d820 ADD	X21, X3, #8

(293) 0x43d824 ORR	X6, XZR, X10

(293) 0x43d828 ADD	X5, X23, X14,LSL #3

(293) 0x43d82c ADD	X19, X10, #8

(293) 0x43d830 LDR	X10, [SP, #112]

(293) 0x43d834 UBFM	X3, X12, #60, #59

(293) 0x43d838 ADD	X18, X5, #8

(293) 0x43d83c ADD	X5, X23, X14,LSL #3

(293) 0x43d840 ADD	X15, X17, X1

(293) 0x43d844 LDR	X12, [SP, #184]

(293) 0x43d848 ADD	X17, X23, X4,LSL #3

(293) 0x43d84c ORR	X7, XZR, X20

(293) 0x43d850 ADD	X14, X13, X1

(293) 0x43d854 ADD	X4, X23, X4,LSL #3

(293) 0x43d858 ADD	X20, X20, #8

(293) 0x43d85c LDR	X2, [SP, #168]

(293) 0x43d860 ADD	X16, X30, X16,LSL #3

(293) 0x43d864 ADD	X17, X17, #8

(293) 0x43d868 ADD	X15, X30, X15,LSL #3

(293) 0x43d86c ADD	X13, X12, X1

(293) 0x43d870 ADD	X12, X11, X1

(293) 0x43d874 ADD	X11, X10, X1

(293) 0x43d878 LDR	X10, [SP, #128]

(293) 0x43d87c ADD	X2, X2, X1

(293) 0x43d880 ADD	X10, X10, X1

(293) 0x43d884 ADD	X1, X0, X1

(293) 0x43d888 LDR	X0, [SP, #192]

(293) 0x43d88c ADD	X14, X0, X14,LSL #3

(293) 0x43d890 LDR	X0, [SP, #176]

(293) 0x43d894 ADD	X13, X0, X13,LSL #3

(293) 0x43d898 LDR	X0, [SP, #160]

(293) 0x43d89c ADD	X2, X0, X2,LSL #3

(293) 0x43d8a0 LDR	X0, [SP, #104]

(293) 0x43d8a4 ADD	X12, X0, X12,LSL #3

(293) 0x43d8a8 LDR	X0, [SP, #120]

(293) 0x43d8ac ADD	X11, X0, X11,LSL #3

(293) 0x43d8b0 LDR	X0, [SP, #136]

(293) 0x43d8b4 ADD	X10, X0, X10,LSL #3

(293) 0x43d8b8 LDR	X0, [SP, #144]

(293) 0x43d8bc ADD	X1, X0, X1,LSL #3

(293) 0x43d8c0 MOVZ	X0, #0

  (294) 0x43d8c4 LDR	Q17, [X18, X0]

  (294) 0x43d8c8 LDR	Q16, [X5, X0]

  (294) 0x43d8cc LDR	Q24, [X16, X0]

  (294) 0x43d8d0 LDR	Q4, [X17, X0]

  (294) 0x43d8d4 LDR	Q3, [X4, X0]

  (294) 0x43d8d8 FADD	V0.2D, V17.2D, V16.2D

  (294) 0x43d8dc LDR	Q26, [X15, X0]

  (294) 0x43d8e0 FADD	V1.2D, V24.2D, V24.2D

  (294) 0x43d8e4 LDR	Q28, [X6, X0]

  (294) 0x43d8e8 LDR	Q27, [X7, X0]

  (294) 0x43d8ec FADD	V2.2D, V4.2D, V3.2D

  (294) 0x43d8f0 LDR	Q25, [X8, X0]

  (294) 0x43d8f4 FADD	V18.2D, V26.2D, V26.2D

  (294) 0x43d8f8 FMUL	V19.2D, V0.2D, V1.2D

  (294) 0x43d8fc LDR	Q7, [X21, X0]

  (294) 0x43d900 LDR	Q6, [X19, X0]

  (294) 0x43d904 FADD	V20.2D, V28.2D, V27.2D

  (294) 0x43d908 LDR	Q5, [X20, X0]

  (294) 0x43d90c FADD	V22.2D, V25.2D, V25.2D

  (294) 0x43d910 FMUL	V23.2D, V2.2D, V18.2D

  (294) 0x43d914 FADD	V31.2D, V7.2D, V7.2D

  (294) 0x43d918 LDR	Q21, [X12, X0]

  (294) 0x43d91c LDR	Q17, [X13, X0]

  (294) 0x43d920 FADD	V16.2D, V6.2D, V5.2D

  (294) 0x43d924 LDR	Q24, [X2, X0]

  (294) 0x43d928 FMLA	V19.2D, V22.2D, V20.2D

  (294) 0x43d92c LDR	Q4, [X14, X0]

  (294) 0x43d930 FADD	V3.2D, V21.2D, V17.2D

  (294) 0x43d934 LDR	Q26, [X11, X0]

  (294) 0x43d938 FMLA	V23.2D, V31.2D, V16.2D

  (294) 0x43d93c FDIV	V0.2D, V3.2D, V24.2D

  (294) 0x43d940 FDIV	V1.2D, V0.2D, V4.2D

  (294) 0x43d944 FSUB	V28.2D, V23.2D, V19.2D

  (294) 0x43d948 FMUL	V27.2D, V28.2D, V29.2D

  (294) 0x43d94c FMLS	V26.2D, V1.2D, V27.2D

  (294) 0x43d950 FADD	V2.2D, V4.2D, V27.2D

  (294) 0x43d954 STR	Q26, [X10, X0]

  (294) 0x43d958 FDIV	V25.2D, V4.2D, V2.2D

  (294) 0x43d95c LDR	Q18, [X2, X0]

  (294) 0x43d960 FMUL	V19.2D, V18.2D, V25.2D

  (294) 0x43d964 STR	Q19, [X1, X0]

  (294) 0x43d968 ADD	X0, X0, #16

  (294) 0x43d96c CMP	X0, X3

  (294) 0x43d970 B.NE	43d8c4

(293) 0x43d974 TBZ	W9, #0, 43dac0

(293) 0x43d978 AND	W9, W9, #0xfffffffe

(293) 0x43d97c ADD	W26, W26, W9

(293) 0x43d980 LDR	X18, [SP, #240]

(293) 0x43d984 ADD	W8, W26, #1

(293) 0x43d988 SBFM	X21, X26, #0, #31

(293) 0x43d98c SBFM	X20, X8, #0, #31

(293) 0x43d990 LDP	X19, X6, [SP, #216]

(293) 0x43d994 ADD	X7, X24, X21

(293) 0x43d998 ADD	X12, X25, X20

(293) 0x43d99c ADD	X25, X25, X21

(293) 0x43d9a0 ADD	X24, X24, X20

(293) 0x43d9a4 ADD	X5, X18, X21

(293) 0x43d9a8 LDR	X13, [SP, #232]

(293) 0x43d9ac ADD	X3, X6, X20

(293) 0x43d9b0 ADD	X4, X6, X21

(293) 0x43d9b4 LDR	D7, [X30, X5,LSL #3]

(293) 0x43d9b8 ADD	X16, X19, X21

(293) 0x43d9bc LDR	D31, [X23, X12,LSL #3]

(293) 0x43d9c0 ADD	X2, X13, X21

(293) 0x43d9c4 LDR	D17, [X23, X25,LSL #3]

(293) 0x43d9c8 LDR	X1, [SP, #248]

(293) 0x43d9cc FADD	D22, D7, D7

(293) 0x43d9d0 LDR	X17, [SP, #256]

(293) 0x43d9d4 LDR	X14, [SP, #152]

(293) 0x43d9d8 FADD	D16, D31, D17

(293) 0x43d9dc ADD	X26, X1, X21

(293) 0x43d9e0 ADD	X8, X1, X20

(293) 0x43d9e4 LDR	X10, [SP, #184]

(293) 0x43d9e8 ADD	X0, X17, X20

(293) 0x43d9ec ADD	X20, X17, X21

(293) 0x43d9f0 LDR	D23, [X23, X4,LSL #3]

(293) 0x43d9f4 ADD	X11, X14, X21

(293) 0x43d9f8 LDR	D5, [X23, X3,LSL #3]

(293) 0x43d9fc FMUL	D0, D16, D22

(293) 0x43da00 ADD	X9, X10, X21

(293) 0x43da04 LDR	D24, [X30, X2,LSL #3]

(293) 0x43da08 LDR	D20, [X22, X7,LSL #3]

(293) 0x43da0c LDR	X30, [SP, #104]

(293) 0x43da10 FADD	D21, D5, D23

(293) 0x43da14 LDR	X7, [SP, #176]

(293) 0x43da18 FADD	D4, D24, D24

(293) 0x43da1c LDR	D6, [X22, X24,LSL #3]

(293) 0x43da20 LDR	D1, [X22, X26,LSL #3]

(293) 0x43da24 LDR	D26, [X28, X20,LSL #3]

(293) 0x43da28 FMUL	D3, D21, D4

(293) 0x43da2c LDR	D28, [X28, X0,LSL #3]

(293) 0x43da30 LDR	D2, [X22, X8,LSL #3]

(293) 0x43da34 FADD	D25, D1, D20

(293) 0x43da38 LDP	X28, X22, [SP, #160]

(293) 0x43da3c FADD	D18, D26, D26

(293) 0x43da40 FADD	D19, D28, D28

(293) 0x43da44 LDR	D27, [X30, X11,LSL #3]

(293) 0x43da48 ADD	X19, X22, X21

(293) 0x43da4c FADD	D20, D2, D6

(293) 0x43da50 LDR	D22, [X7, X9,LSL #3]

(293) 0x43da54 UBFM	X6, X19, #61, #60

(293) 0x43da58 FMADD	D6, D18, D25, D0

(293) 0x43da5c LDR	D31, [X28, X6]

(293) 0x43da60 LDR	X18, [SP, #200]

(293) 0x43da64 FMADD	D7, D19, D20, D3

(293) 0x43da68 FADD	D21, D27, D22

(293) 0x43da6c LDR	X24, [SP, #192]

(293) 0x43da70 LDR	X15, [SP, #128]

(293) 0x43da74 ADD	X17, X18, X21

(293) 0x43da78 LDR	D16, [X24, X17,LSL #3]

(293) 0x43da7c FDIV	D17, D21, D31

(293) 0x43da80 LDP	X5, X3, [SP, #112]

(293) 0x43da84 ADD	X23, X15, X21

(293) 0x43da88 FSUB	D5, D7, S6

(293) 0x43da8c LDR	X4, [SP, #136]

(293) 0x43da90 ADD	X21, X5, X21

(293) 0x43da94 LDR	X15, [SP, #144]

(293) 0x43da98 LDR	D0, [X3, X21,LSL #3]

(293) 0x43da9c FMUL	D23, D5, D30

(293) 0x43daa0 FADD	D24, D16, D23

(293) 0x43daa4 FDIV	D4, D17, D16

(293) 0x43daa8 FDIV	D3, D16, D24

(293) 0x43daac FMSUB	D27, D4, D23, D0

(293) 0x43dab0 STR	D27, [X4, X23,LSL #3]

(293) 0x43dab4 LDR	D1, [X28, X6]

(293) 0x43dab8 FMUL	D26, D1, D3

(293) 0x43dabc STR	D26, [X15, X16,LSL #3]

(293) 0x43dac0 LDR	W23, [SP, #212]

(293) 0x43dac4 ADD	X27, X27, #1

(293) 0x43dac8 LDR	W16, [SP, #264]

(293) 0x43dacc CMP	W16, W27

(293) 0x43dad0 B.LE	43dafc

(293) 0x43dad4 LDR	W13, [SP, #276]

(293) 0x43dad8 LDR	W26, [SP, #268]

(293) 0x43dadc LDR	W14, [SP, #272]

(293) 0x43dae0 SUB	W7, W13, W23

(293) 0x43dae4 B	43d6e0

0x43dae8 LDP	X23, X24, [SP, #48]

0x43daec LDP	X19, X20, [SP, #16]

0x43daf0 LDP	X21, X22, [SP, #32]

0x43daf4 LDP	X29, X30, [SP], #368

0x43daf8 RET

0x43dafc LDP	X23, X24, [SP, #48]

0x43db00 LDP	X25, X26, [SP, #64]

0x43db04 LDP	X27, X28, [SP, #80]

0x43db08 LDP	X19, X20, [SP, #16]

0x43db0c LDP	X21, X22, [SP, #32]

0x43db10 LDP	X29, X30, [SP], #368

0x43db14 RET

0x43db18 ADD	W7, W7, #1

0x43db1c MOVZ	W8, #0

0x43db20 B	43d63c

Coverage (%)	Name	Source Location	Module
►98.42+	omp_fulfill_event		libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.58+	GOMP_parallel		libgomp.so.1.0.0
○	PdV(global_variables&, bool)	PdV.cpp:99	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:64	exec
○	main	clover_leaf.cpp:209	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	clover_leaf.cpp:51	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.00 to 12.50 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 27% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 25.00 to 15.62 cycles (1.60x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 15.50 cycles (1.61x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 12 bytes. The binary function is storing 12 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	87
nb uops	85
loop length	348
used w registers	23
used x registers	20
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	2
used z registers	0
nb stack references	31

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	7.50	7.50	7.50	7.50	0.75	0.75	0.75	0.75	15.50	15.17	15.33	9.50	9.50
cycles	4.50	4.50	7.50	7.50	7.50	7.50	0.75	0.75	0.75	0.75	15.50	15.17	15.33	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	10.63
Dispatch	15.50
DIV/SQRT	10.00-25.00
Overall L1	15.50-25.00

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	10%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	27%
load	32%
store	32%
mul	12%
add-sub	13%
fma	12%
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	27%
load	32%
store	32%
mul	18%
add-sub	13%
fma	12%
div/sqrt	12%
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43d5c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W22, W1, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X20, #100]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W4, [SP, #268]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W22, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 43daec <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W23, W3, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 43dae8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W24, W23, W5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W5, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W8, W7, W21, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 43db18 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x558>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W23, W7, W6, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W7, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W9, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W23, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 43dae8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
FMOV D30, #0.1250000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UDIV W11, W23, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X25, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X28, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMUL D30, D31, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR X17, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB W12, W11, W10, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W13, W11, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X27, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDR X15, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
DUP V29.2D, V30.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP X25, X28, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W16, [SP, #268]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X30, X0, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W26, W12, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X22, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W14, W19, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X3, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X20, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X22, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 43d63c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 15.50 cycles (1.61x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 12 bytes. The binary function is storing 12 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	87
nb uops	85
loop length	348
used w registers	23
used x registers	20
used b registers	0
used h registers	0
used s registers	1
used d registers	2
used q registers	0
used v registers	2
used z registers	0
nb stack references	31

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.63 cycles
front end	10.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	7.50	7.50	7.50	7.50	0.75	0.75	0.75	0.75	15.50	15.17	15.33	9.50	9.50
cycles	4.50	4.50	7.50	7.50	7.50	7.50	0.75	0.75	0.75	0.75	15.50	15.17	15.33	9.50	9.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	10.63
Dispatch	15.50
DIV/SQRT	10.00-25.00
Overall L1	15.50-25.00

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
other	10%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	10%

Vector efficiency ratios

INT

all	27%
load	32%
store	32%
mul	12%
add-sub	13%
fma	12%
other	25%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	27%
load	32%
store	32%
mul	18%
add-sub	13%
fma	12%
div/sqrt	12%
other	26%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.48 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43d5c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #656]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W22, W1, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W0, [X0, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W2, [X20, #100]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
ADD W3, W1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W4, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W3, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
STR W4, [SP, #268]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W22, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 43daec <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W23, W3, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 43dae8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W24, W23, W5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W5, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W8, W7, W21, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 43db18 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x558>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W23, W7, W6, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W7, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W9, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W23, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 43dae8 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x528>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
FMOV D30, #0.1250000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
UDIV W11, W23, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
LDR D31, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (25.0%)
LDR X25, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X28, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X14, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMUL D30, D31, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
LDR X17, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MSUB W12, W11, W10, W23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W13, W11, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SBFM X27, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
LDR X15, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X14, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X18, [X20, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
DUP V29.2D, V30.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (50.0%)
STP X25, X28, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X30, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X17, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X0, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X15, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR W16, [SP, #268]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STR X18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP X30, X0, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD W26, W12, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X22, [X20, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
SUB W14, W19, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDR X3, [X20, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X20, [X20, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X22, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X3, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR X20, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
HINT #0																			N/A
HINT #0																			N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #368	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 43d63c <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	6.65	8.94
▼Loop 293 - PdV.cpp:50-63 - exec–	0.02	0.03
○Loop 294 - PdV.cpp:51-63 - exec	6.64	8.67

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Code clean check

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Vectorization

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Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

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General properties

Front-end

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Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code