OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:117-125 [...]	Coverage (incl. loops): 3.75% \| (excl. loops): 0.00%

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 117 - 125

--------------------------------------------------------------------------------

117: #pragma omp parallel for simd collapse(2)

118:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

119:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

120:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

121:         double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0);

122:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s;

123:         double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0);

124:         density1(i, j) = post_mass_s / advec_vol_s;

125:         energy1(i, j) = post_ener_s;

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42c608 STP	X29, X30, [SP, #800]!

0x42c60c ADD	X29, SP, #0

0x42c610 STP	X19, X20, [SP, #16]

0x42c614 ORR	X20, XZR, X0

0x42c618 STP	X21, X22, [SP, #32]

0x42c61c LDP	W22, W2, [X0, #56]

0x42c620 LDR	W1, [X0, #48]

0x42c624 LDR	W0, [X0, #52]

0x42c628 ADD	W3, W2, #2

0x42c62c ADD	W22, W22, #1

0x42c630 ADD	W4, W1, #1

0x42c634 STP	W3, W4, [SP, #168]

0x42c638 CMP	W22, W3

0x42c63c B.GE	42c9c4

0x42c640 ADD	W19, W0, #2

0x42c644 STP	X23, X24, [SP, #48]

0x42c648 SUB	W23, W3, W22

0x42c64c CMP	W4, W19

0x42c650 B.GE	42c9c0

0x42c654 SUB	W5, W19, W4

0x42c658 MUL	W24, W23, W5

0x42c65c STR	W5, [SP, #216]

0x42c660 BL	410210

0x42c664 ORR	W21, WZR, W0

0x42c668 BL	410240

0x42c66c UDIV	W7, W24, W21

0x42c670 ORR	W6, WZR, W0

0x42c674 MSUB	W8, W7, W21, W24

0x42c678 CMP	W0, W8

0x42c67c B.CC	42c9f0

0x42c680 MADD	W18, W7, W6, W8

0x42c684 ADD	W9, W7, W18

0x42c688 STR	W9, [SP, #220]

0x42c68c CMP	W18, W9

0x42c690 B.CS	42c9c0

0x42c694 LDR	W10, [SP, #216]

0x42c698 STP	X25, X26, [SP, #64]

0x42c69c LDR	W14, [SP, #172]

0x42c6a0 UDIV	W11, W18, W10

0x42c6a4 STP	X27, X28, [SP, #80]

0x42c6a8 LDP	X21, X15, [X20]

0x42c6ac LDP	X17, X24, [X20, #16]

0x42c6b0 ORR	X25, XZR, X15

0x42c6b4 MSUB	W12, W11, W10, W18

0x42c6b8 ADD	W13, W11, W22

0x42c6bc LDP	X22, X28, [X20, #32]

0x42c6c0 SBFM	X27, X13, #0, #31

0x42c6c4 ORR	X23, XZR, X17

0x42c6c8 ADD	W26, W12, W14

0x42c6cc SUB	W13, W19, W26

(164) 0x42c6d0 CMP	W7, W13

(164) 0x42c6d4 CSEL	W4, W7, W13, #9

(164) 0x42c6d8 ADD	W16, W18, W4

(164) 0x42c6dc STR	W16, [SP, #116]

(164) 0x42c6e0 CMP	W18, W16

(164) 0x42c6e4 B.CS	42c99c

(164) 0x42c6e8 LDR	X18, [X21]

(164) 0x42c6ec LDR	X30, [X22]

(164) 0x42c6f0 LDR	X1, [X23]

(164) 0x42c6f4 MUL	X20, X27, X18

(164) 0x42c6f8 LDR	X0, [X25]

(164) 0x42c6fc MUL	X9, X27, X30

(164) 0x42c700 LDR	X3, [X28]

(164) 0x42c704 MUL	X5, X27, X1

(164) 0x42c708 LDR	X8, [X22, #16]

(164) 0x42c70c MUL	X11, X27, X0

(164) 0x42c710 LDR	X2, [X24]

(164) 0x42c714 MUL	X6, X27, X3

(164) 0x42c718 LDR	X19, [X21, #16]

(164) 0x42c71c LDR	X14, [X23, #16]

(164) 0x42c720 MUL	X30, X27, X2

(164) 0x42c724 LDR	X12, [X24, #16]

(164) 0x42c728 LDR	X18, [X25, #16]

(164) 0x42c72c LDR	X13, [X28, #16]

(164) 0x42c730 STP	X8, X6, [SP, #120]

(164) 0x42c734 STP	X11, X5, [SP, #136]

(164) 0x42c738 STP	X9, X20, [SP, #152]

(164) 0x42c73c CMP	W4, #1

(164) 0x42c740 B.EQ	42c900

(164) 0x42c744 SBFM	X2, X26, #0, #31

(164) 0x42c748 UBFM	W17, W4, #1, #31

(164) 0x42c74c ADD	X7, X5, X2

(164) 0x42c750 ADD	X16, X6, X2

(164) 0x42c754 ADD	X5, X30, X2

(164) 0x42c758 UBFM	X1, X7, #61, #60

(164) 0x42c75c ADD	X6, X13, X16,LSL #3

(164) 0x42c760 UBFM	X10, X16, #61, #60

(164) 0x42c764 UBFM	X15, X5, #61, #60

(164) 0x42c768 ADD	X7, X14, X7,LSL #3

(164) 0x42c76c ADD	X16, X20, X2

(164) 0x42c770 ADD	X20, X9, X2

(164) 0x42c774 STR	X1, [SP, #192]

(164) 0x42c778 ADD	X9, X1, #8

(164) 0x42c77c ADD	X1, X10, #8

(164) 0x42c780 STP	X15, X10, [SP, #176]

(164) 0x42c784 ADD	X10, X15, #8

(164) 0x42c788 ADD	X3, X11, X2

(164) 0x42c78c ADD	X11, X8, X20,LSL #3

(164) 0x42c790 ADD	X8, X12, X10

(164) 0x42c794 ADD	X2, X19, X16,LSL #3

(164) 0x42c798 MOVZ	X0, #0

(164) 0x42c79c STR	X1, [SP, #104]

(164) 0x42c7a0 ADD	X5, X12, X5,LSL #3

(164) 0x42c7a4 UBFM	X16, X16, #61, #60

(164) 0x42c7a8 STP	X9, X10, [SP, #200]

(164) 0x42c7ac ADD	X10, X14, X9

(164) 0x42c7b0 ADD	X1, X18, X3,LSL #3

(164) 0x42c7b4 UBFM	X20, X20, #61, #60

(164) 0x42c7b8 UBFM	X15, X17, #60, #59

(164) 0x42c7bc UBFM	X3, X3, #61, #60

(164) 0x42c7c0 LDR	X9, [SP, #104]

(164) 0x42c7c4 ADD	X9, X13, X9

(164) 0x42c7c8 TBZ	W17, #0, 42c844

(164) 0x42c7cc LDR	X0, [SP, #120]

(164) 0x42c7d0 LDR	X17, [SP, #184]

(164) 0x42c7d4 LDR	Q30, [X19, X16]

(164) 0x42c7d8 LDR	Q31, [X0, X20]

(164) 0x42c7dc MOVZ	X0, #16

(164) 0x42c7e0 LDR	X20, [SP, #104]

(164) 0x42c7e4 LDR	Q0, [X13, X17]

(164) 0x42c7e8 LDR	X17, [SP, #176]

(164) 0x42c7ec FMUL	V3.2D, V30.2D, V31.2D

(164) 0x42c7f0 LDR	Q29, [X13, X20]

(164) 0x42c7f4 LDR	X20, [SP, #200]

(164) 0x42c7f8 LDR	Q27, [X12, X17]

(164) 0x42c7fc LDR	X17, [SP, #208]

(164) 0x42c800 FSUB	V4.2D, V0.2D, V29.2D

(164) 0x42c804 LDR	Q2, [X14, X20]

(164) 0x42c808 LDR	X20, [SP, #192]

(164) 0x42c80c FADD	V5.2D, V27.2D, V31.2D

(164) 0x42c810 LDR	Q1, [X18, X3]

(164) 0x42c814 LDR	Q26, [X12, X17]

(164) 0x42c818 FSUB	V6.2D, V3.2D, V2.2D

(164) 0x42c81c LDR	Q28, [X14, X20]

(164) 0x42c820 FMLA	V4.2D, V1.2D, V3.2D

(164) 0x42c824 FSUB	V7.2D, V5.2D, V26.2D

(164) 0x42c828 FADD	V16.2D, V6.2D, V28.2D

(164) 0x42c82c FDIV	V17.2D, V16.2D, V7.2D

(164) 0x42c830 FDIV	V18.2D, V4.2D, V16.2D

(164) 0x42c834 STR	Q17, [X19, X16]

(164) 0x42c838 STR	Q18, [X18, X3]

(164) 0x42c83c CMP	X0, X15

(164) 0x42c840 B.EQ	42c8f4

  (165) 0x42c844 LDR	Q19, [X11, X0]

  (165) 0x42c848 ADD	X16, X0, #16

  (165) 0x42c84c LDR	Q20, [X2, X0]

  (165) 0x42c850 LDR	Q21, [X6, X0]

  (165) 0x42c854 LDR	Q22, [X9, X0]

  (165) 0x42c858 LDR	Q23, [X5, X0]

  (165) 0x42c85c FMUL	V24.2D, V20.2D, V19.2D

  (165) 0x42c860 LDR	Q25, [X10, X0]

  (165) 0x42c864 LDR	Q30, [X1, X0]

  (165) 0x42c868 FSUB	V1.2D, V21.2D, V22.2D

  (165) 0x42c86c LDR	Q31, [X8, X0]

  (165) 0x42c870 FADD	V0.2D, V23.2D, V19.2D

  (165) 0x42c874 LDR	Q3, [X7, X0]

  (165) 0x42c878 FSUB	V29.2D, V24.2D, V25.2D

  (165) 0x42c87c FMLA	V1.2D, V30.2D, V24.2D

  (165) 0x42c880 FSUB	V4.2D, V0.2D, V31.2D

  (165) 0x42c884 FADD	V27.2D, V29.2D, V3.2D

  (165) 0x42c888 FDIV	V5.2D, V27.2D, V4.2D

  (165) 0x42c88c FDIV	V2.2D, V1.2D, V27.2D

  (165) 0x42c890 STR	Q5, [X2, X0]

  (165) 0x42c894 STR	Q2, [X1, X0]

  (165) 0x42c898 ADD	X0, X0, #32

  (165) 0x42c89c LDR	Q6, [X11, X16]

  (165) 0x42c8a0 LDR	Q26, [X2, X16]

  (165) 0x42c8a4 LDR	Q7, [X6, X16]

  (165) 0x42c8a8 LDR	Q28, [X9, X16]

  (165) 0x42c8ac LDR	Q16, [X5, X16]

  (165) 0x42c8b0 FMUL	V17.2D, V26.2D, V6.2D

  (165) 0x42c8b4 LDR	Q18, [X10, X16]

  (165) 0x42c8b8 LDR	Q19, [X1, X16]

  (165) 0x42c8bc FSUB	V23.2D, V7.2D, V28.2D

  (165) 0x42c8c0 LDR	Q20, [X8, X16]

  (165) 0x42c8c4 FADD	V21.2D, V16.2D, V6.2D

  (165) 0x42c8c8 LDR	Q22, [X7, X16]

  (165) 0x42c8cc FSUB	V24.2D, V17.2D, V18.2D

  (165) 0x42c8d0 FMLA	V23.2D, V19.2D, V17.2D

  (165) 0x42c8d4 FSUB	V25.2D, V21.2D, V20.2D

  (165) 0x42c8d8 FADD	V30.2D, V24.2D, V22.2D

  (165) 0x42c8dc FDIV	V1.2D, V30.2D, V25.2D

  (165) 0x42c8e0 FDIV	V31.2D, V23.2D, V30.2D

  (165) 0x42c8e4 STR	Q1, [X2, X16]

  (165) 0x42c8e8 STR	Q31, [X1, X16]

  (165) 0x42c8ec CMP	X0, X15

  (165) 0x42c8f0 B.NE	42c844

(164) 0x42c8f4 TBZ	W4, #0, 42c998

(164) 0x42c8f8 AND	W4, W4, #0xfffffffe

(164) 0x42c8fc ADD	W26, W26, W4

(164) 0x42c900 LDR	X2, [SP, #160]

(164) 0x42c904 ADD	W7, W26, #1

(164) 0x42c908 SBFM	X11, X26, #0, #31

(164) 0x42c90c SBFM	X8, X7, #0, #31

(164) 0x42c910 LDP	X5, X10, [SP, #120]

(164) 0x42c914 ADD	X6, X30, X11

(164) 0x42c918 ADD	X30, X30, X8

(164) 0x42c91c LDR	X3, [SP, #152]

(164) 0x42c920 ADD	X15, X2, X11

(164) 0x42c924 UBFM	X9, X15, #61, #60

(164) 0x42c928 ADD	X1, X10, X8

(164) 0x42c92c LDR	D0, [X12, X6,LSL #3]

(164) 0x42c930 LDR	D4, [X12, X30,LSL #3]

(164) 0x42c934 LDP	X12, X17, [SP, #136]

(164) 0x42c938 ADD	X0, X3, X11

(164) 0x42c93c LDR	D3, [X19, X9]

(164) 0x42c940 ADD	X20, X12, X11

(164) 0x42c944 ADD	X4, X17, X11

(164) 0x42c948 LDR	D29, [X5, X0,LSL #3]

(164) 0x42c94c UBFM	X16, X20, #61, #60

(164) 0x42c950 ADD	X26, X17, X8

(164) 0x42c954 ADD	X11, X10, X11

(164) 0x42c958 LDR	D27, [X13, X1,LSL #3]

(164) 0x42c95c LDR	D26, [X18, X16]

(164) 0x42c960 FMUL	D5, D29, D3

(164) 0x42c964 LDR	D7, [X14, X4,LSL #3]

(164) 0x42c968 FADD	D2, D29, D0

(164) 0x42c96c LDR	D28, [X14, X26,LSL #3]

(164) 0x42c970 LDR	D18, [X13, X11,LSL #3]

(164) 0x42c974 FNMSUB	D16, D26, D5, D27

(164) 0x42c978 FADD	D17, D5, D7

(164) 0x42c97c FSUB	D6, D2, S4

(164) 0x42c980 FSUB	D19, D17, S28

(164) 0x42c984 FADD	D23, D16, D18

(164) 0x42c988 FDIV	D20, D19, D6

(164) 0x42c98c FDIV	D21, D23, D19

(164) 0x42c990 STR	D20, [X19, X9]

(164) 0x42c994 STR	D21, [X18, X16]

(164) 0x42c998 LDR	W18, [SP, #116]

(164) 0x42c99c ADD	X27, X27, #1

(164) 0x42c9a0 LDR	W19, [SP, #168]

(164) 0x42c9a4 CMP	W19, W27

(164) 0x42c9a8 B.LE	42c9d4

(164) 0x42c9ac LDR	W14, [SP, #220]

(164) 0x42c9b0 LDR	W26, [SP, #172]

(164) 0x42c9b4 LDR	W13, [SP, #216]

(164) 0x42c9b8 SUB	W7, W14, W18

(164) 0x42c9bc B	42c6d0

0x42c9c0 LDP	X23, X24, [SP, #48]

0x42c9c4 LDP	X19, X20, [SP, #16]

0x42c9c8 LDP	X21, X22, [SP, #32]

0x42c9cc LDP	X29, X30, [SP], #224

0x42c9d0 RET

0x42c9d4 LDP	X23, X24, [SP, #48]

0x42c9d8 LDP	X25, X26, [SP, #64]

0x42c9dc LDP	X27, X28, [SP, #80]

0x42c9e0 LDP	X19, X20, [SP, #16]

0x42c9e4 LDP	X21, X22, [SP, #32]

0x42c9e8 LDP	X29, X30, [SP], #224

0x42c9ec RET

0x42c9f0 ADD	W7, W7, #1

0x42c9f4 MOVZ	W8, #0

0x42c9f8 B	42c680

0x42c9fc HINT	#0

Coverage (%)	Name	Module
►98.43+	omp_fulfill_event	libgomp.so.1.0.0
○	start_thread	libc.so.6
○	thread_start	libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 28% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 25.00 to 15.62 cycles (1.60x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 9.17 cycles (2.73x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	66
nb uops	65
loop length	264
used w registers	23
used x registers	17
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	9.17	8.83	9.00	4.50	4.50
cycles	4.50	4.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	9.17	8.83	9.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	8.13
Dispatch	9.17
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	28%
load	40%
store	38%
mul	12%
add-sub	13%
fma	12%
div/sqrt	12%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42c608

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #800]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W22, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W4, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP W3, W4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42c9c4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W23, W3, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42c9c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W24, W23, W5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W5, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W8, W7, W21, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 42c9f0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W18, W7, W6, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W7, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W9, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W18, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42c9c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W14, [SP, #172]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
UDIV W11, W18, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X15, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X17, X24, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X25, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MSUB W12, W11, W10, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W13, W11, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X22, X28, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SBFM X27, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ORR X23, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W26, W12, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W13, W19, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #224	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #224	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 42c680 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.00 to 9.17 cycles (2.73x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
- /home/eoseret/qaas/qaas_runs/178-219-7589/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 12 bytes. The binary function is storing 6 bytes.

General properties

nb instructions	66
nb uops	65
loop length	264
used w registers	23
used x registers	17
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.13 cycles
front end	8.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	9.17	8.83	9.00	4.50	4.50
cycles	4.50	4.50	8.00	8.00	8.00	8.00	0.00	0.00	0.00	0.00	9.17	8.83	9.00	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

10.00-25.00

Cycles summary

Front-end	8.13
Dispatch	9.17
DIV/SQRT	10.00-25.00
Overall L1	10.00-25.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Vector efficiency ratios

all	28%
load	40%
store	38%
mul	12%
add-sub	13%
fma	12%
div/sqrt	12%
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.00 cycles. At this rate:

0% of peak load performance is reached (0.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.24 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42c608

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #800]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP W22, W2, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR W1, [X0, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
LDR W0, [X0, #52]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W22, W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD W4, W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP W3, W4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W22, W3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42c9c4 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W19, W0, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB W23, W3, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
CMP W4, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.GE 42c9c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W5, W19, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MUL W24, W23, W5	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (12.5%)
STR W5, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
BL 410210 <@plt_start@+0x1f0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
BL 410240 <@plt_start@+0x220>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UDIV W7, W24, W21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	N/A
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
MSUB W8, W7, W21, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CMP W0, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CC 42c9f0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W18, W7, W6, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W9, W7, W18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
STR W9, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
CMP W18, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.CS 42c9c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W10, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR W14, [SP, #172]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (12.5%)
UDIV W11, W18, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	5-12.50	scal (12.5%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X21, X15, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X17, X24, [X20, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
ORR X25, XZR, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
MSUB W12, W11, W10, W18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD W13, W11, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X22, X28, [X20, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
SBFM X27, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (100.0%)
ORR X23, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (25.0%)
ADD W26, W12, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
SUB W13, W19, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #224	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	N/A
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
LDP X29, X30, [SP], #224	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1	scal (50.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W8, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B 42c680 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x78>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																			N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.75	5.04
▼Loop 164 - advec_cell.cpp:119-125 - exec–	0.00	0.02
○Loop 165 - advec_cell.cpp:120-125 - exec	3.74	4.89

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Matching between your function (in the source code) and the binary function

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ASM code

Vectorization

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Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code